TOPCon battery structure

Abstract

The utility model discloses a TOPCon cell structure which comprises a silicon substrate layer, the front surface of the silicon substrate layer is provided with a front surface grid line, an antireflection film layer, an alumina layer and a boron diffusion emitter layer from outside to inside in sequence, and the back surface of the silicon substrate layer is provided with a tunneling oxide layer, a doped polycrystalline silicon layer, a silicon nitride layer and a back surface grid line from inside to outside in sequence. An ultrathin silicon oxide layer is arranged in the doped polycrystalline silicon layer, and the thickness of the ultrathin silicon oxide layer is 0.8 nm to 2.0 nm. According to the TOPCon cell structure, the doping concentration of the poly layer can be effectively improved, the back passivation effect of the poly layer is further improved, back contact is improved, meanwhile, the ultra-thin silicon oxide layer structure can play a role in blocking phosphorus atoms, the phosphorus atoms are prevented from expanding and penetrating, and passing of carriers is not affected.

Description

Technical Field

[0001] The utility model belongs to the technical field of solar cells and relates to a TOPCon battery structure. Background Art

[0002] Conventional TOPCon cells have a back-side tunneling oxide passivation structure. Taking n-type cells as an example, the back side has a tunneling oxide layer and a phosphorus-doped Poly layer, which together form a tunneling oxide passivation contact structure. The tunneling oxide layer is usually thin to ensure its tunneling effect and selectively transmit carriers. When the Poly layer is doped, phosphorus atoms can easily penetrate the tunneling oxide layer into the silicon substrate, causing the tunneling oxide layer to be destroyed and lose its ability to selectively transmit carriers. Currently, this situation is mainly prevented by controlling and reducing the doping concentration, which limits the field passivation effect of the Poly layer. Utility Model Content

[0003] The technical problem to be solved by the utility model is to overcome the deficiencies of the prior art and provide a TOPCon battery structure which can effectively increase the doping concentration of the poly layer and thus improve the back passivation effect of the poly layer and improve the back contact, while preventing phosphorus atoms from diffusing through and not affecting the passage of carriers.

[0004] In order to solve the above technical problems, the utility model adopts the following technical solutions.

[0005] A TOPCon cell structure comprises a silicon substrate layer, wherein the front side of the silicon substrate layer is provided with a front gate line, an anti-reflection film layer, an aluminum oxide layer and a boron diffusion emitter layer in sequence from the outside to the inside, and the back side of the silicon substrate layer is provided with a tunneling oxide layer, a doped polysilicon layer, a silicon nitride layer and a back gate line in sequence from the inside to the outside, an ultra-thin silicon oxide layer is provided in the doped polysilicon layer, and the thickness of the ultra-thin silicon oxide layer is 0.8nm to 2.0nm, preferably 0.8nm to 1.0nm.

[0006] As a further improvement of the above technical solution, the front gate line passes through the anti-reflection film layer and the aluminum oxide layer and extends to the boron diffused emitter layer.

[0007] As a further improvement of the above technical solution, the back gate line extends through the silicon nitride layer into the doped polysilicon layer and does not pass through the ultra-thin silicon oxide layer.

[0008] As a further improvement of the above technical solution, the thickness of the tunnel oxide layer is 1.2 nm to 2.2 nm.

[0009] As a further improvement of the above technical solution, the doped polysilicon layer includes a lightly doped polysilicon layer and a heavily doped polysilicon layer arranged from the inside to the outside, and the ultra-thin silicon oxide layer is arranged between the lightly doped polysilicon layer and the heavily doped polysilicon layer. The thickness of the lightly doped polysilicon layer is 10nm to 60nm, and the thickness of the heavily doped polysilicon layer is 60nm to 150nm.

[0010] As a further improvement of the above technical solution, the thickness of the silicon nitride layer is 50nm to 90nm, and the refractive index is 1.8 to 2.2.

[0011] As a further improvement of the above technical solution, the anti-reflection film layer is a composite anti-reflection film layer, and the composite anti-reflection film layer is a silicon nitride-silicon oxynitride-silicon oxide composite anti-reflection film layer, and the thickness of the anti-reflection film layer is 50nm~100nm, and the refractive index is 1.8~2.3.

[0012] As a further improvement of the above technical solution, the thickness of the aluminum oxide layer is 2nm to 8nm.

[0013] As a further improvement of the above technical solution, the front side of the silicon base layer is a suede structure.

[0014] Compared with the prior art, the advantages of the utility model are:

[0015] In the prior art, increasing the doping concentration on the back side of the TOPCon cell may cause phosphorus atoms to over-penetrate and destroy the tunneling oxide layer. The TOPCon cell structure of the utility model can improve the ability to hinder the inward expansion of phosphorus atoms by adding an ultra-thin oxide layer in the doped polysilicon layer (Poly layer), preventing the tunneling layer from being destroyed under the condition of high-concentration phosphorus doping, thereby effectively increasing the phosphorus atom doping concentration in the Poly layer, improving the field passivation effect of the Poly layer and the back contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the structure of the TOPCon battery of Example 1 of the utility model.

[0017] Figure 2 It is a phosphorus diffusion doping curve diagram of the TOPCon battery structure of Example 1 of the utility model and the conventional TOPCon battery structure.

[0018] Legend:

[0019] 1. Front gate line; 2. Anti-reflection film layer; 3. Aluminum oxide layer; 4. Boron diffused emitter layer; 5. Tunneling oxide layer; 6. Doped polysilicon layer; 6-1. Lightly doped polysilicon layer; 6-2. Heavily doped polysilicon layer; 7. Ultra-thin silicon oxide layer; 8. Silicon nitride layer; 9. Back gate line; 10. Silicon substrate. DETAILED DESCRIPTION

[0020] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby. The materials and instruments used in the following embodiments are all commercially available.

[0021] Example 1

[0022] A TOPCon battery structure of the utility model, such as Figure 1 As shown, it includes a silicon base layer 10, and the front side of the silicon base layer 10 is provided with a front gate line 1, an anti-reflection film layer 2, an aluminum oxide layer 3, and a boron diffused emitter layer 4 in sequence from the outside to the inside, and the back side of the silicon base layer 10 is provided with a tunneling oxide layer 5, a doped polysilicon layer 6, a silicon nitride layer 8 and a back gate line 9 in sequence from the inside to the outside, and an ultra-thin silicon oxide layer 7 is provided in the doped polysilicon layer 6, and the thickness of the ultra-thin silicon oxide layer 7 is 0.8nm to 2.0nm, and 0.8nm can be selected in this embodiment.

[0023] In this embodiment, the front gate line 1 passes through the anti-reflection film layer 2 and the aluminum oxide layer 3 and extends to the boron diffused emitter layer 4 .

[0024] In this embodiment, the back gate line 9 extends through the silicon nitride layer 8 to the doped polysilicon layer 6 and does not pass through the ultra-thin silicon oxide layer 7 .

[0025] In this embodiment, the thickness of the tunnel oxide layer 5 is 1.2-2.2 nm, and 1.5 nm may be selected in this embodiment.

[0026] In this embodiment, the doped polysilicon layer 6 includes a lightly doped polysilicon layer 6-1 and a heavily doped polysilicon layer 6-2 (light and heavy are relative) arranged from the inside to the outside, and the ultra-thin silicon oxide layer 7 is arranged between the lightly doped polysilicon layer 6-1 and the heavily doped polysilicon layer 6-2. The thickness of the lightly doped polysilicon layer 6-1 is 10nm~60nm, and 30nm can be selected in this embodiment. The thickness of the heavily doped polysilicon layer 6-2 is 60nm~150nm, and 105nm can be selected in this embodiment.

[0027] In this embodiment, the thickness of the silicon nitride layer 8 is 50 nm to 90 nm, and the refractive index is 1.8 to 2.2. In this embodiment, the thickness can be 70 nm, and the refractive index is 2.16.

[0028] In this embodiment, the anti-reflection film layer 2 is a composite anti-reflection film layer, which is a silicon nitride-silicon oxynitride-silicon oxide composite anti-reflection film layer, and the thickness of the composite anti-reflection film layer is 50nm to 100nm, and the refractive index is 1.8 to 2.3. In this embodiment, the optional thickness is 80nm, and the refractive index is 2.06.

[0029] In this embodiment, the thickness of the aluminum oxide layer 3 is 2 nm to 8 nm, and in this embodiment, 4.5 nm may be selected.

[0030] In this embodiment, the front surface of the silicon base layer 10 is a suede structure.

[0031] The preparation method of the TOPCon battery structure of this embodiment includes the following steps:

[0032] (1) Texturing the silicon substrate: Place an N-type silicon substrate with a resistivity of 0.5-2.0Ω / cm, a size of 182×182mm, and a thickness of 160-180μm in a KOH / NaOH solution with a concentration of 0.5-2% for alkaline washing to remove the damaged layer, and then place it in a KOH / NaOH solution with a concentration of 1%-3% containing a texturing additive to form a velvet surface, with a velvet surface reflectivity of ≤12% and a weight reduction of 0.2-0.4g;

[0033] (2) forming a p+ emitter on the front side of the silicon substrate, performing a front boron diffusion process on the silicon substrate, and controlling the front side square resistance between 90 and 130 Ω / sq;

[0034] (3) The front side of the silicon substrate is oxidized, and the square resistance after oxidation is controlled at 220-280Ω / sq, and the thickness of BSG (borosilicate glass) is greater than 100nm;

[0035] (4) Alkaline polishing is performed on the back side of the silicon substrate, and HF with a concentration of 20% to 40% is used to remove the back BSG, so that the back side achieves an overall hydrophobic effect, and then it is placed in a KOH / NaOH solution containing an additive concentration of 2% to 5% for polishing, and the reflectivity of the polished surface is ≥40%, and the weight loss is 0.1 to 0.3 g;

[0036] (5) Using LPCVD technology to grow a tunneling oxide layer 5 + intrinsic polysilicon + ultra-thin silicon oxide layer 7 structure on the back side of the silicon substrate, the process is to first use the LPCVD process to sequentially generate a tunneling oxide layer 5 with a thickness of 1.2 to 2.2 nm, a first polysilicon layer with a thickness of 10 to 60 nm, an ultra-thin silicon oxide layer 7 with a thickness of 0.8 to 2.0 nm, and a second polysilicon layer with a thickness of 60 to 150 nm on the back side;

[0037] (6) Phosphorus diffusion is performed on the back of the tunnel oxide layer + intrinsic polysilicon + ultra-thin oxide layer structure, with a diffusion resistance of 15 to 35 Ω / sq and a doping concentration of 2×10 21 atom / cm 3 ;

[0038] (7) Perform chain de-winding cleaning + tank RCA cleaning on the silicon substrate to remove the front winding PSG / Poly, front BSG, and back PSG. The chain machine is equipped with a liquid of 5% to 20% HF to remove the PSG plated on the front. The chain cleaning should keep the BSG with a thickness of (5 to 50 nm) on the front. The alkali tank of the tank machine is KOH / NaOH with a concentration of 0.5 to 2%, and the acid tank is equipped with a liquid of 20% to 40% HF.

[0039] (8) growing a passivation layer (aluminum oxide layer 3) and an anti-reflection film layer 2 on the front side of the silicon substrate, and growing an aluminum oxide passivation film and a silicon nitride / silicon oxynitride / silicon oxide composite anti-reflection film on the front side of the silicon substrate by ALD and PECVD techniques, respectively. The AlOx film has a thickness of 2 nm to 8 nm, and the silicon nitride-silicon oxynitride-silicon oxide composite anti-reflection film has a thickness of 50 nm to 100 nm, and a refractive index of 1.8 to 2.3;

[0040] (9) growing a passivation layer on the back of the silicon substrate, growing a silicon nitride passivation layer on the back of the silicon substrate by PECVD, the silicon nitride film having a thickness of 50 to 90 nm and a refractive index of 1.8 to 2.2;

[0041] (10) Screen printing, sintering and light injection are performed on the front and back sides of the silicon substrate, and silver paste is screen printed on the front and back polysilicon areas of the silicon substrate to form front and back gate lines, followed by low-temperature sintering, with the sintering temperature controlled at 700 to 900° C. to form electrodes;

[0042] (11) Perform laser-assisted sintering on the front fine grid.

[0043] Depend on Figure 2 It can be seen that compared with the control experiment (conventional LPCVD + phosphorus diffusion doping curve, conventional TOPCon battery structure without ultra-thin silicon oxide structure), the total thickness of the poly layer (doped polysilicon layer) of the LPCVD ultra-thin silicon oxide structure + phosphorus diffusion doping curve of the utility model is 135nm. Taking the case where the ultra-thin oxide layer is located at a position of 30nm thickness (from the inside to the outside) of the poly layer, at this time, the doping concentration of the polysilicon layer at positions from 30nm to 135nm is basically the same, and the doping concentration is the highest, while the doping concentration below 30nm gradually decreases from the outside to the inside. Figure 2 The abscissa represents the depth from the outer surface of the doped polysilicon layer 6 to the inside. It can be seen that the doping concentration gradually decreases from the outside to the inside.

[0044] In the prior art, the TOPCon battery structure limits the phosphorus diffusion doping concentration to prevent the inward expansion of phosphorus sources, and cannot further improve the back passivation effect and the back contact resistance. The utility model adds an ultra-thin silicon oxide layer to the Poly layer to effectively improve the tolerance of phosphorus diffusion, thereby increasing the phosphorus diffusion doping concentration of polysilicon, effectively controlling the continued inward expansion of phosphorus atoms, and improving the passivation effect of the Poly layer and the back contact. The utility model can control the doping concentration of the polysilicon layer by controlling the thickness of the ultra-thin tunneling oxide layer and the lightly doped polysilicon layer, while matching the phosphorus diffusion temperature and the amount of source conduction.

[0045] The structure described in the utility model can also be achieved by using PECVD and other technologies to grow tunneling oxide layer / lightly doped amorphous silicon / ultra-thin silicon oxide layer / heavily doped amorphous silicon layer (PECVD process grows doped amorphous silicon, and the next process (high temperature annealing) forms polycrystalline silicon) + annealing.

[0046] The above is only a preferred embodiment of the utility model, and does not limit the utility model in any form. Although the utility model has been disclosed as above in the preferred embodiment, it is not used to limit the utility model. Any technician familiar with the field can make many possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and technical solution of the utility model, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent replacement, equivalent change and modification made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model, still fall within the scope of protection of the technical solution of the utility model.

Claims

1. A TOPCon cell structure, comprising a silicon substrate layer (10), wherein the front surface of the silicon substrate layer (10) is provided with a front gate line (1), an anti-reflection film layer (2), an aluminum oxide layer (3) and a boron diffused emitter layer (4) in sequence from the outside to the inside, characterized in that: The back side of the silicon base layer (10) is provided with a tunneling oxide layer (5), a doped polysilicon layer (6), a silicon nitride layer (8) and a back side gate line (9) in sequence from the inside to the outside, and an ultra-thin silicon oxide layer (7) is provided inside the doped polysilicon layer (6), and the thickness of the ultra-thin silicon oxide layer (7) is 0.8 nm to 2.0 nm.

2. The TOPCon battery structure according to claim 1, characterized in that: The front gate line (1) passes through the anti-reflection film layer (2) and the aluminum oxide layer (3) and extends to the boron diffusion emitter layer (4).

3. The TOPCon battery structure according to claim 1, characterized in that: The back gate line (9) passes through the silicon nitride layer (8) and extends into the doped polysilicon layer (6) without passing through the ultra-thin silicon oxide layer (7).

4. The TOPCon battery structure according to any one of claims 1 to 3, characterized in that: The thickness of the tunnel oxide layer (5) is 1.2 nm to 2.2 nm.

5. The TOPCon battery structure according to any one of claims 1 to 3, characterized in that: The doped polysilicon layer (6) comprises a lightly doped polysilicon layer (6-1) and a heavily doped polysilicon layer (6-2) arranged from the inside to the outside, the ultra-thin silicon oxide layer (7) is arranged between the lightly doped polysilicon layer (6-1) and the heavily doped polysilicon layer (6-2), the thickness of the lightly doped polysilicon layer (6-1) is 10nm to 60nm, and the thickness of the heavily doped polysilicon layer (6-2) is 60nm to 150nm.

6. The TOPCon battery structure according to any one of claims 1 to 3, characterized in that: The silicon nitride layer (8) has a thickness of 50 nm to 90 nm and a refractive index of 1.8 to 2.

2.

7. The TOPCon battery structure according to any one of claims 1 to 3, characterized in that: The anti-reflection film layer (2) is a composite anti-reflection film layer, and the composite anti-reflection film layer is a silicon nitride-silicon oxynitride-silicon oxide composite anti-reflection film layer. The thickness of the anti-reflection film layer (2) is 50 nm to 100 nm, and the refractive index is 1.8 to 2.

3.

8. The TOPCon battery structure according to any one of claims 1 to 3, characterized in that: The thickness of the aluminum oxide layer (3) is 2 nm to 8 nm.

9. The TOPCon battery structure according to any one of claims 1 to 3, characterized in that: The front surface of the silicon base layer (10) is a velvet structure.

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