Self-biased amplifier and LDO circuit

Abstract

The utility model discloses a self-biased amplifier and an LDO (Low Dropout Regulator) circuit. The amplifier comprises a first input tube, a second input tube, a load unit, an input adjusting unit and a current generating unit, the input adjusting unit is connected with a first differential input signal and the control ends of the first input tube and the second input tube. The input adjusting unit adjusts the first differential input signal to generate a second differential input signal transmitted to the control ends of the first input tube and the second input tube. The second ends of the first input tube and the second input tube are connected with the load unit, the current generating unit is connected with the first ends of the first input tube and the second input tube to generate tail current, and the current generating unit is connected with the input adjusting unit to generate bias current for the input adjusting unit based on the tail current. According to the self-biased amplifier and the LDO circuit, the structure is simple, the self-biased amplifier and the LDO circuit can work in a large voltage range, an external bias power supply is not needed, and the requirement for the power supply is low.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits, and in particular relates to a self-biased amplifier and an LDO circuit. Background Art

[0002] There are many types of amplifiers, and their uses are also very diverse. In the underlying design of integrated circuits, the demand for amplifiers runs through the entire process of chip operation. Existing amplifiers often have the requirement of input voltage range to the power rail or even beyond the power rail. The traditional solution requires the use of a folding amplifier, which has a relatively complex structure and also requires an external high-precision bias voltage and current power supply to start the amplifier. Due to reasons such as chip timing and startup sequence, when the high-precision power supply in the circuit has not yet started, the amplifier with such external bias cannot be used. If an independent voltage and current source is used to start the amplifier, it will consume too much area and power resources.

[0003] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Utility Model Content

[0004] The utility model aims to provide a self-biased amplifier and an LDO circuit, which can extend the input range to exceed the power rail and do not require external bias.

[0005] In order to achieve the above object, the utility model discloses a self-biased amplifier, comprising: a first input tube, a second input tube, a load unit, an input adjustment unit and a current generating unit;

[0006] The input adjustment unit has a first input end, a second input end, a first output end, and a second output end. The first input end and the second input end of the input adjustment unit are connected to the first differential input signal. The first output end and the second output end of the input adjustment unit are connected to the control end of the first input tube and the control end of the second input tube. The input adjustment unit is used to adjust the first differential input signal to generate a second differential input signal transmitted to the control end of the first input tube and the control end of the second input tube.

[0007] The second end of the first input tube and the second end of the second input tube are connected to the load unit, the second end of the first input tube or the second end of the second input tube forms the output end of the self-biased amplifier, the current generating unit is connected to the first end of the first input tube and the first end of the second input tube to generate a tail current, and the current generating unit is connected to the input regulating unit to generate a bias current provided to the input regulating unit based on the tail current.

[0008] In one or more embodiments of the present invention, the input regulating unit includes a first regulating unit and a second regulating unit, the input end of the first regulating unit and the input end of the second regulating unit are used to receive a first differential input signal, the output end of the first regulating unit and the output end of the second regulating unit are respectively connected to the control end of the first input tube and the control end of the second input tube, and the output end of the first regulating unit and the output end of the second regulating unit are connected to the current generating unit.

[0009] In one or more embodiments of the present invention, the first regulating unit includes a first transistor, a control end of the first transistor is used to form an input end of the first regulating unit, a first end of the first transistor is used to form an output end of the first regulating unit, and a second end of the first transistor is connected to a first voltage.

[0010] In one or more embodiments of the present invention, the second regulating unit includes a second transistor, a control end of the second transistor is used to form an input end of the second regulating unit, a first end of the second transistor is used to form an output end of the second regulating unit, and a second end of the second transistor is connected to the first voltage.

[0011] In one or more embodiments of the present invention, the load unit includes a first current mirror, a first end of the first current mirror is connected to the second end of the first input tube, and a second end of the first current mirror is connected to the second end of the second input tube.

[0012] In one or more embodiments of the present utility model, the first current mirror includes a third transistor and a fourth transistor, the control end of the third transistor, the second end of the third transistor and the control end of the fourth transistor are connected to form the first end of the first current mirror, the first end of the third transistor and the first end of the fourth transistor are connected to the first voltage, and the second end of the fourth transistor forms the second end of the first current mirror.

[0013] In one or more embodiments of the present utility model, the current generating unit includes a tail current generating unit and a second current mirror, the first end of the tail current generating unit is connected to the first end of the first input tube and the first end of the second input tube, the second end of the tail current generating unit is connected to the second current mirror, the tail current generating unit is used to generate a tail current, the second current mirror is connected to the input adjustment unit, and the second current mirror is used to mirror the tail current to generate a bias current.

[0014] In one or more embodiments of the present utility model, the tail current generating unit includes one of a resistor, an inverse ratio tube and a transistor, the first end of the resistor is connected to the first end of the first input tube and the first end of the second input tube, the second end of the resistor is connected to the second current mirror, the second end of the inverse ratio tube is connected to the first end of the first input tube and the first end of the second input tube, the first end of the inverse ratio tube is connected to the second current mirror, the control end of the inverse ratio tube is connected to the first input end of the input regulating unit or the second input end of the input regulating unit, the second end of the transistor is connected to the control end of the transistor, the first end of the first input tube and the first end of the second input tube, and the first end of the transistor is connected to the second current mirror; or

[0015] The tail current generating unit includes a plurality of resistors, inverse ratio transistors and transistors which are connected in series.

[0016] In one or more embodiments of the present invention, the second current mirror includes a fifth transistor, a sixth transistor and a seventh transistor, the control end of the fifth transistor, the second end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor are connected to the second end of the tail current generating unit, the first end of the fifth transistor, the first end of the sixth transistor and the first end of the seventh transistor are all connected to the second voltage, and the second end of the sixth transistor and the second end of the seventh transistor are respectively used to generate a bias current.

[0017] The utility model also discloses an LDO circuit, comprising the self-bias amplifier, a voltage regulator diode and a bias resistor, wherein the first end of the bias resistor is connected to a first voltage, the second end of the bias resistor is connected to a cathode of the voltage regulator diode and a first input end of an input adjustment unit of the self-bias amplifier, the output end of the self-bias amplifier is connected to a second input end of the input adjustment unit of the self-bias amplifier, and the anode of the voltage regulator diode is connected to a second voltage.

[0018] Compared with the prior art, the self-biased amplifier and LDO circuit of the utility model have a simple structure. The input range of the amplifier is expanded to exceed the power rail or be lower than the ground voltage rail through the input adjustment unit, and can operate in a larger voltage range. The bias current is generated by the current generating unit based on the tail current mirror to provide bias for the input adjustment unit, thereby achieving self-biasing without the need for external bias power supply, and the power supply requirement is low. The linearity, stability and PVT (process-voltage-temperature) characteristics of the tail current can be adjusted by adjusting the form of the tail current generating unit.

[0019] The self-biased amplifier and LDO circuit of the utility model are universal and can be used as a standard differential input and single-ended output amplifier in various circuits to cover the operating voltage range that is difficult to be covered by the existing biased amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the utility model, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 This is a circuit diagram of the self-bias amplifier in the first embodiment of the utility model.

[0022] Figure 2 This is a circuit diagram of the self-bias amplifier in the second embodiment of the present invention.

[0023] Figure 3 This is a circuit schematic diagram of the LDO circuit in the third embodiment of the present utility model. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] The words "coupled" or "connected" or "connected" in the specification include both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the present utility model, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0026] Example 1

[0027] like Figure 1 As shown, the self-biased amplifier in an embodiment of the present invention includes: a first input tube N1 , a second input tube N2 , a load unit 10 , an input adjustment unit and a current generating unit 20 .

[0028] Among them, the input adjustment unit has a first input end, a second input end, a first output end and a second output end. The first input end and the second input end of the input adjustment unit are connected to the first differential input signal, and the first output end and the second output end of the input adjustment unit are connected to the control end of the first input tube N1 and the control end of the second input tube N2. The input adjustment unit is used to adjust the first differential input signal and generate a second differential input signal transmitted to the control end of the first input tube N1 and the control end of the second input tube N2.

[0029] The second end of the first input tube N1 and the second end of the second input tube N2 are connected to the load unit 10, and the second end of the second input tube N2 is connected to the load unit 10 to form the output end of the self-biased amplifier. The current generating unit 20 is connected to the first end of the first input tube N1 and the first end of the second input tube N2 to generate a tail current Ia. The current generating unit 20 is connected to the input regulating unit to generate a bias current provided to the input regulating unit based on the tail current Ia.

[0030] like Figure 1 As shown, the input adjustment unit includes a first adjustment unit 31 and a second adjustment unit 32. The input end of the first adjustment unit 31 constitutes the first input end of the input adjustment unit, and the input end of the second adjustment unit 32 constitutes the second input end of the input adjustment unit. The input end of the first adjustment unit 31 is used to receive the first signal IN_P1, and the input end of the second adjustment unit 32 is used to receive the second signal IN_N1. The first signal IN_P1 and the second signal IN_N1 constitute a first differential input signal. The output end of the first adjustment unit 31 constitutes the first output end of the input adjustment unit, and the output end of the second adjustment unit 32 constitutes the second output end of the input adjustment unit. The output end of the first adjustment unit 31 is used to output the third signal IN_P2, and the output end of the second adjustment unit 32 is used to output the fourth signal IN_N2. The third signal IN_P2 and the fourth signal IN_N2 constitute a second differential input signal. The output end of the first regulating unit 31 and the output end of the second regulating unit 32 are respectively connected to the control end of the first input tube N1 and the control end of the second input tube N2 , and the output end of the first regulating unit 31 and the output end of the second regulating unit 32 are connected to the current generating unit 20 .

[0031] The first regulating unit 31 includes a first transistor M1, the control end of the first transistor M1 is used to form the input end of the first regulating unit 31, the control end of the first transistor M1 is used to receive the first signal IN_P1, the first end of the first transistor M1 is connected to the control end of the first input tube N1 and the current generating unit 20, the first end of the first transistor M1 is used to form the output end of the first regulating unit 31, and the first end of the first transistor M1 is used to output the third signal IN_P2. The second end of the first transistor M1 is connected to the first voltage. In one embodiment, the first voltage is the power supply voltage VDD.

[0032] The second regulating unit 32 includes a second transistor M2, the control end of the second transistor M2 is used to form an input end of the second regulating unit 32, the control end of the second transistor M2 is used to receive the second signal IN_N1, the first end of the second transistor M2 is used to form an output end of the second regulating unit 32, the first end of the second transistor M2 is connected to the control end of the second input tube N2 and the current generating unit 20, the first end of the second transistor M2 is used to output the fourth signal IN_N2, and the second end of the second transistor M2 is connected to the first voltage.

[0033] like Figure 1 As shown, the load unit 10 includes a first current mirror, a first end of the first current mirror is connected to the second end of the first input tube N1, and a second end of the first current mirror is connected to the second end of the second input tube N2.

[0034] Specifically, the first current mirror includes a third transistor M3 and a fourth transistor M4. The control end of the third transistor M3 and the second end of the third transistor M3 are connected to the control end of the fourth transistor M4 to form a first end of the first current mirror and to the second end of the first input tube N1. The first end of the third transistor M3 and the first end of the fourth transistor M4 are connected to the first voltage. The second end of the fourth transistor M4 forms a second end of the first current mirror and is connected to the second end of the second input tube N2, and serves as an output end of the self-bias amplifier to generate an output voltage Vout.

[0035] like Figure 1 As shown, the current generating unit 20 includes a tail current generating unit 21 and a second current mirror 22. The first end of the tail current generating unit 21 is connected to the first end of the first input tube N1 and the first end of the second input tube N2, and the second end of the tail current generating unit 21 is connected to the second current mirror 22. The tail current generating unit 21 is used to generate a tail current Ia. The second current mirror 22 is connected to the first regulating unit 31 and the second regulating unit 32 of the input regulating unit, and the second current mirror 22 is used to mirror the tail current Ia to generate a bias current provided to the first regulating unit 31 and the second regulating unit 32.

[0036] In one embodiment, the tail current generating unit 21 includes a resistor R1 , a first end of the resistor R1 is connected to a first end of the first input tube N1 and a first end of the second input tube N2 , and a second end of the resistor R1 is connected to the second current mirror 22 .

[0037] In other embodiments, the resistor R1 can be replaced by an inverse ratio transistor or a transistor. Specifically, the second end of the transistor is connected to the control end of the transistor and is connected to the first end of the first input tube N1 and the first end of the second input tube N2. The first end of the transistor is connected to the second current mirror 22, that is, the transistor is connected in a diode manner. The inverse ratio transistor needs to work in the linear region. The control end of the inverse ratio transistor is connected to the first input end of the input adjustment unit or the second input end of the input adjustment unit, that is, the inverse ratio transistor is controlled by the first signal IN_P1 or the second signal IN_N1. The first end of the inverse ratio transistor is connected to the second current mirror 22, and the second end of the inverse ratio transistor is connected to the first end of the first input tube N1 and the first end of the second input tube N2. The channel of the inverse ratio transistor is very long and the width is very narrow, and it can be regarded as a high-resistance resistor. The inverse ratio transistor and the transistor are N-channel MOS transistors, the first end of the inverse ratio transistor and the first end of the transistor are the source, the second end of the inverse ratio transistor and the second end of the transistor are the drain, and the control end of the inverse ratio transistor and the control end of the transistor are the gate.

[0038] Resistor R1, chamfered transistor and transistor have different characteristics. Resistor R1 has the best linearity and stability. The chamfered transistor working in the linear region has good resistance linearity, but the PVT parameters (process, voltage, temperature) vary greatly. The transistor using a diode connection is close to a constant voltage characteristic, but the PVT parameter stability is poor.

[0039] In addition, any two devices or all devices among the resistor R1, the inverse ratio transistor and the transistor may be combined with each other to form a tail current generating unit 21 in a series manner to adjust the temperature characteristics of the tail current to adapt to different application scenarios.

[0040] like Figure 1 As shown, the second current mirror 22 includes a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7. The control end of the fifth transistor M5, the second end of the fifth transistor M5, the control end of the sixth transistor M6 and the control end of the seventh transistor M7 are connected to the second end of the resistor R1 of the tail current generating unit 21, and the first end of the fifth transistor M5, the first end of the sixth transistor M6 and the first end of the seventh transistor M7 are all connected to the second voltage. In one embodiment, the second voltage is the ground voltage GND.

[0041] The second end of the sixth transistor M6 is connected to the first end of the first transistor M1 and the control end of the first input transistor N1, and the sixth transistor M6 cooperates with the fifth transistor M5 to mirror the tail current Ia to generate a first bias current Ib1 provided to the first transistor M1. The second end of the seventh transistor M7 is connected to the first end of the second transistor M2 and the control end of the second input transistor N2, and the seventh transistor M7 cooperates with the fifth transistor M5 to mirror the tail current Ia to generate a second bias current Ib2 provided to the second transistor M2.

[0042] In other embodiments, the second current mirror 22 may also adopt other forms of current mirror structures, as long as it can mirror the tail current Ia to generate a bias current provided to the first transistor M1 and the second transistor M2.

[0043] In one embodiment, the first input tube N1, the second input tube N2, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all N-channel MOS tubes, and the third transistor M3 and the fourth transistor M4 are all P-channel MOS tubes.

[0044] The first end of the first input tube N1, the first end of the second input tube N2, the first end of the first transistor M1, the first end of the second transistor M2, the first end of the third transistor M3, the first end of the fourth transistor M4, the first end of the fifth transistor M5, the first end of the sixth transistor M6, and the first end of the seventh transistor M7 are sources; the second end of the first input tube N1, the second end of the second input tube N2, the second end of the first transistor M1, the second end of the second transistor M2, the second end of the third transistor M3, the second end of the fourth transistor M4, the second end of the fifth transistor M5, the second end of the sixth transistor M6, and the second end of the seventh transistor M7 are drains; the control end of the first input tube N1, the control end of the second input tube N2, the control end of the first transistor M1, the control end of the second transistor M2, the control end of the third transistor M3, the control end of the fourth transistor M4, the control end of the fifth transistor M5, the control end of the sixth transistor M6, and the control end of the seventh transistor M7 are gates.

[0045] In one embodiment, the first transistor M1 and the second transistor M2 function as source followers, and each of the first signal IN_P1 and the second signal IN_N1 is reduced by a threshold voltage Vth to generate a third signal IN_P2 and a fourth signal IN_N2. At this time, the voltage at the first end of the first input tube N1 is IN_P1-2*Vth, and the voltage at the second end of the first input tube N1 is VDD-Vth. In order for the amplifier to work properly, it is necessary to satisfy that the voltage at the first end of the first input tube N1 is less than the voltage at the second end of the first input tube N1, and the first signal IN_P1 can be at most one Vth greater than the power supply voltage VDD. Based on a simple source follower structure, the input voltage range of the amplifier is extended beyond the power rail, which greatly enriches the application scenarios.

[0046] When the amplifier operates normally, the voltage at the first end of the resistor R1 is IN_P1-2*Vth, and the voltage at the second end of the resistor R1 is the threshold voltage Vth of the fifth transistor M5. Then, the value of the tail current Ia generated on the resistor R1 is:

[0047] (IN_P1-3*Vth) / R

[0048] Wherein, R is the resistance value of the resistor R1, and the threshold voltage Vth of each tube is considered equal. In other embodiments, the resistor R1 can be replaced by an inverse ratio tube or a transistor or any combination of a resistor, an inverse ratio tube and a transistor, and R in the above formula is the impedance of the inverse ratio tube or a transistor or any combination of a resistor, an inverse ratio tube and a transistor.

[0049] The width-to-length ratios of the sixth transistor M6, the fifth transistor M5 and the seventh transistor M7 of the second current mirror 22 are 1:N:1. The first bias current Ib1 and the second bias current Ib2 generated by mirroring the tail current Ia through the second current mirror 22 are both equal to Ia / N, thereby providing a static bias current for the first transistor M1 and the second transistor M2, so that the entire amplifier does not require external bias, which creates convenience for the application scenario of the differential input signal near the power rail.

[0050] Example 2

[0051] The circuit structure in this embodiment is different from that in Embodiment 1 in that the first input tube N1, the second input tube N2, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all P-channel MOS tubes, and the third transistor M3 and the fourth transistor M4 are all N-channel MOS tubes, that is, the types of the tubes are changed, and the positions of the current generating unit 20 and the load unit 10 are also exchanged, the first voltage is the ground voltage GND, and the second voltage is the power supply voltage VDD. For the specific circuit structure, please refer to Figure 2 shown.

[0052] Among them, the first transistor M1 and the second transistor M2 function as source followers, and respectively increase a threshold voltage Vth on the basis of the first signal IN_P1 and the second signal IN_N1 to generate a third signal IN_P2 and a fourth signal IN_N2. At this time, the voltage at the first terminal of the first input tube N1 is IN_P1+2*Vth, and the voltage at the second terminal of the first input tube N1 is GND+Vth. In order for the amplifier to work properly, it is necessary to satisfy that the voltage at the first terminal of the first input tube N1 is greater than the voltage at the second terminal of the first input tube M1, and the first signal IN_P1 can be at least one Vth less than the ground voltage GND. Based on a simple source follower structure, the input voltage range of the amplifier is extended to a range lower than the ground voltage GND, enriching the application scenarios of the input differential signal near the ground voltage GND.

[0053] When the amplifier works normally, the voltage at the first end of the resistor R1 is IN_P1+2*Vth, and the voltage at the second end of the resistor R1 is VDD-Vth. Then the value of the tail current Ia generated on the resistor R1 is:

[0054] (VDD-3*Vth-IN_P1) / R

[0055] Wherein R is the resistance value of the resistor R1. In other embodiments, the resistor R1 can be replaced by a transistor connected in reverse ratio or diode, or any combination of a resistor, a transistor connected in reverse ratio and a diode, then R in the above formula is the impedance of any combination of a transistor connected in reverse ratio or diode, or a transistor connected in reverse ratio and a diode. The reverse ratio and the transistor are P-channel MOS tubes, the first end of the reverse ratio and the first end of the transistor are the source, the second end of the reverse ratio and the second end of the transistor are the drain, and the control end of the reverse ratio and the control end of the transistor are the gate.

[0056] In one embodiment, the width-to-length ratios of the sixth transistor M6, the fifth transistor M5, and the seventh transistor M7 of the second current mirror 22 are 1:N:1, and the first bias current Ib1 and the second bias current Ib2 generated by mirroring the tail current Ia through the second current mirror 22 are both equal to Ia / N, thereby providing a static bias current for the first transistor M1 and the second transistor M2, so that the entire amplifier does not require external bias, which creates convenience for the application scenario of the differential input signal near the power rail.

[0057] In other embodiments, the first input tube N1, the second input tube N2, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 may also be replaced by triodes or other similar functional devices.

[0058] Example 3

[0059] like Figure 3 As shown, an LDO circuit includes the self-bias amplifier in embodiment 1 or embodiment 2, a voltage regulator diode D and a bias resistor Rp. The first end of the bias resistor Rp is connected to a first voltage, which is a power supply voltage VDD, the second end of the bias resistor Rp is connected to the cathode of the voltage regulator diode D and the first input end of the input adjustment unit of the self-bias amplifier, the first input end of the input adjustment unit constitutes the positive input end of the self-bias amplifier, the output end of the self-bias amplifier is connected to the second input end of the input adjustment unit of the bias amplifier, the second input end of the input adjustment unit constitutes the negative input end of the self-bias amplifier, and the anode of the voltage regulator diode D is connected to a second voltage, which is a ground voltage GND.

[0060] Since the input can be the power supply voltage VDD, preferably, the LDO circuit adopts the self-bias amplifier in the first embodiment.

[0061] The utility model also provides a chip, comprising the self-bias amplifier in embodiment 1, embodiment 2 or embodiment 3.

[0062] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

[0063] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A self-biased amplifier, characterized in that: include: A first input tube, a second input tube, a load unit, an input adjustment unit and a current generating unit; The input adjustment unit has a first input end, a second input end, a first output end, and a second output end. The first input end and the second input end of the input adjustment unit are connected to the first differential input signal. The first output end and the second output end of the input adjustment unit are connected to the control end of the first input tube and the control end of the second input tube. The input adjustment unit is used to adjust the first differential input signal to generate a second differential input signal transmitted to the control end of the first input tube and the control end of the second input tube. The second end of the first input tube and the second end of the second input tube are connected to the load unit, the second end of the first input tube or the second end of the second input tube forms the output end of the self-biased amplifier, the current generating unit is connected to the first end of the first input tube and the first end of the second input tube to generate a tail current, and the current generating unit is connected to the input regulating unit to generate a bias current provided to the input regulating unit based on the tail current.

2. The self-biased amplifier according to claim 1, wherein: The input regulating unit includes a first regulating unit and a second regulating unit, the input end of the first regulating unit and the input end of the second regulating unit are used to receive a first differential input signal, the output end of the first regulating unit and the output end of the second regulating unit are respectively connected to the control end of the first input tube and the control end of the second input tube, and the output end of the first regulating unit and the output end of the second regulating unit are connected to the current generating unit.

3. The self-bias amplifier according to claim 2, characterized in that: The first regulating unit includes a first transistor, a control end of the first transistor is used to form an input end of the first regulating unit, a first end of the first transistor is used to form an output end of the first regulating unit, and a second end of the first transistor is connected to a first voltage.

4. The self-biased amplifier according to claim 2, characterized in that: The second regulating unit includes a second transistor, a control end of the second transistor is used to form an input end of the second regulating unit, a first end of the second transistor is used to form an output end of the second regulating unit, and a second end of the second transistor is connected to a first voltage.

5. The self-bias amplifier according to claim 1, wherein: The load unit includes a first current mirror, a first end of the first current mirror is connected to the second end of the first input tube, and a second end of the first current mirror is connected to the second end of the second input tube.

6. The self-bias amplifier according to claim 5, characterized in that: The first current mirror includes a third transistor and a fourth transistor, the control end of the third transistor, the second end of the third transistor and the control end of the fourth transistor are connected to form the first end of the first current mirror, the first end of the third transistor and the first end of the fourth transistor are connected to a first voltage, and the second end of the fourth transistor forms the second end of the first current mirror.

7. The self-bias amplifier according to claim 1, wherein: The current generating unit includes a tail current generating unit and a second current mirror, wherein the first end of the tail current generating unit is connected to the first end of the first input tube and the first end of the second input tube, and the second end of the tail current generating unit is connected to the second current mirror, and the tail current generating unit is used to generate a tail current, and the second current mirror is connected to the input regulating unit, and the second current mirror is used to mirror the tail current to generate a bias current.

8. The self-bias amplifier according to claim 7, characterized in that The tail current generating unit comprises one of a resistor, an inverse ratio tube and a transistor, wherein a first end of the resistor is connected to a first end of the first input tube and a first end of the second input tube, a second end of the resistor is connected to a second current mirror, a second end of the inverse ratio tube is connected to a first end of the first input tube and a first end of the second input tube, a first end of the inverse ratio tube is connected to the second current mirror, a control end of the inverse ratio tube is connected to a first input end of the input regulating unit or a second input end of the input regulating unit, a second end of the transistor is connected to a control end of the transistor, a first end of the first input tube and a first end of the second input tube, and a first end of the transistor is connected to the second current mirror; or The tail current generating unit includes a plurality of resistors, inverse ratio transistors and transistors which are connected in series.

9. The self-bias amplifier according to claim 7, characterized in that: The second current mirror includes a fifth transistor, a sixth transistor and a seventh transistor, the control end of the fifth transistor, the second end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor are connected to the second end of the tail current generating unit, the first end of the fifth transistor, the first end of the sixth transistor and the first end of the seventh transistor are all connected to the second voltage, and the second end of the sixth transistor and the second end of the seventh transistor are respectively used to generate a bias current.

10. An LDO circuit, characterized in that: The invention comprises a self-biased amplifier, a voltage regulator diode and a bias resistor as claimed in any one of claims 1 to 9, wherein a first end of the bias resistor is connected to a first voltage, a second end of the bias resistor is connected to a cathode of the voltage regulator diode and a first input end of an input adjustment unit of the self-biased amplifier, an output end of the self-biased amplifier is connected to a second input end of the input adjustment unit of the self-biased amplifier, and an anode of the voltage regulator diode is connected to a second voltage.

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