Low-power-consumption ESD protection device

Abstract

A low power ESD protection device includes a first terminal, a second terminal, and a semiconductor switch coupled to a node between the first terminal and the second terminal and having a control input. The semiconductor switch is an N-type metal oxide semiconductor (NMOS), and in response to changing from a high impedance state to an on state, the semiconductor switch provides negative feedback such that a drain-source terminal voltage of the semiconductor switch decreases by at least 50% for a predetermined time; according to the invention, the self-bias NMOS switch is adopted, the switch can automatically bias itself under the condition of no external bias voltage, negative feedback is generated through output of the switch, and an ESD event is effectively inhibited, so that dependence on an external power supply is reduced, power consumption is reduced, and meanwhile, the chip area occupied by the circuit is reduced.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a low-power ESD protection device. Background Art

[0002] In the field of contemporary electronic engineering, with the continuous miniaturization and performance improvement of integrated circuits (ICs), the sensitivity of electronic devices to electrostatic discharge (ESD) is also increasing. ESD events may be triggered by daily contact or environmental factors, causing instantaneous high current shocks to electronic devices. This requires us to have efficient ESD protection measures to protect these precision electronic components.

[0003] However, in the prior art, ESD protection circuits rely on passive components such as Zener diodes to absorb and disperse ESD energy. Although these components perform well in the face of low-level transients, they are powerless in the face of high-level transients. They cannot withstand continuous high currents, are easily damaged, and often require larger physical sizes, which runs counter to the trend of miniaturization of electronic devices. Summary of the invention

[0004] The object of the present invention is to provide a low-power ESD protection device, which adopts a self-biased NMOS switch to achieve fast and effective ESD event response and suppression, while reducing energy consumption and occupied space.

[0005] The purpose of the present invention can be achieved through the following technical solutions: The present application provides a low-power ESD protection device, comprising: a first terminal; a second terminal; and a semiconductor switch, which is coupled to a node between the first terminal and the second terminal and has a control input, wherein the semiconductor switch is an N-type metal oxide semiconductor (NMOS), and in response to changing from a high impedance state to an on state, the semiconductor switch provides negative feedback so that the drain-source terminal voltage of the semiconductor switch is reduced by at least 50% within a predetermined time.

[0006] The semiconductor switch further comprises: a gate; and a first diffusion region connected to the control input.

[0007] Further, the semiconductor switch further includes: a second diffusion region connected to the first terminal or the second terminal; and a third diffusion region connected to a power rail other than the first terminal and the second terminal.

[0008] Furthermore, the threshold voltage of the semiconductor switch is less than zero volt (V).

[0009] Further, in response to changing from the high impedance state to the on state, the semiconductor switch applies positive feedback to the node, so that the drain-source terminal voltage of the semiconductor switch increases by at least 50% within a predetermined time.

[0010] Further, the semiconductor switch reduces the drain-source terminal voltage of the semiconductor switch from about 8V to less than about 1V within the predetermined time.

[0011] Further, the drain-source terminal voltage of the semiconductor switch increases by more than 10% of the initial peak voltage after the predetermined time.

[0012] Furthermore, it also includes a method for implementing a low-power ESD protection device for handling ESD events from an external environment, including: determining whether a signal at one or more terminals indicates an electrostatic discharge condition; and in response to determining that the signal on the one or more terminals indicates the ESD condition, activating a protection circuit associated with the IC, wherein the protection circuit includes an N-type metal oxide semiconductor switch, the NMOS switch has a control input, and wherein the NMOS switch is a self-biased NMOS switch that provides negative feedback in response to changing from a high-impedance state to an on state.

[0013] Further, the protection circuit further includes a resettable fuse, the resettable fuse being turned on during the ESD condition, and wherein the method further includes: turning off the resettable fuse after the ESD condition has passed.

[0014] Further, the protection circuit further includes a clamping circuit, and the clamping circuit is activated during the ESD condition.

[0015] The beneficial effects of the present invention are: The device uses a self-biased N-type metal oxide semiconductor (NMOS) switch as a core component, and utilizes its characteristic of being able to quickly switch from a high impedance state to a conductive state when an ESD event is detected, and through an internally generated negative feedback mechanism, effectively reduces the drain-source terminal voltage, quickly responds to and suppresses ESD shocks. This design not only achieves rapid response and effective protection to ESD events, but also significantly reduces the energy consumption of the circuit due to its low power consumption characteristics, while reducing the required chip area, meeting the requirements of miniaturization of electronic equipment. In addition, the device combines a resettable fuse and a clamping circuit to provide multiple protection mechanisms, enhance the stability and reliability of the circuit, and ensure comprehensive protection of electronic components in various environments. Through these technical solutions, the present invention achieves the multiple effects of improving ESD protection efficiency, reducing energy consumption, saving space and enhancing circuit robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0017] Figure 1A An exemplary ESD protection circuit integrated with a self-biased NMOS switch of a low-power ESD protection device provided by the present application; Figure 1B It is another exemplary ESD protection circuit integrated with a self-biased NMOS switch of a low-power ESD protection device provided by the present application; Figure 2 is an exemplary characteristic curve of a self-biased NMOS switch of a low-power ESD protection device provided in the present application; Figure 3 This is a flowchart of the steps of a method for implementing a low-power ESD protection device provided by the present application. DETAILED DESCRIPTION

[0018] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0019] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0020] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0021] ESD protection circuits are commonly used to protect sensitive electronic components from potential damage due to ESD events. As modern electronic devices become increasingly miniaturized and complex, they become more susceptible to ESD events. In addition, many electronic devices are portable, which means that users are more likely to accidentally trigger ESD events. Therefore, more effective ESD protection circuits are needed to address these problems.

[0022] Traditional ESD protection circuits rely on conventional passive components such as Zener diodes. While these traditional designs handle lower level transients well, they cannot effectively handle higher level transients because higher transient currents quickly consume the energy reserves of the Zener diode, causing it to fail prematurely. As a result, larger Zener diodes must be used to ensure that they can withstand higher transient currents for a longer period of time. Unfortunately, larger Zener diodes also take up more chip area, which is undesirable in today's highly integrated, small-size packages.

[0023] To overcome the above problems, some existing solutions have introduced active ESD protection circuits. These circuits use active devices such as transistors to improve transient performance and reduce the required chip area. Although these active ESD protection circuits solve the above problems to a certain extent, they still have several disadvantages. First, they tend to be very energy-consuming because they need to be continuously powered to remain active. Second, they usually only work effectively within a limited range, which means that they cannot fully cover all possible ESD situations. Finally, they tend to be complex, difficult to implement, and prone to errors.

[0024] In view of the above discussion, there may be a need for an improved ESD protection circuit. In particular, there is a need for a simple and reliable ESD protection circuit that does not require continuous supply of power but can still operate over a wide transient range.

[0025] In order to meet the above needs, the present invention proposes a low-power ESD protection device that can automatically bias itself without external bias, and can also generate negative feedback at its output to help suppress ESD events. In this way, it can act as a part of the ESD protection circuit and function without external bias. Moreover, due to the negative feedback capability of the ESD protection device, various types of ESD events can be more effectively dealt with.

[0026] Some basic features of the self-biased NMOS switch are as follows. The self-biased NMOS switch is a bipolar device, that is, it has two diffusion regions, both of which are connected to a common substrate. In this way, the self-biased NMOS switch can bias itself through the substrate bias instead of an external bias. In other words, the self-biased NMOS switch can generate bias through its own internal structure without any additional hardware support. In addition, the self-biased NMOS switch can generate negative feedback at its output. Specifically, when the self-biased NMOS switch is in the off state, its output generates negative feedback to help suppress ESD events. This is because it forms an inverter at its output, which can offset the positive feedback effect generated by the ESD event. In this way, the self-biased NMOS switch can help improve the robustness and reliability of the entire system.

[0027] Based on the above discussion, the self-biased NMOS switch and its applications will be described in further detail below.

[0028] Figure 1A An exemplary ESD protection circuit 100 integrated with a self-biased NMOS switch according to some embodiments is shown. As shown, the ESD protection circuit 100 includes a self-biased NMOS switch SW 102, a resettable fuse FUSE 104, and a clamping circuit CLIP 106. The self-biased NMOS switch SW 102 has three pins, namely, a drain (D), a source (S), and a gate (G). The resettable fuse FUSE 104 also has three pins, namely, an anode (A), a cathode (K), and a ground pin (GND). The clamping circuit CLIP 106 has four pins, namely, a first terminal (IN1), a second terminal (IN2), a ground pin (GND), and an output pin (OUT).

[0029] The self-biased NMOS switch SW 102 is used as the main switching element of the ESD protection circuit 100. Specifically, when the ESD protection circuit 100 detects an ESD event from the external environment, the self-biased NMOS switch SW 102 will switch to a conductive state, thereby allowing the ESD event to flow through the self-biased NMOS switch SW 102. In this state, the self-biased NMOS switch SW 102 will generate negative feedback at its output to help suppress the ESD event, so that the drain-source terminal voltage of the self-biased NMOS switch is reduced by at least 50% within a predetermined time. Due to this negative feedback effect, the self-biased NMOS switch SW 102 can better cope with various types of ESD events without having to worry about overload or failure.

[0030] The self-biased NMOS switch further comprises: a gate; and a first diffusion region connected to the control input; a second diffusion region connected to the first terminal or the second terminal; and a third diffusion region connected to a power rail other than the first terminal and the second terminal.

[0031] The resettable fuse FUSE 104 is used as a backup mechanism for the ESD protection circuit 100. Specifically, when the ESD protection circuit 100 detects an ESD event from the external environment, the resettable fuse FUSE 104 will also switch to the on state, so that the ESD event flows through the resettable fuse FUSE 104. In this state, the resettable fuse FUSE 104 will absorb most of the ESD energy and convert it into heat. Once the ESD event is over, the resettable fuse FUSE 104 can be closed again and prepared to deal with the next ESD event again. In this way, the resettable fuse FUSE 104 can provide a low-cost and efficient way to deal with sudden ESD events.

[0032] The clamp circuit CLIP 106 serves as an additional layer of protection for the ESD protection circuit 100. Specifically, when the ESD protection circuit 100 detects an ESD event from the external environment, the clamp circuit CLIP 106 will switch to a conductive state, thereby allowing the ESD event to flow through the clamp circuit CLIP 106. In this state, the clamp circuit CLIP 106 will limit the maximum voltage level of the ESD event, thereby protecting downstream components from excessive stress. In this way, the clamp circuit CLIP 106 can provide a cost-effective and easy-to-implement way to enhance the robustness and stability of the overall system.

[0033] Figure 1B Another exemplary ESD protection circuit 200 integrated with a self-biased NMOS switch according to some embodiments is shown. As shown, the ESD protection circuit 200 includes a self-biased NMOS switch SW 202, a resettable fuse FUSE 204, and a clamping circuit CLIP 206. The self-biased NMOS switch SW 202 has three pins, namely, a drain (D), a source (S), and a gate (G). The resettable fuse FUSE 204 also has three pins, namely, an anode (A), a cathode (K), and a ground pin (GND). The clamping circuit CLIP 206 has four pins, namely, a first terminal (IN1), a second terminal (IN2), a ground pin (GND), and an output pin (OUT).

[0034] The self-biased NMOS switch SW 202 is used as the main switching element of the ESD protection circuit 200. Specifically, when the ESD protection circuit 200 detects an ESD event from the external environment, the self-biased NMOS switch SW 202 will switch to a conductive state, thereby allowing the ESD event to flow through the self-biased NMOS switch SW 202. In this state, the self-biased NMOS switch SW 202 will generate negative feedback at its output to help suppress the ESD event. Due to this negative feedback effect, the self-biased NMOS switch SW 202 can better cope with various types of ESD events without having to worry about overload or failure.

[0035] The resettable fuse FUSE 204 is used as a backup mechanism for the ESD protection circuit 200. Specifically, when the ESD protection circuit 200 detects an ESD event from the external environment, the resettable fuse FUSE 204 will also switch to the on state, so that the ESD event flows through the resettable fuse FUSE 204. In this state, the resettable fuse FUSE 204 will absorb most of the ESD energy and convert it into heat. Once the ESD event is over, the resettable fuse FUSE 204 can be closed again and prepared to deal with the next ESD event again. In this way, the resettable fuse FUSE 204 can provide a low-cost and efficient way to deal with sudden ESD events.

[0036] The clamp circuit CLIP 206 serves as an additional layer of protection for the ESD protection circuit 200. Specifically, when the ESD protection circuit 200 detects an ESD event from the external environment, the clamp circuit CLIP 206 will switch to a conductive state, thereby allowing the ESD event to flow through the clamp circuit CLIP 206. In this state, the clamp circuit CLIP 206 will limit the maximum voltage level of the ESD event, thereby protecting downstream components from excessive stress. In this way, the clamp circuit CLIP 206 can provide a cost-effective and easy-to-implement way to enhance the robustness and stability of the overall system.

[0037] Figure 2 An exemplary characteristic curve of a self-biased NMOS switch according to some embodiments is shown. As shown in the figure, the horizontal axis represents the gate voltage VG of the self-biased NMOS switch, and the vertical axis represents the drain-source terminal voltage VD-SD of the self-biased NMOS switch. The dotted line represents the threshold voltage VT of the self-biased NMOS switch, and the solid line represents the output characteristic curve of the self-biased NMOS switch.

[0038] When the gate voltage VG of the self-biased NMOS switch is less than the threshold voltage VT, the self-biased NMOS switch is in the cut-off state. In this state, the drain-source terminal voltage VD-SD of the self-biased NMOS switch is very high and close to infinity. When the gate voltage VG of the self-biased NMOS switch is greater than the threshold voltage VT, the self-biased NMOS switch enters the saturation state. In this state, the drain-source terminal voltage VD-SD of the self-biased NMOS switch begins to decrease and eventually reaches a minimum value. It is worth noting that the drain-source terminal voltage VD-SD of the self-biased NMOS switch will experience a negative feedback effect throughout the process, which means that the drain-source terminal voltage VD-SD of the self-biased NMOS switch will gradually decrease over time. It is this negative feedback effect that makes the self-biased NMOS switch an ideal choice for ESD protection circuits.

[0039] Figure 3 A method for implementing a low-power ESD protection device according to some embodiments is shown, a method 300 for handling ESD events from an external environment. Method 300 may start from block 302, where it is determined whether a signal at one or more terminals indicates an ESD condition. If so, block 304 is executed, where a protection circuit associated with the IC is activated. The protection circuit includes an N-type metal oxide semiconductor (NMOS) switch having a control input. The NMOS switch is a self-biased NMOS switch that provides negative feedback in response to changing from a high impedance state to a conductive state. Then, method 300 ends.

[0040] If the signal at one or more terminals of the IC does not indicate an ESD condition, the method 300 returns to block 302 to continue monitoring the signal at one or more terminals of the IC. An advantage of this method is that the protection circuit can be activated even in the absence of an external bias. This can make the design of the protection circuit more flexible and allow the protection circuit to be used in a wider range of environments.

[0041] This device combines a self-biased NMOS switch, a resettable fuse, and a clamp circuit to provide comprehensive ESD protection. The following are the possible ESD protection effects of this design in different working environments: Dry environment: In dry environments, static electricity accumulation is more common. The self-biased NMOS switch can respond quickly to ESD events and quickly turn on through its negative feedback effect, thereby providing a low impedance path to safely dissipate ESD energy; Wet Environments: Although the ESD risk may be relatively low in wet environments, the device’s resettable fuse can serve as an effective backup mechanism, absorbing and converting ESD energy even in wet conditions, preventing potential damage; Temperature Varying Environments: Temperature fluctuations may affect the performance of some components. However, the negative feedback characteristics of the self-biased NMOS switch provide a degree of adaptability that helps maintain stable ESD protection performance even under temperature variations; High-frequency operating environment: In high-frequency operating environments, the clamping circuit can quickly limit the voltage peak, protect the IC from the voltage shock generated by ESD events, and ensure signal integrity; High vibration or shock environments: In these environments, physical shock may induce ESD events. The fast response of the self-biased NMOS switch and the high absorption capacity of the resettable fuse can jointly protect the IC from ESD damage caused by mechanical shock; Electromagnetic Interference (EMI) Environment: In an EMI environment, ESD protection devices need to accurately distinguish between ESD events and EMI. The collaborative work of the self-biased NMOS switch and the clamping circuit can effectively suppress real ESD events while avoiding interference with normal signal transmission; Outdoor environment: The outdoor environment may face more extreme temperature and humidity conditions. The thermal response characteristics of the resettable fuse and the voltage limiting function of the clamp circuit can jointly protect the IC from the impact of outdoor environmental changes; Industrial environment: ESD sources in industrial environments may be more diverse and frequent. The adaptive negative feedback of the self-biased NMOS switch and the reuse capability of the self-resettable fuse can provide continuous protection, reducing equipment failure and downtime caused by ESD; Laboratory or manufacturing environment: In these more strictly controlled environments, the integrated design of ESD protection devices can ensure the safety of ICs throughout the manufacturing and testing process; Daily Use Environment: For end users, this ESD protection device can provide adequate protection against ESD events that may be encountered in daily use, such as static electricity generated from walking on carpet.

[0042] In general, the design goal of this ESD protection device is to provide an adaptable and reliable solution to meet the ESD protection needs in various working environments.

[0043] The low-power ESD protection device proposed in the present invention improves the limitations of the traditional ESD protection circuit mentioned in the background technology. In traditional ESD protection circuits, passive components such as Zener diodes are usually relied on. Although these components can handle lower levels of transients, they cannot effectively cope with higher levels of transients. In addition, in order to withstand higher transient currents, larger Zener diodes are required, which not only occupies more chip area, but is also not conducive to the miniaturization and integration of integrated circuits. In order to overcome these problems, the present invention adopts a self-biased NMOS switch, which can automatically bias itself in the absence of an external bias, and generate negative feedback through its output, effectively suppressing ESD events, thereby reducing dependence on external power supplies, reducing power consumption, and reducing the chip area occupied by the circuit.

[0044] Through the low-power ESD protection circuit design, the ESD protection device achieves several key effects. First, the self-biased NMOS switch can respond to and suppress various types of ESD events more effectively due to its negative feedback mechanism, which improves the reliability of the protection circuit. Second, compared with traditional passive components, the self-biased NMOS switch reduces the demand for chip area while providing the same or better protection level, which helps to achieve the miniaturization of integrated circuits. In addition, the device also includes a resettable fuse and a clamping circuit as a backup and additional protection mechanism, which further improves the protection capability against ESD events. The resettable fuse can absorb and convert ESD energy during an ESD event and can automatically recover after the event, while the clamping circuit limits the maximum voltage level of the ESD event to protect downstream components from excessive stress. Overall, this low-power ESD protection device provides a cost-effective and easy-to-implement solution that enhances the robustness and stability of electronic systems and is suitable for various working environments, including dry, humid, temperature changes and other different conditions.

[0045] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A low power consumption ESD protection device, characterized in that: First terminal; Second terminal; and a semiconductor switch coupled to a node between the first terminal and the second terminal and having a control input, wherein the semiconductor switch is an N-type metal oxide semiconductor (NMOS) and, in response to changing from a high impedance state to a conductive state, the semiconductor switch provides negative feedback such that a drain-source terminal voltage of the semiconductor switch is reduced by at least 50% within a predetermined time.

2. A low power consumption ESD protection device according to claim 1, characterized in that: The semiconductor switch further comprises: a gate; and a first diffusion region connected to the control input.

3. A low power consumption ESD protection device according to claim 2, characterized in that: The semiconductor switch further includes a second diffusion region connected to the first terminal or the second terminal, and a third diffusion region connected to a power rail other than the first terminal and the second terminal.

4. A low power consumption ESD protection device according to claim 3, characterized in that: The threshold voltage of the semiconductor switch is less than zero volt (V).

5. The low power consumption ESD protection device according to claim 1, characterized in that: The semiconductor switch also applies positive feedback to the node in response to changing from the high impedance state to the conductive state, so that the drain-source terminal voltage of the semiconductor switch increases by at least 50% within a predetermined time.

6. A low power consumption ESD protection device according to claim 1, characterized in that: The semiconductor switch causes a drain-source terminal voltage of the semiconductor switch to drop from about 8V to less than about 1V within the predetermined time.

7. A low power consumption ESD protection device according to claim 1, characterized in that: The drain-source terminal voltage of the semiconductor switch increases by more than 10% of the initial peak voltage after the predetermined time.

8. A low-power ESD protection device according to any one of claims 1 to 7, which is a method for implementing a low-power ESD protection device, used to handle ESD events from an external environment, characterized in that: include: determining whether a signal at one or more terminals indicates an electrostatic discharge condition; and activating a protection circuit associated with the IC in response to determining that the signal on the one or more terminals indicates the ESD condition, wherein the protection circuit includes an N-type metal oxide semiconductor switch, the NMOS switch having a control input, and wherein the NMOS switch is a self-biased NMOS switch that provides negative feedback in response to changing from a high-impedance state to a conductive state.

9. The method for implementing a low power consumption ESD protection device according to claim 8, characterized in that: The protection circuit also includes a resettable fuse that turns on during the ESD condition, and wherein the method further includes turning off the resettable fuse after the ESD condition has passed.

10. The method for implementing a low power consumption ESD protection device according to claim 8, characterized in that: The protection circuit also includes a clamp circuit that is activated during the ESD condition.

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