Ultra-low noise LDO (Low Dropout Regulator) with programmable current limit and quick start

Abstract

The invention relates to the technical field of power management in an integrated circuit, in particular to an ultra-low noise LDO with a programmable current limit and quick start. Comprising a reference current generating circuit, an RC filter, a first negative feedback loop, a control resistor, a comparison control circuit, a programmable current limiting circuit, a sampling tube MP0 and a first switch current source. The first negative feedback loop comprises an error amplifier, a buffer stage and a power tube MP1; before the LDO is started, current limit programming is achieved; after current limit programming is finished, the LDO starts to start, an LDO quick start control signal is generated through the programmable current limit circuit, an extra charging path is provided for the RC filter circuit through the constant current source, and quick start of the ultralow-noise LDO is achieved; when the output voltage of the LDO is close to a preset value, the quick starting circuit is closed; according to the LDO, the current limit is adjustable, the protection capability to the rear stage is improved, and the reliability of the whole system is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of power management in integrated circuits, and in particular to an ultra-low noise LDO with programmable current limit and fast startup. Background Art

[0002] Low-dropout linear regulators (LDOs) are a very important type of device in the field of power management technology. LDOs are widely used in battery-powered portable electronic systems and communication equipment due to their small size, simple application, and no output voltage ripple. As the signal frequency processed by portable electronic devices continues to increase and the power supply voltage continues to decrease, power supply noise has an increasingly greater impact on the performance of electronic devices, especially for noise-sensitive RF and analog devices such as phase-locked loops (PLLs) and high-precision A / D converters, whose performance is particularly affected by power supply noise. The output noise of ultra-low noise LDOs is extremely low. For example, the output noise of some ultra-low noise LDOs can be as low as a few microvolts (uV) or even lower than the nanovolt (nV) level. Therefore, ultra-low noise LDOs have become an important direction for the development of LDO technology.

[0003] LDO is composed of a bandgap reference, an error amplifier, a power tube, and a feedback resistor. The LDO output voltage noise includes the bandgap reference voltage noise, the error amplifier equivalent input voltage noise, the feedback resistor thermal noise, and the like. In order to reduce the LDO output voltage noise, an external capacitor and an on-chip resistor are usually used to form a low-pass filter to obtain a lower reference voltage noise. At the same time, a unit gain negative feedback structure is used to eliminate the influence of the feedback resistor thermal noise on the output voltage noise, and to suppress the amplification of the reference voltage noise and the error amplifier equivalent input voltage noise. In the prior art, the on-chip large resistor and the off-chip large capacitor extend the reference voltage establishment time, resulting in a contradiction between the LDO startup time and the output voltage noise. In addition, the existing high-current LDO usually has a high current limit and cannot be adjusted. The excessively high current limit leads to a reduction in the protection capability of the LDO to the subsequent stage under the application condition of a small output load current, which affects the reliability of the overall system. Summary of the invention

[0004] The object of the present invention is to provide an ultra-low noise LDO with programmable current limit and fast startup. Before the LDO is started, the current limit is programmed by comparing the voltage value of the output voltage feedback port with the reference voltage. The control signal for current limit programming is locked afterwards, and the current limit is configured. The current limit is determined by the resistance values ​​of two resistors connected to the output voltage feedback port. By selecting different resistance values, the current limit can be flexibly configured according to the usage scenario. After the current limit programming is completed, the LDO starts to start, and an LDO fast startup control signal is generated by reusing one of the current limit configuration comparators. An additional charging path is provided for the RC filter circuit through a constant current source to achieve ultra-low noise LDO fast startup. When the LDO output voltage is close to a preset value, the fast startup circuit is turned off. The fast startup time is determined by the ratio of the resistance values ​​of the two resistors connected to the output voltage feedback port. The ratio of the resistance values ​​can be reasonably selected according to the preset output voltage value to achieve ultra-low noise LDO fast startup.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] In a first aspect of the present invention, the present invention provides an ultra-low noise LDO with programmable current limit and fast startup, the LDO comprising:

[0007] A reference current generating circuit, an RC filter, a first negative feedback loop, a control resistor, a comparison control circuit, a programmable current limit circuit, a sampling tube MP0, and a first switching current source; the first negative feedback loop includes an error amplifier, a buffer stage and a power tube MP1; wherein:

[0008] The output end of the reference current generating circuit is connected to the inverting input end of the error amplifier and the negative end of the first switch current source, and is also connected to the positive end of the RC filter as the external port VSET, and the negative end of the RC filter is grounded; the non-inverting input end of the error amplifier is connected to the drain of the power tube MP1 and the input end VOUT of the programmable current limit circuit, and is also connected to the positive end of the control resistor as the external port VOUT, the control end of the control resistor is connected to the output voltage feedback port VO_FB, and the negative end of the control resistor is grounded; the output end of the error amplifier is connected to the input end of the buffer stage and the output end of the programmable current limit circuit; the output end of the buffer stage is connected to the gates of the sampling tube MP0 and the power tube MP1, the sources of the MP0 and MP1 are connected to the input voltage port VIN, the drain of the MP0 is connected to the input end VCS of the programmable current limit circuit, the other two input ends of the programmable current limit circuit are connected to the output ends VLIMIT1 and VLIMIT2 of the comparison control circuit, the input end of the comparison control circuit is connected to the output voltage feedback port VO_FB, the other output end VS of the comparison control circuit is connected to the control end of the first switch current source, and the positive end of the first switch current source is connected to the input power supply port VIN.

[0009] Furthermore, the reference current generating circuit is composed of amplifiers AMP1, AMP2, NMOS tube M0, PMOS tube M1 and resistors R0, R1 and R2. The in-phase input terminal of the amplifier AMP1 is connected to the internal bandgap reference voltage VREF, the inverting input terminal of the amplifier AMP1 is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of M0 tube, the negative terminal of the resistor R0 is grounded, the drain of M0 tube is connected to the negative terminal of the resistor R1 and the in-phase input terminal of the amplifier AMP2, the inverting input terminal of the amplifier AMP2 is connected to the negative terminal of the resistor R2 and the source of M1 tube, the positive terminals of the resistors R1 and R2 are connected to the input power supply VIN, the output terminal of the amplifier AMP2 is connected to the gate of M1 tube, and the drain of M1 tube serves as the output port VSET.

[0010] Furthermore, the programmable current limit circuit includes a current limit configuration circuit, an LDO output current sampling circuit and a clamping circuit; the current limit configuration circuit changes the first control point VA voltage in response to the programmable current limit control signals VLIMIT1 and VLIMT2 output by the comparison control circuit; the LDO output current sampling circuit changes the second control point VB voltage in response to the sampling voltage VCS of the sampling tube MP0; the clamping circuit outputs the clamping voltage VEA in response to the first control point VA voltage and the second control point VB voltage to achieve overcurrent protection.

[0011] Furthermore, the programmable current limit circuit includes bias current sources IB1 to IB5, PMOS tubes M2 to M6, resistors R3 to R7, NMOS tube M7 and amplifier AMP3. The positive ends of bias current sources IB3, IB4 and IB5 are connected together and connected to the input voltage VIN, the negative end of IB3 is connected to the drain of tube M2, the drain of tube M3 and the positive end of resistor R3, and is also connected to the inverting input end of AMP3, the source of tube M2 is connected to the negative end of IB4, and the gate is connected to the programmable current limit control signal VLIMIT2, the source of tube M3 is connected to the negative end of IB5, and the gate is connected to the programmable current limit control signal VLIMIT1; the positive end of resistor R4 is connected to the current sampling signal VCS, the negative end is connected to the source of tube M4 and the source of tube M6, and the gate of tube M4 is connected to the drain The two poles are short-circuited, and connected to the positive end of the bias current source IB1 and the gate of the M5 tube. The source of the M5 tube is connected to the negative end of the resistor R5, and the drain is connected to the gate of the M6 ​​tube and the positive end of the bias current source IB2. The positive end of the resistor R5 is connected to the output voltage VOUT. The negative ends of the bias current sources IB1 and IB2 are connected to the ground. The drain of the M6 ​​tube is connected to the positive end of the resistor R6 and the in-phase input end of AMP3, and the negative end of R6 is grounded; the output of the amplifier AMP3 is connected to the gate of the M7 tube, the drain of M7 is connected to the negative end of the resistor R7, the positive end of R7 is connected to the input voltage VIN, and the source of the M7 tube is connected to the output end of the error amplifier.

[0012] Furthermore, the resistance of the resistor R6 is smaller than the resistance of the resistor R3.

[0013] Furthermore, the comparison control circuit is composed of comparators COMP1, COMP2, two-input NAND gates NAND1, NAND2, NAND3, RS flip-flops FF1, FF2, current source IS2 and switch tube S2. COMP1 is connected to the in-phase input terminal of COMP2, and is connected to the negative terminal of the second switch current source, and is also connected to the output voltage feedback port VO_FB. The control terminal of the second switch current source is connected to CK1, the positive terminal of the second switch current source is connected to the input voltage VIN, the inverting input terminals of COMP1 and COMP2 are connected to the internal reference voltages VREF1 and VREF2 respectively, the output terminal of COMP1 is connected to the first input terminal of NAND1, the output terminal of COMP2 is connected to the first input terminal of NAND2 and the first input terminal of NAND3, the second input terminal of NAND1 and the second input terminal of NAND2 are connected to the control signal CK2, the second input terminal of NAND3 is connected to the control signal CK4, the output of NAND3 is the control signal VS of the first switch current source, the output of NAND1 is connected to the R terminal of the RS trigger FF1, the output of NAND2 is connected to the R terminal of the RS trigger FF2, the S terminals of FF1 and FF2 are both connected to the control signal CK3, the output of FF1 is the programmable current control signal VLIMIT2, and the output of FF2 is the programmable current control signal VLIMIT1.

[0014] In a second aspect of the present invention, the present invention further provides an ultra-low noise LDO with programmable current limit and fast startup, specifically comprising:

[0015] When the current limit programming starts, the LDO is not started, the output voltage VOUT is pulled down to the ground, and the comparison control circuit generates a bias current. The bias current generates a voltage on the control resistor through the output voltage feedback terminal VO_FB. The voltage generates current limit control signals VLIMIT1 and VLIMT2 through the input terminal of the comparison control circuit. The programmable current limit circuit completes the configuration of the LDO current limit according to VLIMIT1 and VLIMT2.

[0016] After the current limit programming is completed, the LDO starts to start, the output current ISET of the reference current generating circuit generates a reference voltage at the VSET port, the voltage of the VSET port rises, and the LDO output voltage VOUT follows the voltage rise of the VSET port. At the same time, VOUT is output to the voltage feedback port VO_FB as a feedback voltage after being divided by the control resistor. The feedback voltage and the reference voltage are compared through the programmable current limit circuit. During the output voltage establishment process, the feedback voltage VO_FB is less than the reference voltage, and the comparator output VS controls the first switch current source to work. The first switch current source and the output current ISET of the reference current generating circuit charge the VSET terminal at the same time. The voltage of the VSET terminal rises, and the LDO output voltage follows the VSET terminal voltage to rise rapidly. When the output voltage VOUT approaches the preset value, the feedback voltage VO_FB is greater than the reference voltage, the comparison control circuit output VS flips, the first switch current source does not work, the LDO fast establishment process ends, and the reference current generating circuit output current ISET continues to charge the RC filter until the voltage of the VSET terminal reaches the preset value. At this time, the LDO completes the startup and the output voltage stabilizes at the preset value.

[0017] Beneficial effects of the present invention:

[0018] The ultra-low noise LDO proposed in the present invention has the characteristics of fast startup and programmable current limit. Before the LDO is started, the current limit is programmed by comparing the output voltage feedback port voltage with the reference voltage. The current limit is determined by the resistance values ​​of two resistors connected to the output voltage feedback port. By selecting different resistance values, the current limit can be flexibly configured according to the usage scenario. During the LDO startup process, an LDO fast startup control signal is generated by multiplexing the current limit configuration comparator. The fast startup time is determined by the ratio of the two resistance values ​​connected to the output voltage feedback port. The ratio of the resistance values ​​can be reasonably selected according to the preset output voltage value to achieve the ultra-low noise LDO fast startup. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of an ultra-low noise LDO structure with programmable current limit and fast startup according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of an ultra-low noise LDO structure with programmable current limit and fast startup according to a preferred embodiment of the present invention;

[0021] Figure 3 A schematic diagram of a reference current generating circuit according to an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of a programmable current limit circuit according to an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of a comparison control circuit according to an embodiment of the present invention;

[0024] Figure 6 This is a timing diagram of control signals of a comparison control circuit according to an embodiment of the present invention;

[0025] Figure 7 This is a simulation diagram of the programmable current limit of an ultra-low noise LDO according to an embodiment of the present invention;

[0026] Figure 8 This is a simulation diagram of the ultra-low noise LDO startup according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] It should be noted that, since the embodiments of the present invention focus on the current or voltage of the signal, the current or voltage input / output of each module / unit / device is used for description herein, and it should be understood by those skilled in the art that, in fact, the input / output of each module / unit / device is a signal. In order to make the technical means and creative features of the present invention easy to understand, the present invention is further described in conjunction with the accompanying drawings.

[0029] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0030] In an embodiment of the present invention, an ultra-low noise LDO with programmable current limit and fast startup is specifically implemented in the present invention, and its structural block diagram is as follows: Figure 1 As shown, the ultra-low noise LDO includes a reference current generating circuit, an RC filter, a first negative feedback loop, a control resistor, a comparison control circuit, a programmable current limit circuit, a sampling tube MP0, and a first switching current source; the first negative feedback loop includes an error amplifier, a buffer stage and a power tube MP1; wherein:

[0031] The output end of the reference current generating circuit is connected to the inverting input end of the error amplifier and the negative end of the first switch current source, and is also connected to the positive end of the RC filter as the external port VSET, and the negative end of the RC filter is grounded; the non-inverting input end of the error amplifier is connected to the drain of the power tube MP1 and the input end VOUT of the programmable current limit circuit, and is also connected to the positive end of the control resistor as the external port VOUT, the control end of the control resistor is connected to the output voltage feedback port VO_FB, and the negative end of the control resistor is grounded; the output end of the error amplifier is connected to the input end of the buffer stage and the output end of the programmable current limit circuit; the output end of the buffer stage is connected to the gates of the sampling tube MP0 and the power tube MP1, the sources of the MP0 and MP1 are connected to the input voltage port VIN, the drain of the MP0 is connected to the input end VCS of the programmable current limit circuit, the other two input ends of the programmable current limit circuit are connected to the output ends VLIMIT1 and VLIMIT2 of the comparison control circuit, the input end of the comparison control circuit is connected to the output voltage feedback port VO_FB, the other output end VS of the comparison control circuit is connected to the control end of the first switch current source, and the positive end of the first switch current source is connected to the input power supply port VIN.

[0032] In a preferred embodiment of the present invention, an ultra-low noise LDO with programmable current limit and fast startup is specifically implemented in the present invention, and its structural block diagram is as follows Figure 2 As shown, the RC filter includes a capacitor CS and a resistor RS; the control resistor includes a resistor RF1 and a resistor RF2; and the first switch current source includes a switch tube S1 and a current source IS1.

[0033] In some embodiments, the control resistor includes external resistors RF1 and RF2, the positive end of the resistor RF2 is connected to the external port VOUT, the negative end of the resistor RF2 is connected to the positive end of the resistor RF1 and is connected to the output voltage feedback port VO_FB as the control end of the control resistor, and the negative end of the resistor RF1 is grounded.

[0034] In some embodiments of the present invention, the specific implementation process of an ultra-low noise LDO with programmable current limit and fast startup of the present invention can be as follows:

[0035] When the current limit programming starts, the LDO is not started, the output voltage VOUT is pulled down to the ground, and the comparison control circuit generates a bias current. The bias current generates a voltage on the control resistor through the output voltage feedback terminal VO_FB. The voltage generates current limit control signals VLIMIT1 and VLIMT2 through the input terminal of the comparison control circuit. The programmable current limit circuit completes the configuration of the LDO current limit according to VLIMIT1 and VLIMT2.

[0036] After the current limit programming is completed, the LDO starts to start, the output current ISET of the reference current generating circuit generates a reference voltage at the VSET port, the voltage of the VSET port rises, and the LDO output voltage VOUT follows the voltage rise of the VSET port. At the same time, VOUT is output as a feedback voltage to the voltage feedback port VO_FB after being divided by the control resistor. The feedback voltage and the reference voltage are compared through the programmable current limit circuit. During the output voltage establishment process, the feedback voltage VO_FB is less than the reference voltage, and the comparator output VS controls the first switch current source to work. The first switch current source and the output current ISET of the reference current generating circuit charge the VSET terminal at the same time. The voltage of the VSET terminal rises, and the LDO output voltage follows the voltage rise of the VSET terminal. The LDO starts. When the output voltage VOUT is close to the preset value, the feedback voltage VO_FB is greater than the reference voltage, and the comparison control circuit output VS flips, the first switch current source does not work, and the LDO fast establishment process ends. The output current ISET of the reference current generating circuit continues to charge the capacitor CS of the RC filter until the voltage of the VSET terminal reaches the preset value. At this time, the LDO completes the startup and the output voltage stabilizes at the preset value.

[0037] In the embodiment of the present invention, the preset value is ISET*RS, where RS is the resistance of the RC filter.

[0038] In a preferred embodiment of the present invention, a specific implementation process of an ultra-low noise LDO with programmable current limit and fast startup may also include the following:

[0039] The reference current generation circuit outputs a stable reference current ISET, which flows through an external RC filter composed of RS and CS to generate a low-noise reference voltage at the VSET terminal. The negative feedback loop composed of the error amplifier, buffer stage and power tube MP1 clamps the output voltage VOUT at the VSET terminal voltage. The LDO output voltage value can be set by selecting the RS resistance value, and the LDO output voltage noise can be reduced by increasing the CS capacitance value. Before the LDO starts, the output voltage VOUT is pulled down to ground by the built-in bleeder tube, and the comparison control circuit generates a bias current. This current generates a voltage on the resistor (RF1 / / RF2) through the output voltage feedback terminal VO_FB. This voltage is used as the common input terminal of the two comparators with different flip thresholds in the comparison control circuit to generate current limit control signals VLIMIT1 and VLIMT2. The programmable current limit circuit completes the configuration of the LDO current limit according to VLIMIT1 and VLIMT2. The working principle of the LDO current limit is to mirror the current in the power tube through the sampling tube MP0, and to achieve overcurrent protection by clamping the error amplifier output VEA when the LDO is overcurrent. After the current limit programming is completed, the LDO starts to start, and the output current ISET of the reference current generating circuit generates a voltage at the VSET port. Due to the large capacitance of the capacitor CS, VSET rises slowly, and the LDO output voltage VOUT follows VSET to rise. At the same time, VOUT is fed back to the output voltage feedback port VO_FB after being divided by resistors RF2 and RF1. The feedback voltage is compared with the reference voltage through the reused COMP2 comparator. During the output voltage establishment process, the feedback voltage VO_FB is less than the reference voltage, and the comparator output VS controls the switch tube S1 to turn on. The current source IS1 and the output current ISET of the reference current generating circuit charge the VSET terminal at the same time. The voltage at the VSET terminal rises rapidly, and the LDO output voltage follows the VSET terminal voltage to rise rapidly. When the output voltage VOUT approaches the preset value ISET*RS, the feedback voltage VO_FB is greater than the reference voltage, the comparator output VS flips, the switch tube S1 is disconnected, and the LDO fast establishment process ends. The output current ISET of the reference current generating circuit continues to charge the capacitor CS until the voltage at the VSET terminal reaches the preset value ISET*RS. At this time, the LDO is started up and the output voltage is stabilized at ISET*RS. By properly configuring the resistors RF2 and RF1, the LDO can exit the fast startup phase when the output voltage approaches ISET*RS, thereby achieving fast startup of the LDO while avoiding output voltage overshoot.

[0040] It can be understood that COMP1 and COMP2 are used to generate current limit configuration signals VLIMIT1 and VLIMT2 before the LDO is started. After the configuration is completed, the LDO is quickly started by multiplexing COMP2.

[0041] In some embodiments of the present invention, a reference current generating circuit of the present invention is implemented as follows: Figure 3 As shown, the reference current generating circuit includes amplifiers AMP1, AMP2, NMOS tube M0, PMOS tube M1 and resistors R0, R1, R2; the in-phase input terminal of the amplifier AMP1 is connected to the internal bandgap reference voltage VREF, the inverting input terminal of the amplifier AMP1 is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of M0 tube, the negative terminal of resistor R0 is grounded, the drain of M0 tube is connected to the negative terminal of resistor R1 and the in-phase input terminal of the amplifier AMP2, the inverting input terminal of the amplifier AMP2 is connected to the negative terminal of resistor R2 and the source of M1 tube, the positive terminals of resistors R1 and R2 are connected to the input power supply VIN, the output terminal of the amplifier AMP2 is connected to the gate of M1 tube, and the drain of M1 tube serves as the output port VSET.

[0042] It should be noted that, in this embodiment, the amplifier AMP1, the NMOS tube M0 and the resistor R0 form a second negative feedback loop, the voltage at the inverting input terminal of the amplifier AMP1 is clamped at VREF, and the current flowing through the tube M0 is:

[0043]

[0044] Resistors R1, R2, amplifier AMP2, M1, and external resistors RS and CS connected to the VSET terminal form a negative feedback circuit, which outputs a stable current ISET at the VSET terminal. Assuming that resistor R1 = R2, the output current ISET of the reference current generating circuit is:

[0045]

[0046] After LDO is stable, the output voltage is:

[0047]

[0048] In some embodiments of the present invention, the programmable current limit circuit includes a current limit configuration circuit, an LDO output current sampling circuit and a clamping circuit; the current limit configuration circuit changes the first control point VA voltage in response to the programmable current limit control signals VLIMIT1 and VLIMT2 output by the comparison control circuit; the LDO output current sampling circuit changes the second control point VB voltage in response to the sampling voltage VCS of the sampling tube MP0; the clamping circuit outputs the clamping voltage VEA in response to the first control point VA voltage and the second control point VB voltage to achieve overcurrent protection.

[0049] In a preferred embodiment of the present invention, a programmable current limit circuit of the present invention is implemented as follows Figure 4As shown, the programmable current limit circuit includes bias current sources IB1~IB5, PMOS tubes M2~M6, resistors R3~R7, NMOS tube M7 and amplifier AMP3; the positive ends of bias current sources IB3, IB4 and IB5 are connected together and connected to the input voltage VIN, the negative end of IB3 is connected to the drain of M2 tube, the drain of M3 tube and the positive end of resistor R3, and is also connected to the inverting input end of AMP3, the source of M2 tube is connected to the negative end of IB4, and the gate is connected to the programmable current limit control signal VLIMIT2, the source of M3 tube is connected to the negative end of IB5, and the gate is connected to the programmable current limit control signal VLIMIT1; the positive end of resistor R4 is connected to the voltage VIN, and the negative end of IB4 ... The current sampling signal VCS is connected to the negative end of the M4 tube source and the M6 ​​tube source. The M4 tube gate and drain are short-circuited, and connected to the positive end of the bias current source IB1 and the M5 tube gate. The M5 tube source is connected to the negative end of the resistor R5, and the drain is connected to the M6 ​​tube gate and the positive end of the bias current source IB2. The positive end of the resistor R5 is connected to the output voltage VOUT. The negative ends of the bias current sources IB1 and IB2 are connected to the ground. The drain of the M6 ​​tube is connected to the positive end of the resistor R6 and the in-phase input end of AMP3, and the negative end of R6 is grounded; the output of the amplifier AMP3 is connected to the M7 tube gate, the M7 drain is connected to the negative end of the resistor R7, the positive end of R7 is connected to the input voltage VIN, and the M7 tube source is connected to the error amplifier output VEA.

[0050] It should be noted that the current sources IB3 to IB5, PMOS tubes M2, M3 and resistor R3 constitute a current limit configuration circuit. The programmable current limit control signals VLIMIT1 and VLIMT2 output by the comparison control circuit control the on and off of tubes M2 and M3, thereby changing the voltage at point VA. Resistors R4 to R6, PMOS tubes M4 to M6 and bias current sources IB1 and IB2 constitute an LDO output current sampling circuit. As the current of the power tube increases, the current of the sampling tube also gradually increases, and the sampling voltage VCS gradually increases, which leads to a decrease in the gate voltage of tube M6, an increase in the current in tube M6, and an increase in the voltage at point VB. When the LDO output current increases to a point where the voltage at point VB is greater than the voltage at point VA, the clamping circuit formed by amplifier AMP3, PMOS tube M7 and resistor R7 clamps the VEA output by the error amplifier, preventing VEA from continuing to decrease, thereby avoiding a continuous increase in the LDO output current. If the width-to-length ratio of the sampling tube MP0 to the power tube MP1 is 1:k, when the LDO output current reaches the current limit, the voltage at point VB is equal to the voltage at point VA, so:

[0051]

[0052] Where ILIMIT is the LDO current limit. If IB3=2IB4=2IB5=2I, and the programmable current limit control signals VLIMIT1 and VLIMT2 are both high, the LDO has the minimum overcurrent limit:

[0053]

[0054] When the programmable current limit control signal VLIMIT1 is low and VLIMT2 is high, the LDO overcurrent limit is:

[0055]

[0056] When the programmable current limit control signals VLIMIT1 and VLIMT2 are both low, the LDO has a maximum overcurrent limit:

[0057]

[0058] Since R3 is much larger than R6, the minimum current limit of LDO is about 50% of the maximum current limit, and the intermediate current limit is 75% of the maximum current limit. Figure 5 As shown, the comparison control circuit includes comparators COMP1 and COMP2, two-input NAND gates NAND1, NAND2, and NAND3, RS triggers FF1 and FF2, and a second switch current source; COMP1 is connected to the in-phase input terminals of COMP2, and is connected to the negative terminal of the second switch current source, and is also connected to the output voltage feedback port VO_FB, the control terminal of the second switch current source is connected to CK1, the positive terminal of the second switch current source is connected to the input voltage VIN, the inverting input terminals of COMP1 and COMP2 are connected to the internal reference voltages VREF1 and VREF2 respectively, and the output terminal of COMP1 is connected to the first input terminal of NAND1. The COMP2 output is connected to the first input of NAND2 and the first input of NAND3, the second input of NAND1 and the second input of NAND2 are connected to the control signal CK2, the second input of NAND3 is connected to the control signal CK4, the NAND3 output is the control signal VS of the first switch current source, the NAND1 output is connected to the R end of the RS trigger FF1, the NAND2 output is connected to the R end of the RS trigger FF2, the S ends of FF1 and FF2 are both connected to the control signal CK3, the FF1 output is the programmable current control signal VLIMIT2, and the FF2 output is the programmable current control signal VLIMIT1. The second switch current source includes a switch tube S2 and a current source IS2.

[0059] In the preferred embodiment of the present invention, in order to realize multi-level programmable, the present embodiment can also Figure 4 Add a branch similar to M2 and M3 in the programmable current limit circuit and use VLIMT3 to control it. Figure 5 The comparison control circuit shown is increased with a comparator COMP3, a two-input NAND gate NAND4, an RS trigger FF3, etc., and an output VLIMT3 to achieve 4 levels of programmability; similarly, more levels of programmability can be achieved by continuing to increase.

[0060] In some embodiments of the present invention, the timing relationship of the control signals CK1-CK4 is as follows: Figure 6 Before the current limit programming starts, VREF1 and VREF2 have been established, and VREF1 is greater than VREF2, CK1 is high, switch tube S2 is disconnected, VO_FB voltage is 0, CK2 and CK3 are low, RS flip-flops FF1 and FF2 have R terminals high, S terminals low, RS flip-flops are set, outputs VLIMIT1 and VLIMT2 are high, CK4 is low, and output VS is high; after the current limit programming starts, CK3 becomes high, CK1 becomes low, switch tube S2 is turned on, and the current limit programming starts. The current source IS2 generates a voltage through the output voltage feedback port VO_FB, and its value is IS2*(RF1 / / RF2). This voltage is compared with two different reference voltages VREF1 and VREF2, and outputs VCOMP1 and VCOMP2. During the period when CK2 is at a high level, the comparator output is transmitted to the R terminal of the RS trigger. When the comparator output is at a high level, the voltage at the R terminal is at a low level, the RS trigger output is reset, and the programmable current limit control signal becomes a low level. When the comparator output is at a low level, the voltage at the R terminal is at a high level, and the RS trigger The output of the trigger is maintained, and the programmable current limit control signal is maintained at a high level. Thereafter, CK2 becomes a low level, and the R terminal of the RS trigger returns to a high level. The RS trigger state is locked, and then CK1 becomes a high level, and the switch tube S2 is disconnected to complete the current limit programming. During the current limit programming process, VS continues to maintain a high level. After the current limit programming is completed, CK4 becomes a high level, VS is controlled by VCOMP2, and the LDO starts to start. The voltage at the VO_FB terminal is obtained by dividing the LDO output voltage. During the LDO establishment process, the voltage at the VO_FB terminal is lower than VREF2, and the comparator output COMP2 is a low level. Since CK4 is a high level at this time, VS is controlled by VCOMP2 to output a high level, the switch tube S1 is turned on, and the current source IS1 charges the VSET port. The voltage at the VSET terminal rises rapidly, and the LDO output voltage rises with the voltage at the VSET terminal. When the output voltage approaches the preset value ISET*RS, the voltage at the output voltage feedback port VO_FB is higher than VREF2, the output of the comparator COMP2 flips, VS becomes a low level, the switch tube S1 is disconnected, and the LDO fast startup process ends. Before the current limit programming is completed, VS is controlled by CK4 output and is also high level, and the switch tube S1 is turned on. However, since the LDO startup enable signal has not arrived at this time, the current source IS1 has not generated current. Therefore, IS1 has no effect on the port VSET during this process, and the voltage at the VSET terminal is 0.

[0061] Figure 7The present invention is an ultra-low noise LDO programmable current limit simulation diagram. By changing the resistance values ​​of external resistors RF1 and RF2, three levels of programmable current limits are achieved, and the current limits are 1.44A, 1.1A, and 0.77A respectively. The intermediate current limit is approximately 75% of the maximum current limit, and the minimum current limit is approximately 50% of the maximum current limit.

[0062] Figure 8 The present invention is an ultra-low noise LDO fast startup simulation diagram. By changing the ratio of the resistance values ​​of the external resistors RF1 and RF2, the LDO fast establishment time can be set. During the LDO fast establishment process, the switch tube S1 controls the signal VS to a high level, and the current source IS1 charges the VSET terminal. The fast establishment process ends after VS becomes a low level.

[0063] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An ultra-low noise LDO with programmable current limit and fast startup, characterized in that: include: A reference current generating circuit, an RC filter, a first negative feedback loop, a control resistor, a comparison control circuit, a programmable current limit circuit, a sampling tube MP0, and a first switching current source; the first negative feedback loop includes an error amplifier, a buffer stage and a power tube MP1; wherein: The output end of the reference current generating circuit is connected to the inverting input end of the error amplifier and the negative end of the first switch current source, and is also connected to the positive end of the RC filter as an external port VSET, and the negative end of the RC filter is grounded; the non-inverting input end of the error amplifier is connected to the drain of the power tube MP1 and the input end VOUT of the programmable current limit circuit, and is also connected to the positive end of the control resistor as an external port VOUT, the control end of the control resistor is connected to the output voltage feedback port VO_FB, and the negative end of the control resistor is grounded; the output end of the error amplifier is connected to the input end of the buffer stage and the output end of the programmable current limit circuit; The output end of the buffer stage is connected to the gates of the sampling tube MP0 and the power tube MP1, the sources of the MP0 and MP1 are connected to the input voltage port VIN, the drain of the MP0 is connected to the input end VCS of the programmable current limit circuit, the other two input ends of the programmable current limit circuit are connected to the output ends VLIMIT1 and VLIMIT2 of the comparison control circuit, the input end of the comparison control circuit is connected to the output voltage feedback port VO_FB, the other output end VS of the comparison control circuit is connected to the control end of the first switch current source, and the positive end of the first switch current source is connected to the input power supply port VIN.

2. The ultra-low noise LDO with programmable current limit and fast startup according to claim 1, characterized in that: The reference current generating circuit comprises amplifiers AMP1, AMP2, NMOS tube M0, PMOS tube M1 and resistors R0, R1 and R2; the in-phase input terminal of the amplifier AMP1 is connected to the internal bandgap reference voltage VREF, the inverting input terminal of the amplifier AMP1 is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of M0 tube, the negative terminal of the resistor R0 is grounded, the drain of M0 tube is connected to the negative terminal of the resistor R1 and the in-phase input terminal of the amplifier AMP2, the inverting input terminal of the amplifier AMP2 is connected to the negative terminal of the resistor R2 and the source of M1 tube, the positive terminals of the resistors R1 and R2 are connected to the input power supply VIN, the output terminal of the amplifier AMP2 is connected to the gate of M1 tube, and the drain of M1 tube serves as the output port VSET.

3. The ultra-low noise LDO with programmable current limit and fast startup according to claim 1, characterized in that: The programmable current limit circuit includes a current limit configuration circuit, an LDO output current sampling circuit and a clamping circuit; the current limit configuration circuit changes the voltage of the first control point VA in response to the programmable current limit control signals VLIMIT1 and VLIMT2 output by the comparison control circuit; the LDO output current sampling circuit changes the voltage of the second control point VB in response to the sampling voltage VCS of the sampling tube MP0; the clamping circuit outputs a clamping voltage VEA in response to the voltage of the first control point VA and the voltage of the second control point VB to achieve overcurrent protection.

4. An ultra-low noise LDO with programmable current limit and fast startup according to claim 1 or 3, characterized in that: The programmable current limit circuit includes bias current sources IB1-IB5, PMOS tubes M2-M6, resistors R3-R7, NMOS tube M7 and amplifier AMP3; the positive ends of bias current sources IB3, IB4 and IB5 are connected together and connected to the input voltage VIN, the negative end of IB3 is connected to the drain of tube M2, the drain of tube M3 and the positive end of resistor R3, and is also connected to the inverting input end of AMP3, the source of tube M2 is connected to the negative end of IB4, and the gate is connected to the programmable current limit control signal VLIMIT2, the source of tube M3 is connected to the negative end of IB5, and the gate is connected to the programmable current limit control signal VLIMIT1; the positive end of resistor R4 is connected to the current The negative end of the sampling signal VCS is connected to the source of the M4 tube and the source of the M6 ​​tube. The gate and drain of the M4 tube are short-circuited, and are connected to the positive end of the bias current source IB1 and the gate of the M5 tube. The source of the M5 tube is connected to the negative end of the resistor R5, and the drain is connected to the gate of the M6 ​​tube and the positive end of the bias current source IB2. The positive end of the resistor R5 is connected to the output voltage VOUT, the negative ends of the bias current sources IB1 and IB2 are connected to the ground, the drain of the M6 ​​tube is connected to the positive end of the resistor R6 and the in-phase input end of the AMP3, and the negative end of R6 is grounded; the output of the amplifier AMP3 is connected to the gate of the M7 tube, the drain of the M7 is connected to the negative end of the resistor R7, the positive end of R7 is connected to the input voltage VIN, and the source of the M7 tube is connected to the output end of the error amplifier.

5. The ultra-low noise LDO with programmable current limit and fast startup according to claim 4, characterized in that: The resistance of the resistor R6 is smaller than the resistance of the resistor R3.

6. The ultra-low noise LDO with programmable current limit and fast startup according to claim 1, characterized in that: The comparison control circuit includes comparators COMP1 and COMP2, two-input NAND gates NAND1, NAND2, and NAND3, RS triggers FF1 and FF2, and a second switch current source; COMP1 is connected to the in-phase input terminal of COMP2, and is connected to the negative terminal of the second switch current source, and is also connected to the output voltage feedback port VO_FB, the control terminal of the second switch current source is connected to CK1, the positive terminal of the second switch current source is connected to the input voltage VIN, the inverting input terminals of COMP1 and COMP2 are connected to the internal reference voltages VREF1 and VREF2 respectively, and the output terminal of COMP1 is connected to the first input terminal of NAND1 end, the COMP2 output end is connected to the first input end of NAND2 and the first input end of NAND3, the second input end of NAND1 and the second input end of NAND2 are connected to the control signal CK2, the second input end of NAND3 is connected to the control signal CK4, the NAND3 output is the control signal VS of the first switching current source, the NAND1 output is connected to the R end of the RS trigger FF1, the NAND2 output is connected to the R end of the RS trigger FF2, the S ends of FF1 and FF2 are both connected to the control signal CK3, the FF1 output is the programmable current control signal VLIMIT2, and the FF2 output is the programmable current control signal VLIMIT1.

7. The ultra-low noise LDO with programmable current limit and fast startup according to claim 1, characterized in that: The control resistor includes external resistors RF1 and RF2, the positive end of the resistor RF2 is connected to the external port VOUT, the negative end of the resistor RF2 is connected to the positive end of the resistor RF1 and is connected to the output voltage feedback port VO_FB as the control end of the control resistor, and the negative end of the resistor RF1 is grounded.

8. The ultra-low noise LDO with programmable current limit and fast startup according to claim 7, characterized in that: The resistance values ​​of the resistor RF1 and the resistor RF2 are adjustable.

9. An ultra-low noise LDO with programmable current limit and fast startup, characterized in that: When the current limit programming starts, the LDO is not started, the output voltage VOUT is pulled down to the ground, and the comparison control circuit generates a bias current. The bias current generates a voltage on the control resistor through the output voltage feedback terminal VO_FB. The voltage generates current limit control signals VLIMIT1 and VLIMT2 through the input terminal of the comparison control circuit. The programmable current limit circuit completes the configuration of the LDO current limit according to VLIMIT1 and VLIMT2. After the current limit programming is completed, the LDO starts to start, the output current ISET of the reference current generating circuit generates a reference voltage at the VSET port, the voltage of the VSET port rises, and the LDO output voltage VOUT follows the voltage rise of the VSET port. At the same time, VOUT is output to the voltage feedback port VO_FB as a feedback voltage after being divided by the control resistor. The feedback voltage and the reference voltage are compared through the programmable current limit circuit. During the output voltage establishment process, the feedback voltage VO_FB is less than the reference voltage, and the comparator output VS controls the first switch current source to work. The first switch current source and the output current ISET of the reference current generating circuit charge the VSET terminal at the same time. The voltage of the VSET terminal rises, and the LDO output voltage follows the VSET terminal voltage to rise rapidly. When the output voltage VOUT approaches the preset value, the feedback voltage VO_FB is greater than the reference voltage, the comparison control circuit output VS flips, the first switch current source does not work, the LDO fast establishment process ends, and the reference current generating circuit output current ISET continues to charge the RC filter until the voltage of the VSET terminal reaches the preset value. At this time, the LDO completes the startup and the output voltage stabilizes at the preset value.

10. The ultra-low noise LDO with programmable current limit and fast startup according to claim 9, characterized in that: The preset value is ISET*RS, where RS is the resistance of the RC filter.

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