Chip testing device and chip

Abstract

The utility model relates to a chip testing device and a chip. The chip testing device comprises a testing machine, at least two testing plates and a switching circuit board, the test machine is used for testing the to-be-tested chip at a preset temperature; the test board is used for bearing a to-be-tested chip, carrying out functional test and electrical test on the borne to-be-tested chip at different temperatures, and feeding back a test result to the test machine; the switching circuit board is connected with the test machine and the at least two test boards, a plurality of multiplexing pins are arranged on the switching circuit board, and the multiplexing pins are connected with the at least two test boards and used for transmitting test signals provided by the test machine to the at least two connected test boards in parallel. According to the chip testing device, multiple chips to be tested can be tested at the same time, the testing time is shortened, the testing efficiency is improved, the testing time cost and labor cost are reduced, the overall project progress is accelerated, and the machine utilization rate is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing device and a chip. Background Art

[0002] After the chip is packaged, the function and electrical parameter tests of the packaged chip will be carried out through the coordinated use of sorting machines and testing machines to ensure that the function and performance indicators of each semiconductor chip leaving the factory can meet the design specifications.

[0003] At present, during the finished product testing phase of flash memory (eFLASH) chips, high temperature, low temperature and normal temperature tests are carried out. However, when conducting high temperature and low temperature tests on the chip, it takes a certain amount of waiting time for the chip to fully reach the preset temperature, and after the test is completed, it takes another certain amount of waiting time for the temperature to return to normal temperature. Moreover, only one chip sample can be tested at a time, which increases the test time, increases labor costs, and even delays the progress of the entire project. Utility Model Content

[0004] Based on this, it is necessary to provide a chip testing device and chip to address the problems in the above-mentioned background technology, so as to improve the efficiency of chip testing, reduce time cost and labor cost, speed up the overall project progress, and effectively improve the utilization rate of the testing machine.

[0005] To achieve the above-mentioned purpose and other purposes, according to various embodiments of the present application, the first aspect of the present application provides a chip testing device, including a testing machine, at least two testing boards and a transfer circuit board; the testing machine is used to test the chip to be tested at a preset temperature; a test board is used to carry a chip to be tested, perform functional tests and electrical tests on the carried chip to be tested at different temperatures, and also to feed back the test results to the testing machine; the transfer circuit board is connected to the testing machine and at least two test boards, and a plurality of multiplexed pins are arranged on the transfer circuit board, and the multiplexed pins are connected to at least two test boards, and are used to transmit the test signals provided by the testing machine in parallel to the at least two connected test boards.

[0006] The above-mentioned chip testing device tests the chip to be tested at a preset temperature through a test machine; through at least two test boards, one test board is used to carry a chip to be tested, and the functional test and electrical test of the carried chip to be tested at different temperatures are performed on the carried chip to be tested, and is also used to feed back the test results to the test machine, and judge whether the chip to be tested meets the expected requirements according to the test results; through a transfer circuit board connected to the test machine and at least two test boards, a plurality of multiplexed pins are arranged on the transfer circuit board, and the multiplexed pins are connected to at least two test boards, and are used to transmit the test signal provided by the test machine in parallel to at least two connected test boards, the transfer circuit board connects the test machine and multiple test boards to form a test loop, which can realize the testing of multiple chips to be tested at the same time, thereby improving the test efficiency. At present, the relevant chip testing device can only perform three-temperature tests (high temperature, low temperature and normal temperature) on a single chip to be tested. After the temperature rise / cooling of the test environment reaches the preset temperature, it is necessary to wait for a certain time for the chip to fully reach the preset temperature. After the test of the chip to be tested is completed, the test environment needs a certain recovery time to change from high temperature / low temperature to normal temperature, and then the chip to be tested is replaced, which prolongs the overall test time, reduces the test efficiency and prolongs the progress of the project. The chip testing device in the embodiment of the present application is provided with a plurality of multiplexing pins on the adapter circuit board, and the test machine and the plurality of test boards are connected through the multiplexing pins to form a test loop. The test machine transmits the test signal to the corresponding pins of the adapter circuit board in sequence, so that after the temperature reaches the preset requirement, the test of the plurality of chips to be tested is performed, and the multiplexing of a single pin is realized. After the test is completed, the test results of the plurality of chips to be tested are fed back to the test machine. By testing the plurality of chips to be tested at the same time, the test time is reduced, the test efficiency is improved, the time cost and labor cost of the test are reduced, the overall progress of the project is accelerated, and the utilization rate of the machine is effectively improved.

[0007] In some embodiments, the adapter circuit board includes a power pin area and an input / output pin area that are distributed at intervals; the power pin area includes a plurality of power pads arranged in rows and columns along a first direction and a second direction; the input / output pin area includes a plurality of input / output pads arranged in rows and columns along a first direction and a second direction.

[0008] In some embodiments, each row of power pads includes first unit areas distributed in sequence along a first direction, and a first unit area includes excitation pads, detection pads and ground pads distributed in sequence along the first direction; the excitation pads are used to receive and transmit power signals, the detection pads are used to detect whether the amplitude of the power signal on the excitation pad is within a corresponding amplitude range, and the ground pads are used for grounding; in adjacent first unit areas along the first direction, the ground pad of one first unit area is adjacent to the excitation pad of another first unit area.

[0009] In some embodiments, power pads adjacent to each other along a first direction are used to connect to the same chip under test; and power pads adjacent to each other along a second direction are used to connect to different chips under test.

[0010] In some embodiments, the input / output pin area includes a second unit area arranged in rows and columns along a first direction and a second direction; the second unit area includes a plurality of signal pads arranged in sequence along the first direction and a plurality of ground pads arranged in sequence along the first direction; a plurality of signal pads constitute a signal pad row, and a plurality of ground pads constitute a ground pad row; the signal pads are used to receive and transmit test signals, and the ground pads are used for grounding; in adjacent second unit areas along the second direction, the signal pad row of one second unit area is adjacent to the ground pad row of another second unit area.

[0011] In some embodiments, a second unit region is used to connect the same chip under test; different second unit regions are used to connect different chips under test.

[0012] In some embodiments, the chip testing device further includes a temperature control cover, which is disposed corresponding to the test board and is used to perform at least one of the following steps while covering the chip to be tested on the corresponding test board:

[0013] After heating the chip to be tested to a preset first temperature at room temperature, a temperature test is performed on the chip to be tested;

[0014] After cooling the chip to be tested to a preset second temperature at room temperature, a temperature test is performed on the chip to be tested;

[0015] A temperature test is performed on the chip to be tested at room temperature; the first temperature is greater than the temperature at room temperature, and the temperature at room temperature is greater than the second temperature.

[0016] In some embodiments, the test machine includes a signal lead-out board, which includes multiple test pads arranged in rows and columns along the first direction and the second direction, and different test pads are used to be connected to different pins on the adapter circuit board via wires.

[0017] In some embodiments, the test machine includes a display, and the display is used to display the test results, and the test results include at least one of a voltage test result, a current test result, a frequency test result, and a functional test result.

[0018] A second aspect of the present application provides a chip that is tested using any of the above-mentioned chip testing devices.

[0019] The chip in the above embodiment is tested by a chip testing device. Multiple chips can be placed in a test board at the same time. The test machine and multiple test boards are connected through multiple multiplexing pins on the adapter circuit board to form a test loop. The test machine transmits the test signal to the corresponding pins of the adapter circuit board in sequence, so that multiple chips are tested after the temperature reaches the preset requirements. After the test is completed, the test results of the multiple chips are fed back to the tester. By testing multiple chips to be tested at the same time, the test time is reduced, the test efficiency is improved, the time cost and labor cost of the test are reduced, the overall progress of the project is accelerated, and the machine utilization rate is effectively improved.

[0020] The unexpected technical effect that the present application can produce is: the chip testing device is provided with multiple multiplexed pins on the adapter circuit board, and the test machine and multiple test boards are connected through the multiplexed pins to form a test loop. The test machine transmits the test signal to the corresponding pins of the adapter circuit board in sequence, so as to test multiple chips to be tested after the temperature reaches the preset requirements, thereby realizing the multiplexing of a single pin, and after the test is completed, the test results of the multiple chips to be tested are fed back to the test machine. By testing multiple chips to be tested at the same time, the test time is reduced, the test efficiency is improved, the time cost and labor cost of the test are reduced, the overall progress of the project is accelerated, and the machine utilization rate is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of a structural block diagram of a chip testing device provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of a connection structure of a chip testing device provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of transmission of test signals and test results in a chip testing device provided in an embodiment of the present application;

[0025] Figure 4a A schematic diagram of the structure of a power pin area provided in an embodiment of the present application;

[0026] Figure 4b A schematic diagram of an input / output pin block provided in an embodiment of the present application;

[0027] Figure 5A schematic diagram of a test flow of a chip testing device provided in an embodiment of the present application.

[0028] Description of reference numerals:

[0029] 100, chip testing device; 110, testing machine; 111, signal lead-out board; 1111, testing pad; 120, testing board; 121 / 1 / 2 / 3 / 4 / 5 / 6, chip to be tested; 1211, chip pin; 130, transfer circuit board; 131, multiplexing pin; 132, power pin area; 1321, power pad; 1322, first unit area; 133, input / output pin area; 1331, input / output pad; 1332, second unit area; S1, excitation pad; F, detection pad; G, ground pad; S2, signal pad. DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the application content of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0033] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0034] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0035] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0036] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0037] At present, in the reliability test process of flash memory products, in the finished product testing stage, the test machine and sample board are connected by wires, and then the sample to be tested is inserted into the sample board to form a test loop for three-temperature (high temperature, low temperature and normal temperature) testing. Both high temperature testing and low temperature testing are carried out through independent high and low temperature equipment to independently heat up / cool down a single sample to be tested. After the test environment temperature reaches the preset value, the test machine starts testing.

[0038] During each high temperature / low temperature test, when the environmental cover of the equipment is lowered to cover the sample to be tested and reaches the preset ambient temperature, it is necessary to wait for about 3 minutes (the sample fully reaches the target temperature) before starting the test. After the test is completed, the sample to be tested needs to be cooled to room temperature (25°C) for about 30 to 50 seconds before the environmental cover of the equipment can be raised to prevent human damage to the chip at high temperature, or frosting damage to the chip and test sample due to temperature difference at low temperature. After taking out the sample to be tested, put in the next sample to be tested, repeat the test steps, continue testing, put in the next sample to be tested, repeat the above steps, and continue testing.

[0039] In this way, only one sample can be heated / cooled or cooled independently at a time, and only one sample can be tested at a time, which greatly increases the time cost of finished product testing and the labor cost of manually replacing samples. In addition, when using parallel testing, it will cause a great deal of waste and redundancy of the test machine channel resources, significantly reduce the efficiency of finished product testing, and greatly extend the overall progress of the project.

[0040] Based on this, please refer to Figure 1-Figure 3The embodiment of the present application provides a chip testing device 100, including a testing machine 110, a testing board 120 and a transfer circuit board 130; the testing machine 110 is used to test a chip to be tested 121 at a preset temperature; a testing board 120 is used to carry a chip to be tested 121, perform functional tests and electrical tests on the carried chip to be tested 121 at different temperatures, and also to feed back the test results to the testing machine 110; the transfer circuit board 130 is connected to the testing machine 110 and at least two testing boards 120, and a plurality of multiplexing pins 131 are arranged on the transfer circuit board 130, and the multiplexing pins 131 are connected to at least two testing boards 120, and are used to transmit the test signal provided by the testing machine 110 to the at least two connected testing boards 120 in parallel.

[0041] In some embodiments, please refer to Figure 1-Figure 3The chip testing device 100 tests the chip to be tested 121 at a preset temperature through a test machine 110; through at least two test boards 120, one test board 120 is used to carry a chip to be tested 121, and the functional test and electrical test of the carried chip to be tested 121 at different temperatures are performed, and it is also used to feed back the test results to the test machine 110, and judge whether the chip to be tested 121 meets the expected requirements according to the test results; through a transfer circuit board 130 connected to the test machine 110 and at least two test boards 120, a plurality of multiplexing pins 131 are arranged on the transfer circuit board 130, and the multiplexing pins 131 are connected to at least two test boards 120, and are used to transmit the test signal provided by the test machine 110 to the at least two connected test boards 120 in parallel, and the transfer circuit board 130 connects the test machine 110 and multiple test boards 120 to form a test loop, which can realize the simultaneous testing of multiple chips to be tested 121, thereby improving the test efficiency. At present, the relevant chip testing equipment can only perform three-temperature tests (high temperature, low temperature and normal temperature) on a single chip to be tested. After the test environment is heated up / cooled down to the preset temperature, it is necessary to wait for a certain period of time for the chip to fully reach the preset temperature. After the chip to be tested is tested, the test environment changes from high temperature / low temperature to normal temperature, which requires a certain recovery time, and then the chip to be tested is replaced. This prolongs the overall test time, reduces the test efficiency and prolongs the project progress. The chip testing device 100 in the embodiment of the present application is provided with a plurality of multiplexed pins 131 on the adapter circuit board 130, and the test machine 110 and the plurality of test boards 120 are connected through the multiplexed pins 131 to form a test loop. The test machine 110 transmits the test signal to the corresponding pins of the adapter circuit board 130 in sequence, so that the plurality of chips to be tested 121 are tested after the temperature reaches the preset requirement, thereby realizing the multiplexing of a single pin, and after the test is completed, the test results of the plurality of chips to be tested 121 are fed back to the test machine 110. By testing the plurality of chips to be tested 121 at the same time, the test time is reduced, the test efficiency is improved, the time cost and labor cost of the test are reduced, the overall progress of the project is accelerated, and the utilization rate of the machine is effectively improved.

[0042] In some embodiments, please refer to Figure 2 The test machine 110 includes a signal lead-out board 111, and the signal lead-out board 111 includes a plurality of test pads 1111 arranged in rows and columns along a first direction (for example, an OX direction) and a second direction (for example, an OY direction), and different test pads 1111 are used to be respectively connected to different multiplexed pins 131 on the adapter circuit board 130 via wires; the chip to be tested 121 includes a plurality of chip pins 1211, and the plurality of chip pins 1211 of a chip to be tested 121 are respectively inserted into corresponding connection holes (not shown) of a test board 120 to implement testing of the chip to be tested 121.

[0043] In some embodiments, please refer to Figure 2-Figure 3 By soldering a reuse pin 131 on the adapter circuit board 130, the test pad 1111 on the test machine 110 is connected to the reuse pin 131 on the adapter circuit board 130, and then connected to multiple independent test boards 120 through the reuse pin 131 of the adapter circuit board 130, a test signal loop is formed between the test machine 110, the adapter circuit board 130, the test board 120 and the chip to be tested 121, and the temperature of multiple chips to be tested 121 is increased / decreased at the same time, which can take into account the existing parallel finished product test program or achieve simultaneous heating / cooling and testing of multiple chips to be tested 121 by developing a serial program, thereby improving the utilization rate of the test pad 1111 and improving the test efficiency.

[0044] In some embodiments, please refer to Figure 2-Figure 3 Through the adapter circuit board 130 and the corresponding serial test program, the test machine 110 gives the test signals of the corresponding multiplexed pins 131 in sequence, and then transmits the required test signals to each chip under test 121 through the adapter circuit board 130, thereby realizing the multiplexing of a single pin. After the temperature of the chip under test 121 reaches the preset requirement, multiple chips under test 121 can be tested at the same time and the test results can be returned, thereby saving the waiting time for independent heating / cooling of each chip under test 121 and improving the test efficiency.

[0045] In some embodiments, the test signals transmitted by the test machine to the multiplexed pins of the transfer circuit board may be the same or different.

[0046] It should be noted that the number of chips to be tested that can be connected to the adapter circuit board depends on the number of test pads of the test machine and the pin allocation set according to the chip function in the test serial program; the parallel program instructs the chip test device to perform multiple test tasks at the same time; the serial program instructs the chip test device to perform only one test task at the same time.

[0047] In some embodiments, please refer to Figure 4a-4b The adapter circuit board includes a power pin area 132 and an input / output pin area 133 that are distributed at intervals; the power pin area 132 includes a plurality of power pads 1321 arranged in rows and columns along a first direction (e.g., OX direction) and a second direction (e.g., OY direction); the input / output pin area 133 includes a plurality of input / output pads 1331 arranged in rows and columns along the first direction and the second direction.

[0048] In some embodiments, please refer to Figure 4a-4b, each row of power pads 1321 includes first unit areas 1322 distributed in sequence along the first direction, and a first unit area 1322 includes an excitation pad S1, a detection pad F and a ground pad G distributed in sequence along the first direction; the excitation pad S1 is used to receive and transmit the power signal, the detection pad F is used to detect whether the amplitude of the power signal on the excitation pad S1 is within the corresponding amplitude range, and the ground pad G is used for grounding; in the first unit areas 1322 adjacent to each other along the first direction, the ground pad G of a first unit area 1322 is adjacent to the excitation pad S1 of another first unit area.

[0049] In some embodiments, if the detection pad detects that the amplitude of the power signal on the excitation pad is outside the corresponding amplitude range, the detection pad notifies the tester to provide a compensation power signal; the power signal includes a voltage signal and a current signal.

[0050] In some embodiments, please refer to Figure 4a-4b The power pads 1321 adjacent along the first direction are used to connect the same chip to be tested; the power pads 1321 adjacent along the second direction are used to connect different chips to be tested; the excitation pads S1 adjacent along the second direction are connected; the detection pads F adjacent along the second direction are connected; and the ground pads G adjacent along the second direction are connected.

[0051] In some embodiments, please refer to Figure 4a-4b The input / output pin area 133 includes a second unit area 1332 arranged in rows and columns along the first direction and the second direction; the second unit area 1332 includes a plurality of signal pads S2 arranged in sequence along the first direction and a plurality of ground pads G arranged in sequence along the first direction; a plurality of signal pads S2 constitute a signal pad row, and a plurality of ground pads G constitute a ground pad row; the signal pads S2 are used to receive and transmit test signals, and the ground pads G are used for grounding; in the adjacent second unit areas 1332 along the second direction, the signal pad row of one second unit area 1332 is adjacent to the ground pad row of another second unit area 1332.

[0052] In some embodiments, please refer to Figure 4a-4b , one second unit area 1332 is used to connect the same chip under test; different second unit areas 1332 are used to connect different chips under test.

[0053] In some embodiments, the chip testing device further includes a temperature control cover (not shown), which is disposed corresponding to the test board and is used to perform at least one of the following steps while covering the chip to be tested on the corresponding test board:

[0054] After heating the chip to be tested to a preset first temperature at room temperature, a temperature test is performed on the chip to be tested;

[0055] After cooling the chip to be tested to a preset second temperature at room temperature, a temperature test is performed on the chip to be tested;

[0056] A temperature test is performed on the chip to be tested at room temperature; the first temperature is greater than the temperature at room temperature, and the temperature at room temperature is greater than the second temperature.

[0057] In some embodiments, the first temperature is 84°C-86°C, for example 84°C, 85°C or 86°C; the second temperature is (-41°C)-(-39°C), for example -41°C, -40°C or -39°C; the temperature at room temperature is 24°C-26°C, for example 24°C, 25°C or 26°C.

[0058] In some embodiments, the test machine includes a display (not shown), which is used to display test results, and the test results include at least one of voltage test results, current test results, frequency test results, and functional test results.

[0059] In some embodiments, please refer to Figure 5 , the chip testing device tests the chip to be tested. For example, when performing a high temperature test on the chip to be tested, after inserting multiple chips to be tested into the corresponding test board, the temperature of the chip to be tested is raised to 85°C at room temperature, preheated for 3 minutes, and the test is started after the chip to be tested fully reaches the target temperature of 85°C. After the test is completed, the ambient temperature and the temperature of the chip to be tested are adjusted to 25°C, kept at 25°C for 1 minute, and then the multiple chips to be tested are taken out. For another example, when performing a low temperature test on the chip to be tested, after inserting multiple chips to be tested into the corresponding test board, the temperature of the chip to be tested is lowered to -40°C at room temperature, cooled for 3 minutes, and the temperature of the chip to be tested fully reaches the target temperature of -40°C. After the test is completed, the ambient temperature and the temperature of the chip to be tested are adjusted to 25°C, kept at 25°C for 1 minute, and then the multiple chips to be tested are taken out. For another example, when performing a normal temperature test on the chip to be tested, the test can be started in an environment with a normal temperature of 25°C, and multiple chips to be tested can be taken out after the test is completed.

[0060] Table 1

[0061]

[0062] In some embodiments, as shown in Table 1, when the current relevant chip testing device performs three-temperature testing, the plug-in and pull-out time of the chip to be tested is 5s. When testing at room temperature of 25°C, there is no need to change the temperature of the test environment to test, but only one chip to be tested can be tested at a time, and the test time is 3min. The chip testing device in the embodiment of the present application can test multiple chips to be tested at a time. Compared with the relevant chip testing device, the test time is shortened and the test efficiency is improved by at least 2 times or more; when the relevant chip testing device performs a high-temperature 85°C test, the heating preparation time is 3.3min, the test time is about 3min, the room temperature standing time is 30s, and the high-temperature test of a single chip to be tested is a total of The test time is 6.8 minutes, while the chip test device in the embodiment of the present application saves the time for preparing the test environment for each chip to be tested and the time for manually plugging and replacing the chip to be tested, and the test efficiency in the same time is improved by at least 2 times or more; when the relevant chip test device performs a low-temperature test at -40°C, the cooling preparation time is 3.3 minutes, the test time is about 3 minutes, the room temperature standing time is 40 seconds, and the high-temperature test of a single chip to be tested is a total of 7 minutes, while the chip test device in the embodiment of the present application saves the time for preparing the test environment for each chip to be tested and the time for manually plugging and replacing the chip to be tested, and the test efficiency in the same time is improved by at least 2 times or more. By improving the test efficiency, the equipment cost caused by the low efficiency of the relevant chip test device is reduced, and at the same time, the time of the test project is shortened, which speeds up the overall progress of the project.

[0063] Table 2

[0064]

[0065] In some embodiments, as shown in Table 2, due to the small area of ​​the transfer circuit board, in order to ensure the normal progress of the test and prevent the test circuit from malfunctioning, the channel resource interface of the test machine can be connected to 2-3 test boards through the transfer circuit board, so that 2-3 chips to be tested can be heated / cooled and tested at the same time. When the number of chips to be tested is the same, the old solution uses the relevant chip testing device, which requires 2 testers to complete the test in one day. The new solution uses the chip testing device in the embodiment of the present application, which only requires 1 tester to complete the test in one day, reducing labor costs. For example, the old solution uses the relevant chip testing device. During the test preparation stage, 120 chips can be tested per hour at room temperature 25°C, 20 chips can be tested per hour at high temperature 85°C, and 15 chips can be tested per hour at low temperature -40°C; while the new solution uses the chip testing device in the embodiment of the present application. During the test preparation stage, 120 chips can be tested per hour at room temperature 25°C, 40-60 chips can be tested per hour at high temperature 85°C, and 30-45 chips can be tested per hour at low temperature -40°C. The old scheme adopts the relevant chip testing device. In the test phase 1, 20 chips can be tested per hour at room temperature 25°C, 20 chips can be tested per hour at high temperature 85°C, and 20 chips can be tested per hour at low temperature -40°C; while the new scheme adopts the chip testing device in the embodiment of the present application. In the test phase 1, 40-60 chips can be tested per hour at room temperature 25°C, 40-60 chips can be tested per hour at high temperature 85°C, and 40-60 chips can be tested per hour at low temperature -40°C.

[0066] In some embodiments, please continue to refer to Table 2. The old scheme uses the relevant chip testing device. In test phase 2, 22 chips can be tested per hour at room temperature 25°C, 12 chips can be tested per hour at high temperature 85°C, and 10 chips can be tested per hour at low temperature -40°C; while the new scheme uses the chip testing device in the embodiment of the present application. In test phase 2, 44-60 chips can be tested per hour at room temperature 25°C, 24-36 chips can be tested per hour at high temperature 85°C, and 20-30 chips can be tested per hour at low temperature -40°C. It not only reduces labor costs, but also effectively improves the utilization rate of the test machine. One test machine can test multiple chips to be tested at the same time, improving test efficiency.

[0067] In some embodiments, a chip is provided and tested using any chip testing device in the above embodiments.

[0068] The chip in the above embodiment is tested by a chip testing device. Multiple chips can be placed on a test board at the same time. The test machine and multiple test boards are connected through multiple multiplexing pins on the adapter circuit board to form a test loop. The test machine transmits the test signal to the test board through the corresponding pins of the adapter circuit board. After the temperature reaches the preset requirements, multiple chips are tested. After the test is completed, the test board feeds back the test results of multiple chips to the test machine, thereby reducing the test time, improving the test efficiency, reducing the time cost of the test, and accelerating the overall progress of the project.

[0069] The unexpected technical effect that the present application can produce is: the chip testing device is provided with multiple multiplexed pins on the adapter circuit board, and the test machine and multiple test boards are connected through the multiplexed pins to form a test loop. The test machine transmits the test signal to the corresponding pins of the adapter circuit board in sequence, so as to test multiple chips to be tested after the temperature reaches the preset requirements, thereby realizing the multiplexing of a single pin. After the test is completed, the test board feeds back the test results of the multiple chips to be tested to the test machine. By testing multiple chips to be tested at the same time, the test time is reduced, the test efficiency is improved, the time cost and labor cost of the test are reduced, the overall progress of the project is accelerated, and the machine utilization rate is effectively improved.

[0070] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0071] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip testing device, characterized in that: include: A test machine, used to test the chip under test at a preset temperature; At least two test boards, one of which is used to carry a chip to be tested, perform functional tests and electrical tests on the chip to be tested at different temperatures, and also to feed back the test results to the test machine; A switching circuit board is connected to the test machine and the at least two test boards. A plurality of multiplexing pins are arranged on the switching circuit board. The multiplexing pins are connected to at least two test boards and are used to transmit the test signals provided by the test machine in parallel to the at least two connected test boards.

2. The chip testing device according to claim 1, characterized in that: The transfer circuit board includes a power pin area and an input / output pin area which are distributed at intervals; The power pin area includes a plurality of power pads arranged in rows and columns along a first direction and a second direction; The input / output pin area includes a plurality of input / output pads arranged in rows and columns along the first direction and the second direction.

3. The chip testing device according to claim 2, characterized in that: Each row of the power pads includes a first unit area sequentially distributed along the first direction, and the first unit area includes an excitation pad, a detection pad and a ground pad sequentially distributed along the first direction; the excitation pad is used to receive and transmit a power signal, the detection pad is used to detect whether the amplitude of the power signal on the excitation pad is within a corresponding amplitude range, and the ground pad is used to be grounded; In the first unit regions adjacent to each other along the first direction, a ground pad of one of the first unit regions is adjacent to an excitation pad of another of the first unit regions.

4. The chip testing device according to claim 3, characterized in that: The power pads adjacent to each other along the first direction are used to connect to the same chip under test; The power pads adjacent to each other along the second direction are used to connect different chips to be tested.

5. The chip testing device according to any one of claims 2 to 4, characterized in that: The input / output pin area includes a second unit area arranged in rows and columns along the first direction and the second direction; The second unit area includes a plurality of signal pads sequentially arranged along the first direction and a plurality of ground pads sequentially arranged along the first direction; the plurality of signal pads constitute a signal pad row, and the plurality of ground pads constitute a ground pad row; the signal pads are used to receive and transmit the test signal, and the ground pads are used to be grounded; In the second unit regions adjacent to each other along the second direction, a signal pad row of a second unit region is adjacent to a ground pad row of another second unit region.

6. The chip testing device according to claim 5, characterized in that: The second unit area is used to connect to the same chip under test; Different second unit areas are used to connect different chips to be tested.

7. The chip testing device according to any one of claims 1 to 4, characterized in that: Also includes: The temperature control cover is provided corresponding to the test board, and is used to perform at least one of the following steps while covering the chip to be tested on the corresponding test board: After heating the chip to be tested to a preset first temperature at room temperature, performing a temperature test on the chip to be tested; After cooling the chip to be tested to a preset second temperature at room temperature, performing a temperature test on the chip to be tested; A temperature test is performed on the chip to be tested at room temperature; the first temperature is greater than the temperature at room temperature, and the temperature at room temperature is greater than the second temperature.

8. The chip testing device according to any one of claims 1 to 4, characterized in that: The testing machine comprises: A signal lead-out board includes a plurality of test pads arranged in rows and columns along a first direction and a second direction, and different test pads are used to be connected to different pins on the adapter circuit board via wires.

9. The chip testing device according to any one of claims 1 to 4, characterized in that: The testing machine comprises: The display is used to display the test results, wherein the test results include at least one of voltage test results, current test results, frequency test results and function test results.

10. A chip, characterized in that: The chip testing device according to any one of claims 1 to 9 is used for testing.

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