Data acquisition device for chip aging test
The voltage signal of chip aging test is processed through the three-stage filtering circuit structure, which solves the problems of inefficiency and manual errors in the existing technology, and realizes intelligent sorting and accurate judgment of the chip.
Patent Information
- Application Number
- CN202420423524.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-05
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2034-03-05
AI Technical Summary
The existing chip aging test solutions are inefficient, have high labor costs, and are prone to errors in data. The LED lamp signal is too weak, which makes it difficult to identify abnormal chips.
Design a data acquisition device to process the voltage signals output by the chip step by step through the three-stage filter circuit (first-level filter circuit, second-level filter circuit and third-level filter circuit), including SN74LVC8T245DWR chip, IIC signal isolation circuit and SPI differential Signal processing circuit ensures the accuracy and stability of the signal.
It realizes accurate acquisition and processing of chip output voltage signals, improves the efficiency and accuracy of chip sorting, reduces manual errors, and can more intuitively determine whether there are abnormalities in the chip.
Smart Images
Figure CN222259505U_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip testing, and in particular relates to a data acquisition device for chip aging testing. Background Art
[0002] At present, the aging of digital integrated circuits is one of the important factors affecting the reliability of integrated circuits. Once digital integrated circuits age, some parameters of the chip will change, and its performance will also drop significantly. Different levels of circuit aging will show different physical characteristics. Therefore, in order to extend the service life of the circuit and reduce maintenance costs, it is particularly important to perform aging tests on digital integrated circuits. The existing chip testing scheme is to make a dedicated aging test board for the chip under test. Each IC of the test board is equipped with an LED indicator light. After the aging test of the chip under test is completed, the staff will manually sort and record the data of the chip under test according to the state of the LED light (for example, the green light indicates that the chip test is normal, and the red light indicates that the test is abnormal). However, since human operation is inevitably wrong, it is possible that the chip sorting error may occur due to negligence. Therefore, this scheme has the defects of low efficiency, high labor cost, and easy data errors. At the same time, there are some chips in the aging test process. The LED light does not flash due to the weak output voltage signal, and it is impossible to judge whether the chip is abnormal. Therefore, it is necessary to propose a new chip aging test data acquisition device to solve the above problems. Utility Model Content
[0003] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a data acquisition device for chip aging testing, which performs three-level filtering in the process of acquiring the voltage signal output by the chip, thereby ensuring the accuracy of the voltage signal output by the chip.
[0004] To achieve the above objectives, the present disclosure provides the following technical solutions:
[0005] A data acquisition device for chip aging test comprises a first data acquisition unit, a second data acquisition unit and a third data acquisition unit, wherein:
[0006] The input end of the first data acquisition unit is electrically connected to the output end of the chip aging test board, and the output end of the first data acquisition unit is electrically connected to the input end of the second data acquisition unit;
[0007] The output end of the second data acquisition unit is electrically connected to the input end of the third data acquisition unit;
[0008] The acquisition device further comprises a data storage unit, and an input end of the data storage unit is electrically connected to an output end of the third data acquisition unit.
[0009] Preferably, the first data acquisition unit includes multiple corresponding first-level filter circuits and sub-MCUs, the input end of each first-level filter circuit is electrically connected to the output end of the chip aging test board, and the output end of each first-level filter circuit is electrically connected to the input end of the corresponding sub-MCU.
[0010] Preferably, the first-stage filtering circuit adopts the SN74LVC8T245DWR chip.
[0011] Preferably, the second data acquisition unit includes multiple secondary filtering circuits corresponding to the sub-MCUs and a main MCU, the input end of each secondary filtering circuit is electrically connected to the output end of the corresponding sub-MCU, and the output end of each secondary filtering circuit is electrically connected to the input end of the main MCU.
[0012] Preferably, the secondary filtering circuit adopts an IIC signal isolation circuit.
[0013] Preferably, the third data acquisition unit includes a three-stage filtering circuit and an FPGA acquisition card, the input end of the three-stage filtering circuit is electrically connected to the output end of the main MCU, and the output end of the three-stage filtering circuit is electrically connected to the input end of the FPGA acquisition card.
[0014] Preferably, the three-stage filtering circuit adopts an SPI differential signal processing circuit.
[0015] Preferably, the data storage unit adopts a host computer.
[0016] Compared with the prior art, the present invention has the following beneficial effects:
[0017] The present invention processes the output voltage signal of the chip after the aging test step by step through a multi-stage circuit structure, and can accurately obtain the output voltage signal of the chip, so as to make a more intuitive and accurate judgment on whether the chip is abnormal, and further realize the intelligent sorting of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a structural schematic diagram of a data acquisition device for chip aging test provided by an embodiment of the present disclosure;
[0019] Figure 2 is a circuit diagram of a primary filtering circuit provided by another embodiment of the present disclosure;
[0020] Figure 3 is a circuit diagram of an MCU provided by another embodiment of the present disclosure;
[0021] Figure 4 is a circuit diagram of a secondary filtering circuit provided by another embodiment of the present disclosure;
[0022] Figure 5 is a circuit diagram of a three-stage filtering circuit provided by another embodiment of the present disclosure;
[0023] Figure 6 is a circuit diagram of an FPGA acquisition card provided by another embodiment of the present disclosure;
[0024] Figure 7 is a schematic diagram of the internal structure of a chip SN74LVC8T245DWR provided by another embodiment of the present disclosure;
[0025] Figure 8 is a schematic diagram of the internal structure of an ISO1541D chip provided by another embodiment of the present disclosure;
[0026] Fig. 9 is a chip test MAP diagram provided by another embodiment of the present disclosure;
[0027] The following are the descriptions of the reference numerals:
[0028] 1. Aging test board; 2. Primary filter circuit; 3. Sub-MCU; 4. Secondary filter circuit; 5. Main MCU; 6. Third-stage filter circuit; 7. FPGA acquisition card; 8. Data storage unit. DETAILED DESCRIPTION
[0029] The following will refer to the attached Figures 1 to 9 Specific embodiments of the present disclosure are described in detail. Although specific embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0030] It should be noted that certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. This specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction. As mentioned throughout the specification and claims, "including" or "comprising" is an open term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is a preferred embodiment of the present disclosure, but the description is based on the general principles of the specification and is not used to limit the scope of the present disclosure. The scope of protection of the present disclosure shall be determined by the attached claims.
[0031] To facilitate understanding of the embodiments of the present disclosure, further explanation will be given below using specific embodiments as examples in conjunction with the accompanying drawings, and each of the accompanying drawings does not constitute a limitation on the embodiments of the present disclosure.
[0032] In one embodiment, if Figure 1 As shown, the present disclosure provides a data acquisition device for chip aging test, including a first data acquisition unit, a second data acquisition unit and a third data acquisition unit, wherein:
[0033] The input end of the first data acquisition unit is electrically connected to the output end of the chip aging test board, and the output end of the first data acquisition unit is electrically connected to the input end of the second data acquisition unit;
[0034] The output end of the second data acquisition unit is electrically connected to the input end of the third data acquisition unit;
[0035] The acquisition device further comprises a data storage unit, and an input end of the data storage unit is electrically connected to an output end of the third data acquisition unit.
[0036] In another embodiment, the first data acquisition unit includes multiple corresponding first-level filter circuits and sub-MCUs, the input end of each first-level filter circuit is electrically connected to the output end of the chip aging test board, and the output end of each first-level filter circuit is electrically connected to the input end of the corresponding sub-MCU.
[0037] In this embodiment, the chips on the aging test board are a matrix structure with fixed rows and columns. In this embodiment, a primary filtering circuit and a sub-MCU corresponding to the primary filtering circuit are set for each row or column of chips, wherein the input end of the primary filtering circuit is electrically connected to the gold finger on the aging test board to perform primary filtering and amplification on the output voltage signal of each row or column of chips (since the output voltage signal of each chip is relatively weak, and the output voltage signals of adjacent chips inevitably interfere with each other, in order to accurately collect the output voltage signal of each chip, it is necessary to set a primary filtering circuit in front of the sub-MCU that collects and stores the output voltage signal of each row or column of chips, so as to perform primary filtering and amplification on the output voltage signal of each row or column of chips). The chip output voltage signal after primary filtering and amplification is output to the corresponding sub-MCU through the output end of the primary filtering circuit, thereby completing the primary collection of the chip output voltage signal.
[0038] In another embodiment, the first-stage filtering circuit uses a SN74LVC8T245DWR chip.
[0039] In this embodiment, Figure 2As shown, the SN74LVC8T245DWR chip includes pins 1 to 24, wherein pins 1 and 2 are respectively connected to both sides of the resistor R1, and connected to the power supply end of the chip to be tested on the aging test board through capacitors C1 and C2 in parallel, and the output voltage signal of the chip to be tested (exemplarily, the voltage signal is 1.8V) is input into the SN74LVC8T245DWR chip through pins 3 to 10, and is amplified inside the SN74LVC8T245DWR chip and output through pins 13 to 21. In addition, the parallel capacitors C3 and C4 connected to pins 23 and 24 form a power supply filter circuit to filter the amplified voltage signal output from pins 13 to 21, and the amplified voltage signal (exemplarily, the voltage signal after amplification and filtering is 5V) after filtering by the SN74LVC8T245DWR chip is output to the input end of the sub-MCU through pins 13 to 21.
[0040] It should be noted that the SN74LVC8T245DWR chip is a non-directional voltage level converter chip. Figure 7 As shown, the chip internally realizes chip level conversion by controlling the gate architecture. In this embodiment, a small signal is input to one end of the chip, and a large level signal is output at the other end, so that the MCU can identify and judge the processing.
[0041] Before the introduction of the primary filter circuit, the output voltage signal strength of the chip under test is weak and lower than the comparison voltage of the sub-MCU, so it is usually judged as low by the sub-MCU, resulting in misjudgment. By introducing the primary filter circuit to filter and amplify the output voltage signal of the chip under test, the signal strength can be improved and accurate signal recognition can be achieved.
[0042] In another embodiment, the sub-MCU adopts a M0A23EC1AC chip.
[0043] In this embodiment, Figure 3 As shown, the M0A23EC1AC chip includes pins 1 to 28, wherein pin 1 is externally connected to a power supply VDD through capacitors C8 and C9 connected in parallel, and pins 5 to 13 and pins 17 to 24 are connected to the output end of a primary filter circuit, that is, the 5V voltage signal output from pins 14 to 21 of the SN74LVC8T245DWR chip is introduced into the M0A23EC1AC chip through pins 5 to 13 and pins 17 to 24, thereby completing the collection of the output voltage signal of each row or column of the chip to be tested on the aging test board.
[0044] In another embodiment, the second data acquisition unit includes multiple secondary filtering circuits corresponding to the sub-MCU and a main MCU, the input end of each secondary filtering circuit is electrically connected to the output end of the corresponding sub-MCU, and the output end of each secondary filtering circuit is electrically connected to the input end of the main MCU.
[0045] In this embodiment, the main MCU also uses Figure 3 The M0A23EC1AC chip shown, the main MCU communicates with each sub-MCU through the IIC protocol, thereby integrating the signals collected by multiple sub-MCUs.
[0046] Furthermore, in order to prevent the signal from being disturbed during the integration process, the present embodiment provides a secondary filtering and amplifying circuit at the input end of the main MCU to perform secondary filtering and amplifying processing on the output voltage signal of each sub-MCU.
[0047] In another embodiment, the secondary filtering circuit adopts an IIC signal isolation circuit.
[0048] In this embodiment, the IIC signal isolation circuit adopts Figure 4 The ISO1541D chip shown in the figure includes pins 1 to 8, wherein pin 1 is connected to the power supply reference voltage (5V) of the corresponding sub-MCU, and pins 2 (i.e., interface SDA1) and 3 (i.e., interface SCL1) are electrically connected to pins 16 (i.e., interface IIC_SDA) and 14 (i.e., interface IIC_SCL) of the sub-MCU, so as to introduce the voltage signal after the primary filtering and amplification collected by the sub-MCU into the ISO1541D chip for secondary filtering. The output voltage signal after the secondary filtering is output to the main MCU via pins 6 (i.e., interface SCL2) and 7 (i.e., interface SDA2) (specifically, it is input to the main MCU via pins 14 (i.e., interface IIC_SCL) and 16 (i.e., interface IIC_SDA) of the main MCU).
[0049] It should be noted that the internal structure of the ISO1541D chip is as follows Figure 8 As shown, silicon dioxide is used internally to isolate the logic input and output buffers, so that the voltage signals collected by multiple sub-MCUs will not crosstalk with each other, thereby avoiding the occurrence of unstable signals at the input end of the main MCU.
[0050] In another embodiment, the third data acquisition unit includes a three-stage filtering circuit and an FPGA acquisition card, the input end of the three-stage filtering circuit is electrically connected to the output end of the main MCU, and the output end of the three-stage filtering circuit is electrically connected to the input end of the FPGA acquisition card.
[0051] In this embodiment, the three-stage filter amplifier circuit adopts an SPI differential signal processing circuit, such as Figure 5 As shown, the SPI differential signal processing circuit is composed of a chip SN65LVDT41 and a chip SN65LVDT14. Among them, the chip SN65LVDT41 is used to realize differential processing of the output signal of the main MCU and generate differential signals, and the chip SN65LVDT14 is used to realize integration of the differential signals output by the chip SN65LVDT41 and output SPI signals.
[0052] Specifically, pin 1 (i.e., interface MOSI_M), pin 9 (i.e., interface MISO_M), pin 3 (i.e., interface SCLK_M), and pin 5 (i.e., interface CS_M) of SN65LVDT41 are connected to pin 5 (i.e., interface SPI_MOSI), pin 6 (i.e., interface SPI_MISO), pin 12 (i.e., interface SPI_CLK), and pin 13 (i.e., interface SPI_CS) of the main MCU. The output signal of the main MCU is processed by the internal differential of the chip SN65LVDT41 to generate a differential signal and output through the H1 terminal, and then input into the chip SN65LVDT14 through the H2 terminal, and then converted into an SPI signal by the chip SN65LVDT14 and input into the FPGA acquisition card.
[0053] The circuit of the FPGA acquisition card is as follows Figure 6 As shown, pin 9 (i.e., interface SPI_MISO), pin 59 (i.e., interface SPI_MOSI), pin 63 (i.e., interface SPI_CLK) and pin 61 (i.e., interface SPI_CS) are respectively connected to pin 20 (i.e., interface MOSE_S), pin 12 (i.e., interface MISO_S), pin 18 (i.e., interface SCLK_S) and pin 16 (CS_S) of the chip SN65LVDT14, so as to input the output voltage signal filtered by the three-stage filtering circuit into the FPGA acquisition card.
[0054] Since the voltage signal collected by the main MCU is severely attenuated during long-distance transmission, if this differential circuit is not used, signal transmission will fail and affect data judgment.
[0055] In another embodiment, the data storage unit adopts a host computer.
[0056] In this embodiment, the FPGA acquisition card outputs the collected output voltage signal to the host computer through the PCIE board for storage, thereby completing the collection of the output voltage signals of all the chips to be tested on the aging test board. The host computer integrates the received signals according to the row and column structure of the chips on the aging test board. When the chip is tested normally on the aging test board, it is marked green and assigned a value of 1. When the test is abnormal, it is marked red and assigned a value of 2, thereby obtaining the corresponding output voltage signal of the current board. Fig. 9 The MAP diagram shown greatly improves the chip sorting efficiency compared to the manual chip sorting based on the flashing of LED lights.
[0057] The above embodiments are only for illustrating the technical concept and features of the present disclosure, and their purpose is to enable people familiar with the technology to understand the content of the present disclosure and implement it accordingly, and they cannot be used to limit the protection scope of the present disclosure. Any equivalent changes or modifications made according to the spirit of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A data acquisition device for chip aging test, comprising a first data acquisition unit, a second data acquisition unit and a third data acquisition unit, wherein: The input end of the first data acquisition unit is electrically connected to the output end of the chip aging test board, and the output end of the first data acquisition unit is electrically connected to the input end of the second data acquisition unit; The output end of the second data acquisition unit is electrically connected to the input end of the third data acquisition unit; The acquisition device further comprises a data storage unit, and an input end of the data storage unit is electrically connected to an output end of the third data acquisition unit.
2. The device according to claim 1, wherein: The first data acquisition unit includes a plurality of corresponding primary filter circuits and sub-MCUs, the input end of each primary filter circuit is electrically connected to the output end of the chip aging test board, and the output end of each primary filter circuit is electrically connected to the input end of the corresponding sub-MCU.
3. The device according to claim 2, wherein: The first-stage filtering circuit adopts the SN74LVC8T245DWR chip.
4. The device according to claim 2, wherein: The sub-MCU adopts M0A23EC1AC chip.
5. The device according to claim 2, wherein: The second data acquisition unit includes multiple secondary filter circuits corresponding to the sub-MCUs and a main MCU, the input end of each secondary filter circuit is electrically connected to the output end of the corresponding sub-MCU, and the output end of each secondary filter circuit is electrically connected to the input end of the main MCU.
6. The device according to claim 5, wherein: The secondary filtering circuit adopts an IIC signal isolation circuit.
7. The device according to claim 5, wherein: The third data acquisition unit includes a three-stage filter circuit and an FPGA acquisition card. The input end of the three-stage filter circuit is electrically connected to the output end of the main MCU, and the output end of the three-stage filter circuit is electrically connected to the input end of the FPGA acquisition card.
8. The device according to claim 7, wherein: The three-stage filtering circuit adopts an SPI differential signal processing circuit.
9. The device according to claim 1, wherein: The data storage unit adopts a host computer.