Architecture for high-speed large-capacity recording and storage

Abstract

The utility model discloses an architecture for high-speed and high-capacity recording and storage. The architecture comprises a CPU (Central Processing Unit), a bridge chip, a symmetric FPGA (Field Programmable Gate Array) module, an MCU (Microprogrammed Control Unit) and a plurality of groups of DDR3 (Double Data Rate 3), two groups of DDR3 are mounted on the cpu, and the cpu is connected with the MCU through two paths of IPMB buses and is connected with the third end of the bridge sheet through one path of PCIe * 8 bus; the symmetrical FPGA module comprises a first FPGA and a second FPGA, the first FPGA and the second FPGA are both connected with the cpu and located on the two sides of the cpu respectively to form a symmetrical structure, the first FPGA is connected with the first end of the bridge piece through a PCIe2 * 8 bus, the second FPGA is connected with the second end of the bridge piece through a PCIe2 * 8 bus, and the first end and the second end of the bridge piece are located on the two symmetrical sides of the bridge piece respectively; two sets of DDR3 are mounted on the symmetrical side of the connection side of the first FPGA and the bridge piece, and two sets of DDR3 are also mounted on the symmetrical side of the connection side of the second FPGA and the bridge piece. According to the utility model, the structure is effectively simplified by utilizing the symmetric FPGA and the two groups of symmetric DDR3, the working efficiency is improved, and meanwhile, the corresponding connection is carried out by utilizing a plurality of PCIe buses, so that the recording and storage functions are effectively completed.

Description

Technical Field

[0001] The utility model relates to the technical field of data storage architecture, and in particular to an architecture for high-speed and large-capacity recording and storage. Background Art

[0002] The recording and storage platform mainly completes the recording and playback of intelligence information, signal data, health management data and combat data. It has data management functions such as data query, retrieval, extraction, upload and download, and has a wide range of application scenarios.

[0003] The current record storage platform needs to complete multiple functions such as storing large amounts of data, recording and replaying optical fiber data, data query and retrieval, data downloading, and BIT upload status information. The architecture adopted by the platform often uses a large number of complex channels and has a complicated structure, resulting in reduced processing efficiency and actual manual operation efficiency. In addition, the demand for multi-functions and the use of complex multi-channels often cause heat dissipation problems, causing the architecture to generate severe heat when working, which in turn affects the work efficiency of the architecture. Utility Model Content

[0004] The purpose of the utility model is to provide an architecture for high-speed, large-capacity recording and storage. On the basis of ensuring high-speed, large-capacity recording and transmission functions, a symmetrical FPGA structure is used to simplify the overall architecture to solve the problems of multiple channels and complex structures in the architecture. At the same time, the architecture is arranged on an aluminum alloy plate, which is compatible with air cooling and liquid cooling to solve the heat dissipation problem of the architecture when it is working.

[0005] The specific technical solutions are as follows:

[0006] A framework for high-speed and large-capacity recording and storage, the framework comprises: a CPU, a bridge chip, a symmetrical FPGA module, an MCU and multiple groups of DDR3; the CPU is mounted with two groups of DDR3, the CPU is connected to the MCU via two IPMB buses and is connected to the third end of the bridge chip via a PCIe×8 bus; the symmetrical FPGA module comprises a first FPGA and a second FPGA, the first FPGA and the second FPGA are both connected to the CPU and are respectively located on both sides of the CPU to form a symmetrical structure, the first FPGA is connected to the first end of the bridge chip via a PCIe2×8 bus, the second FPGA is connected to the second end of the bridge chip via a PCIe2×8 bus, and the first end and the second end of the bridge chip are respectively located on both symmetrical sides of the bridge chip; two groups of DDR3 are mounted on the symmetrical side of the first FPGA connected to the bridge chip, and two groups of DDR3 are also mounted on the symmetrical side of the second FPGA connected to the bridge chip.

[0007] Preferably, a heat sink and a base plate are installed on the CPU, the CPU is connected to a fan, the fan blows air in the direction of the heat sink, and the base plate is connected to a liquid cooling tube. The heat sink and the fan are used for air cooling, and the base plate and the liquid cooling tube are used for liquid cooling. The two types of heat dissipation are compatible, which can effectively cool the architecture and prevent overheating from affecting the architecture.

[0008] Preferably, the architecture adopts the VPX non-standard structure, and the width of the architecture is 25.4mm, the height is 262.05mm, and the length is 233.5mm. The VPX non-standard structure is to customize and modify the VPX standard architecture while being compatible with the VPX standard, which is more suitable for actual architecture use while ensuring performance.

[0009] Preferably, the CPU is provided with a Gigabit Ethernet interface and a 10 Gigabit Ethernet interface, the Gigabit Ethernet interface is connected to the Gigabit chip via a PCIe×4 bus, and the 10 Gigabit Ethernet interface is connected to the 10 Gigabit chip via a PCIe×8 bus. Corresponding transmission buses are provided for the 10 Gigabit Ethernet chip and the Gigabit Ethernet chip, meeting the transmission capacity requirements of the two, thereby completing external communication.

[0010] Preferably, the structure is mounted on an aluminum alloy plate, and reinforcing ribs are provided to fix the structure on the aluminum alloy plate. The aluminum alloy plate has high hardness and high thermal conductivity, and the fixing effect of the reinforcing ribs can ensure the stability of the structure and enhance the heat dissipation effect.

[0011] Preferably, the CPU is connected to the power supply through an optocoupler, each FPGA and MCU is connected to the power supply circuit, and the power supply has a filter isolation layer, which isolates the power supply from the power supply circuit. The filter isolation layer can effectively filter and isolate, reduce interference between different circuits, and reduce the impact of power supply noise.

[0012] Preferably, the architecture further includes a plurality of inter-stage buffers, one inter-stage buffer is provided between the CPU and the two FPGAs, and one inter-stage buffer is provided between the CPU and the MCU. The use of a plurality of inter-stage buffers can reduce inter-stage interference and prevent damage to key components due to breakdown.

[0013] The beneficial effects of the utility model compared with the prior art are:

[0014] The utility model utilizes a symmetrical FPGA structure to simplify the overall architecture, solving the problems of multiple channels and complex structures in the architecture; at the same time, the architecture is laid out on an aluminum alloy plate, compatible with air cooling and liquid cooling, solving the heat dissipation problem of the architecture when it is working; in addition, the architecture adopts a VPX non-standard structure and strictly limits the spacing between different circuits in the filter isolation layer, further reducing the adverse effects that may be suffered by the architecture while ensuring high-speed recording and storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of an architecture for high-speed, high-capacity recording and storage;

[0016] Figure 2 A schematic diagram of a bridge chip using a PCIe bus for data transmission in an architecture for high-speed, large-capacity recording and storage. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model. Example

[0018] like Figure 1 As shown, it is a block diagram of an architecture for high-speed and large-capacity recording and storage. The architecture includes a CPU, a bridge chip, a first FPGA, a second FPGA, an MCU and multiple groups of DDR3. The two FPGAs adopt a symmetrical structure to simplify the entire architecture.

[0019] In this embodiment, the CPU mounts two groups of DDR3 for data caching and control. The capacity of each group of DDR3 is 2GB, and the transmission rate is not less than 1333MT / s, so as to ensure transmission efficiency and performance. The CPU realizes a bidirectional connection with the MCU through two IPMB buses. The MCU is a microcontroller that can send instructions to the CPU or receive information transmitted by the CPU, and the IPMB bus is a data line based on the communication protocol of the physical layer of the integrated circuit bus, which can run in parallel at high speed to ensure operation performance and efficiency.

[0020] In order to solve the heat dissipation problem of the architecture, a heat sink and a base plate are installed on the CPU. The CPU is connected to a fan, and the direction of the fan blowing is aimed at the heat sink. When heat dissipation is needed, the fan can be turned on; the base plate is connected to a liquid cooling pipe, and cooling water or ethylene glycol can be used as cooling liquid for heat dissipation. In addition, a guide cover can be installed between the CPU and the fan to limit the direction of the fan blowing, thereby further ensuring that the blowing can accurately align the wind direction with the CPU for heat dissipation.

[0021] It should be noted that the main heat-generating part in this architecture is the CPU, so making the CPU compatible with air cooling and liquid cooling can effectively reduce the temperature of the entire architecture and reduce the impact of high temperature on the architecture. If the heat generation of other parts of the architecture cannot be ignored, such as FPGA heat generation, or new heat-prone functional components are added to the architecture, these heat-generating locations can also be cooled by air cooling and liquid cooling.

[0022] In this embodiment, the CPU has 8 port interfaces connected to the 8 port interfaces on the third end of the bridge through a PCIe×8 bus; the two sides of the CPU are connected to the first FPGA and the second FPGA respectively, and the two FPGAs form a symmetrical structure with the CPU as the center. The first FPGA is connected to the first end of the bridge through a PCIe2×8 bus, and the second FPGA is connected to the second end of the bridge through a PCIe2×8 bus. The first end and the second end of the bridge are located on the symmetrical sides of the bridge, further improving the symmetrical structure. Two groups of DDR3 are mounted on the symmetrical side of the first FPGA and the bridge, and two groups of DDR3 are also mounted on the symmetrical side of the second FPGA and the bridge.

[0023] It should be noted that the DDR3 specifications in this embodiment are the same, the capacity of each DDR3 group is 2GB, and the transmission rate is not less than 1333MT / s. On the basis of ensuring the performance of the architecture, it is also convenient for procurement and actual analysis. The PCIe×8 bus is a bus that supports 8 channels and complies with the bus standard for high-speed serial computer expansion. Each channel can transmit in parallel; the corresponding PCIe2×8 bus means two PCIe×8 buses, with a total of 16 channels; the PCIe×4 bus means a total of 4 channels.

[0024] In this embodiment, the CPU also needs to be connected to an optical fiber to complete high-speed optical fiber transmission. Specifically, the CPU is provided with a Gigabit Ethernet interface and a 10 Gigabit Ethernet interface. The Gigabit Ethernet interface is connected to the Gigabit chip via a PCIe×4 bus, and the 10 Gigabit Ethernet interface is connected to the 10 Gigabit chip via a PCIe×8 bus.

[0025] In this embodiment, the architecture adopts the VPX non-standard structure. It is a customized modification of the VPX standard architecture while being compatible with the high performance, high reliability and openness of the VPX standard architecture. While ensuring performance, it is more suitable for actual architecture use. The width of the architecture is 25.4mm; the height is 262.05mm mm, and the length is 233.5mmmm. The three data here are approximate numbers, and there may be slight errors in reality. However, in order to meet actual use requirements, the upper and lower errors cannot exceed 0.4mm at most. The architecture is installed on an aluminum alloy plate with high hardness and high thermal conductivity to facilitate heat dissipation. At the same time, reinforcing ribs are set to fix the architecture on the aluminum alloy plate to ensure the stability of the architecture.

[0026] In this embodiment, the CPU is connected to the power supply through a photoelectric coupler. In this architecture, a power supply circuit is additionally provided, and each FPGA and MCU is connected to the power supply circuit. The photoelectric coupler can improve the anti-interference ability of the device, reduce transmission loss and interference, and a filter isolation layer is provided between the power supply and other power supply circuits, which is mainly used to solve the problems of noise interference, ground loop problems and noise coupling between different circuits during signal transmission, and ensure the quality and stability of the signal. The filter isolation layer can adopt photoelectric isolation, magnetic coupling isolation, active isolation or digital isolation. These isolation methods are common methods and will not be described here. At the same time, by shortening the connection between high-frequency components, gigabit chips, 10,000 chips and DDR3 are all high-frequency components, reducing the distributed parameters and electromagnetic interference between them, and further ensuring the performance of the architecture.

[0027] In this example, the architecture also uses the method of adding inter-stage buffers to reduce inter-stage interference and prevent damage to key components due to breakdown. An inter-stage buffer can be set between the CPU and the two FPGAs, and an inter-stage buffer is also set between the CPU and the MCU to protect the safety of transmission. At the same time, the redundant ports are grounded or connected to the power supply through resistors to prevent interference caused by port induction. In addition, the safety distance between the safety ground and other circuits is not less than 3mm; safety capacitors and resistors are added between the safety ground and the signal ground according to the actual application scenario. The main function of the safety capacitor is to provide coupling on the AC power line, allowing high-frequency interference signals to pass through, and at the same time presenting high impedance in the DC state, effectively preventing dangerous leakage current from flowing directly to the ground; the SGND and PGND pins on the power chip are designed separately.

[0028] Figure 2 A schematic diagram of a bridge chip using a PCIe bus for data transmission in an architecture for high-speed, large-capacity recording and storage, combined with Figure 1 and Figure 2 , give a specific application example:

[0029] The high-speed solid-state record storage architecture uses a Feiteng FT2000 / 4 processor, two Fudan Micro JFM7VX690T FPGAs on board, two groups of DDR3 with a single capacity of 2GB, and an onboard PCIe switch chip PEX8780, i.e. a bridge chip; on this basis, the two FPGAs are symmetrically positioned on both sides of the FT2000 / 4 processor, and each FPGA JFM7VX690T FPGA is equipped with two groups of DDR3 with a single capacity of 2GB, which is also relatively symmetrical.

[0030] The architecture uses non-standard VPX bus plug-ins to implement functions such as recording and playback control and data management. The specific parts of the architecture are as follows:

[0031] 1) Adopt a Feiteng FT2000 / 4 processor to realize file system management, host computer communication and other functions;

[0032] 2) FT2000 / 4 processor is connected to 2 sets of DDR3, each set has a capacity of 2GB, and the transmission speed is not less than 1333MT / s;

[0033] 3) Onboard 10 M.2 interface NVMe disks, i.e. SSD storage disks that comply with the NVMe standard, with a single disk storage capacity of no less than 2TB;

[0034] 4) Onboard 1 SATA interface hard disk chip, storing the FT2000 / 4 operating system and JFM7VX690T FPGA program;

[0035] 5) Two JFM7VX690T FPGAs from Fudan Micro are mounted on both sides of the FT2000 / 4 processor to implement RocketIO data transmission and reception and disk reading and writing functions;

[0036] 6) JFM7VX690T FPGA has two external DDR3s, each with a capacity of 2GB and a read / write rate of 1333MT / s;

[0037] 7) Onboard one PCIe switch chip PEX8780, expanding the PCIe interface in the board;

[0038] 8) Onboard one WX1820AL chip from Netcom, realizing protocol conversion between 1×4 PCIe and 2-way 10GE;

[0039] 9) Onboard one Intel I350 chip to achieve PCIe to 4-way SGMII network conversion;

[0040] 10) 1 XC7A50T FPGA to control the module's power, reset, LED and other signals;

[0041] 11) A GigaDevice GD32F103 MCU is connected to the system management module (1 master and 1 backup) through a 2-way IPMB backplane to achieve board-level monitoring and control, and send monitoring information to the system management module;

[0042] 12) J30J-18TJWP7 integrates JTAG, UART and other debugging interfaces.

[0043] PEX8780 is selected to implement PCIe switching function. The chip has 80 channels and can be configured as up to 20 Port interfaces. The Port interface can be flexibly configured as ×1, ×4, ×8 or ×16 mode according to needs. It supports up to 4 Upstream Ports. The typical power consumption is 16.6W. It is compatible with PCIe3.0 protocol and the maximum rate of a single channel is 8Gbps.

[0044] PEX8780 uses a total of 80 channels, 1 channel × 8 is connected to the CPU, 10 channels × 4 are connected to 10 NVME disks, and 4 channels × 8 are connected to the corresponding FPGA.

[0045] The front end of the JFM7VX690T FPGA is a variety of user interfaces, including multiple RocketIO interfaces, Gigabit Ethernet interfaces, and 10 Gigabit Ethernet interfaces, which communicate with the outside world through optical fiber interfaces.

[0046] In summary, this application uses a symmetrical FPGA structure to simplify the overall architecture and solve the problems of multiple channels and complex structures in the architecture; at the same time, the architecture is laid out on an aluminum alloy plate, which is compatible with air cooling and liquid cooling to solve the heat dissipation problem of the architecture when it is working; in addition, the architecture adopts the VPX non-standard structure and strictly limits the spacing between different circuits in the filter isolation layer, which further reduces the adverse effects that the architecture may suffer while ensuring high-speed recording and storage, and has significant progress.

[0047] The above embodiments are only for illustrating the technical idea of ​​the present utility model, and cannot be used to limit the protection scope of the present utility model. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present utility model shall fall within the protection scope of the present utility model.

Claims

1. An architecture for high-speed, high-capacity recording and storage, characterized in that: The architecture includes: a CPU, a bridge chip, a symmetrical FPGA module, an MCU and multiple groups of DDR3; the CPU is mounted with two groups of DDR3, the CPU is connected to the MCU through two IPMB buses and is connected to the third end of the bridge chip through a PCIe×8 bus; the symmetrical FPGA module includes a first FPGA and a second FPGA, the first FPGA and the second FPGA are both connected to the CPU and are respectively located on both sides of the CPU to form a symmetrical structure, the first FPGA is connected to the first end of the bridge chip through a PCIe2×8 bus, the second FPGA is connected to the second end of the bridge chip through a PCIe2×8 bus, and the first end and the second end of the bridge chip are respectively located on both sides of the symmetrical bridge chip; two groups of DDR3 are mounted on the symmetrical side of the first FPGA connected to the bridge chip, and two groups of DDR3 are also mounted on the symmetrical side of the second FPGA connected to the bridge chip.

2. The architecture for high-speed, large-capacity recording and storage according to claim 1, characterized in that ,A heat sink and a base plate are installed on the CPU. The CPU is connected to a fan, the direction of the fan blowing is aimed at the heat sink, and the base plate is connected to a liquid cooling tube.

3. The architecture for high-speed, large-capacity recording and storage according to claim 1, characterized in that: The architecture adopts the VPX non-standard structure, with a width of 25.4mm, a height of 262.05mm, and a length of 233.5mm.

4. The architecture for high-speed, large-capacity recording and storage according to claim 1, characterized in that: The CPU is equipped with a Gigabit network interface and a 10 Gigabit network interface. The Gigabit network interface is connected to the Gigabit chip through a PCIe×4 bus, and the 10 Gigabit network interface is connected to the 10 Gigabit chip through a PCIe×8 bus.

5. The architecture for high-speed, large-capacity recording and storage according to claim 1, characterized in that: The framework is mounted on an aluminum alloy plate, and reinforcing ribs are provided to fix the framework on the aluminum alloy plate.

6. The architecture for high-speed, large-capacity recording and storage according to claim 1, characterized in that: The CPU is connected to the power supply through an optocoupler, and each FPGA and MCU are connected to the power supply circuit. The power supply has a filter isolation layer, which isolates the power supply from the power supply circuit.

7. The architecture for high-speed, large-capacity recording and storage according to claim 1, characterized in that: The architecture also includes a plurality of inter-stage buffers, one inter-stage buffer is provided between the CPU and each of the two FPGAs, and one inter-stage buffer is also provided between the CPU and the MCU.

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