TOPCON battery structure

Abstract

The utility model provides a TOPCON cell structure, which belongs to the technical field of solar cells and comprises an N-type silicon substrate, and a tunneling silicon oxide layer, a transparent conducting layer, a polycrystalline silicon layer, a back silicon nitride layer and a back metal electrode are sequentially arranged on the back of the N-type silicon substrate from inside to outside. A P-type emitting electrode, an aluminum oxide film layer, a front silicon nitride layer and a front metal electrode are sequentially arranged on the front surface of the substrate from inside to outside; a rough structure is arranged on the surface, connected with the polycrystalline silicon layer, of the transparent conducting layer. The ultrathin transparent conductive layer is inserted between the silicon oxide layer and the polycrystalline silicon layer, the interface, adjacent to the silicon oxide layer, of the transparent conductive layer is a plane, and the interface, adjacent to the polycrystalline silicon layer, of the transparent conductive layer is a rough diffuse reflection surface, so that the direction of light rays incident to the surface can be randomized, the total reflection proportion is increased, and the light ray escape loss is reduced; therefore, the light absorption effect is improved and the cell conversion efficiency is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of solar cells, and in particular relates to a TOPCON battery structure. Background Art

[0002] TOPCon (Tunnel Oxide Passivated Contact) is a tunnel oxide passivated contact solar cell technology based on the principle of selective carriers. Its cell structure is an N-type silicon substrate cell. The silicon oxide layer on the back of the cell can play a role in passivation and allow electrons to tunnel through. The polysilicon layer is a phosphorus-doped N-type polysilicon layer, which can transport electrons to the electrode.

[0003] Existing TOPCon cells usually use a velvet surface on the front side, the purpose of which is to reduce the reflectivity of light when it is incident from the outside to the cell surface, that is, to reduce the external reflection loss of the incident light, increase the short-circuit current, and ultimately improve the photoelectric conversion efficiency of the cell. However, it has relatively little effect on the light that has already entered the cell, and the internal light trapping effect is insufficient. Moreover, since the back side of the TOPCon cell is often flat, the structure on the back side of the cell is not effectively utilized, and the photoelectric conversion efficiency of the cell cannot be further improved. Utility Model Content

[0004] The embodiment of the utility model provides a TOPCON battery structure, which increases the proportion of total reflected light and reduces the proportion of light escaping to the outside of the battery by adding a transparent conductive layer with a diffuse reflection rough structure on the back of the battery, thereby increasing the light absorption effect and improving the battery efficiency.

[0005] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: to provide a TOPCON battery structure, including an N-type silicon substrate, the back side of which is provided with a tunneling silicon oxide layer, a transparent conductive layer, a polysilicon layer, a back silicon nitride layer and a back metal electrode in sequence from the inside to the outside, and the front side is provided with a P-type emitter, an aluminum oxide film layer, a front silicon nitride layer and a front metal electrode in sequence from the inside to the outside; a rough structure is provided on the surface where the transparent conductive layer is connected to the polysilicon layer.

[0006] In one achievable manner, the rough structure is a concave-convex texture structure etched on the surface of the transparent conductive layer.

[0007] In one achievable manner, the transparent conductive layer is a zinc oxide layer doped with Al or Ga.

[0008] In one achievable manner, the thickness of the transparent conductive layer is between 2 nm and 5 nm.

[0009] In one achievable manner, the thickness of the tunneling silicon oxide layer is 1.5±0.5 nm.

[0010] In one achievable manner, the polysilicon layer is a phosphorus-doped N-type polysilicon layer.

[0011] In one achievable manner, a pyramid velvet structure is formed on the front surface of the N-type silicon substrate.

[0012] In one achievable manner, the N-type silicon substrate is N-type single crystal silicon.

[0013] Compared with the prior art, the TOPCON cell structure provided by the utility model has the following beneficial effects: (1) an ultra-thin transparent conductive layer is inserted between the silicon oxide layer and the polycrystalline silicon layer, and the interface between the transparent conductive layer and the silicon oxide layer is a plane, and the interface between the transparent conductive layer and the polycrystalline silicon layer is a rough diffuse reflection surface. In addition to randomizing the direction of the light incident on the surface, thereby increasing the total reflection ratio and reducing the light escape loss, the light absorption effect is increased and the cell conversion efficiency is improved. (2) The transparent conductive layer does not hinder the passage of light and does not affect the collection of electrons. Electrons can tunnel through the silicon oxide layer into the transparent conductive layer, and then enter the polycrystalline silicon layer and be collected by the electrode. (3) The back surface area of ​​the interface between the silicon and silicon oxide layers is not changed, so the total number of defects on the back side will not increase. (4) The thickness and uniformity of the silicon oxide layer are not affected, so the passivation effect of the silicon oxide layer is not affected. (5) The transparent conductive layer is relatively thin, and the proportion of light absorbed and lost by the transparent conductive layer itself can be ignored. (6) Depositing a polysilicon layer on the rough diffuse reflective surface of the transparent conductive layer can control the distribution of polysilicon nucleation points, making the distribution of polysilicon nucleation points more uniform, thereby improving the electrical properties of the polysilicon layer. (7) After the polysilicon layer is deposited, the polysilicon layer can be planarized by chemical polishing or other methods, so that the side of the polysilicon layer that is not adjacent to the transparent conductive layer is a plane, and a silicon nitride layer is deposited on the plane and the electrode is printed, which will not affect the printing effect of the silicon nitride layer and the electrode. (8) It does not affect the original velvet design on the front of the battery, which is usually a pyramid-structured velvet.

[0014] In addition, the nucleation probability of polysilicon layer on flat and concave surfaces is different. When depositing polysilicon layer on ultra-thin diffuse reflective bottom surface with uniform roughness, the nucleation point distribution is more uniform, and a polysilicon layer with more uniform grain size can be obtained, which is beneficial to improve the crystallization rate and electrical properties of the polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of a TOPCON battery provided in an embodiment of the utility model;

[0016] Figure 2 A schematic diagram of the light reflection path of light on the transparent conductive layer provided in an embodiment of the utility model;

[0017] Figure 3This is a schematic diagram of the optical path of total reflection of light on the internal surface of the battery;

[0018] Description of reference numerals:

[0019] 1. N-type silicon substrate; 2. Tunneling silicon oxide layer; 3. Transparent conductive layer; 31. Rough structure; 4. Polysilicon layer; 5. Back silicon nitride layer; 6. Back metal electrode; 7. P-type emitter; 8. Aluminum oxide film layer; 9. Front silicon nitride layer; 10. Front metal electrode. DETAILED DESCRIPTION

[0020] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0021] Please also read Figure 1 and Figure 2 Now, the TOPCON cell structure provided by the utility model is described. The TOPCON cell structure comprises an N-type silicon substrate 1, on the back of which a tunneling silicon oxide layer 2, a transparent conductive layer 3, a polysilicon layer 4, a back silicon nitride layer 5 and a back metal electrode 6 are sequentially arranged from the inside to the outside, and on the front thereof a P-type emitter 7, an aluminum oxide film layer 8, a front silicon nitride layer 9 and a front metal electrode 10 are sequentially arranged from the inside to the outside; a rough structure 31 is arranged on the surface where the transparent conductive layer 3 and the polysilicon layer 4 are connected.

[0022] The utility model inserts an ultra-thin transparent conductive layer 3 with diffuse reflection effect on the bottom surface into the conventional TOPCon battery structure. Figure 1 As shown, the design principle is as follows:

[0023] In the back structure of TOPCon cells, the ultra-thin silicon oxide layer is adjacent to the n-type silicon substrate, which can play a good passivation role, but there are still a certain density of interface defects. The larger the interface area, the greater the total number of defects. If the back of the n-type silicon substrate is directly roughened, on the one hand, a damage layer will be formed, and on the other hand, the back surface area of ​​the silicon substrate will be increased, thereby increasing the total number of defects at the interface between the silicon substrate and silicon oxide on the back of the cell, directly reducing the efficiency of the cell.

[0024] The ultra-thin silicon oxide layer itself is not conductive. Electrons need to tunnel through the silicon oxide layer to enter the conductive polysilicon layer 4 and be collected by the electrode. Since the silicon oxide layer is thin, only about 1.5nm, a too thick or uneven silicon oxide layer will significantly affect the battery performance. Therefore, it is impossible to directly roughen the silicon oxide layer.

[0025] If the interface between the polysilicon layer 4 and the silicon nitride layer or the outer surface of the silicon nitride layer is roughened, the back of the battery will become an irregular rough surface, which will affect the silicon nitride deposition effect and the electrode printing effect, and also affect the original back surface shape of the TOPCon battery (usually a plane).

[0026] As mentioned above, since other structural layers in the battery cannot be roughened, the utility model inserts an ultra-thin transparent conductive layer 3 with diffuse reflection effect on the bottom surface into the conventional TOPCon battery structure. Figure 1 As shown, the structure of the ultra-thin diffuse reflective bottom transparent conductive layer 3 is as follows Figure 2 As shown in the figure, the top surface adjacent to the ultra-thin silicon oxide layer is a plane, and the bottom surface adjacent to the phosphorus-doped polysilicon layer 4 is a rough diffuse reflection surface, which can randomize the direction of parallel sunlight incident on the interface. The critical angle of total reflection of silicon is small, about 16°. After the light enters the battery and its direction is randomized, the proportion of light that falls within the critical angle and escapes to the outside of the battery is small, and most of the light will be totally reflected back to the inside of the battery, such as Figure 3 As shown, the probability of light being absorbed by the silicon substrate is increased.

[0027] Compared with the prior art, the TOPCON cell structure provided by the utility model has the following beneficial effects: (1) an ultra-thin transparent conductive layer 3 is inserted between the silicon oxide layer and the polycrystalline silicon layer 4, and the interface between the transparent conductive layer 3 and the silicon oxide layer is a plane, and the interface between the transparent conductive layer 3 and the polycrystalline silicon layer 4 is a rough diffuse reflection surface. In addition to randomizing the direction of the light incident on the surface, thereby increasing the total reflection ratio and reducing the light escape loss, the light absorption effect is increased, and the cell conversion efficiency is improved. (2) The transparent conductive layer 3 does not hinder the passage of light and does not affect the collection of electrons. Electrons can tunnel through the silicon oxide layer into the transparent conductive layer 3, and then enter the polycrystalline silicon layer 4 to be collected by the electrode. (3) The back surface area of ​​the interface between the silicon and the silicon oxide layer is not changed, so the total number of defects on the back side will not increase. (4) The thickness and uniformity of the silicon oxide layer are not affected, so the passivation effect of the silicon oxide layer is not affected. (5) The transparent conductive layer 3 is relatively thin, and the proportion of light absorbed and lost by the transparent conductive layer 3 itself can be ignored. (6) Depositing the polysilicon layer 4 on the rough diffuse reflection surface of the transparent conductive layer 3 can control the distribution of the polysilicon nucleation points, making the distribution of the polysilicon nucleation points more uniform, thereby improving the electrical properties of the polysilicon layer 4. (7) After the polysilicon layer 4 is deposited, the polysilicon layer 4 can be planarized by chemical polishing or other methods, so that the side of the polysilicon layer 4 that is not adjacent to the transparent conductive layer 3 is a plane, and the silicon nitride layer is deposited on the plane and the electrode is printed, which will not affect the printing effect of the silicon nitride layer and the electrode. (8) It does not affect the original velvet design on the front of the battery, which is usually a pyramid-structured velvet.

[0028] In addition, the nucleation probability of the polysilicon layer 4 on the flat surface and the concave surface is different. When the polysilicon layer 4 is deposited on an ultra-thin diffuse reflective bottom surface with uniform roughness, the nucleation points are distributed more evenly, and a polysilicon layer 4 with more uniform grain size can be obtained, which is conducive to improving the crystallization rate and electrical properties of the polysilicon layer 4.

[0029] The following terms are explained in this article:

[0030] Nucleation: During the vapor deposition of the polysilicon layer 4, molecules are adsorbed and accumulated at appropriate locations on the substrate surface to form nuclei. After the crystal nuclei are formed, they will gradually grow and become grains of a certain size. Compared with flat surfaces, it is easier to form nuclei on concave surfaces.

[0031] Internal light trapping: Keep the light that enters the battery inside the battery as much as possible, thereby increasing the light absorption rate of the silicon matrix and reducing the proportion of light escaping to the outside of the battery.

[0032] In some embodiments, Figure 2 As shown, the rough structure 31 is an uneven texture structure etched on the surface of the transparent conductive layer 3. The surface adjacent to the polysilicon layer 4 of the transparent conductive layer 3 is a rough surface, which has a good diffuse reflection effect and can randomize the direction of light incident on the interface, thereby increasing the total reflection ratio and enhancing the light trapping effect inside the battery. The rough surface can be achieved by a roughening process such as plasma etching.

[0033] In some embodiments, the transparent conductive layer 3 is a zinc oxide layer doped with Al or Ga.

[0034] In some embodiments, the thickness of the transparent conductive layer 3 is between 2 nm and 5 nm.

[0035] In some embodiments, the thickness of the tunneling silicon oxide layer 2 is 1.5±0.5 nm, which can play the role of passivation and allow electrons to tunnel through.

[0036] In some embodiments, the polysilicon layer 4 is a phosphorus-doped N-type polysilicon layer, which can transport electrons to the electrode.

[0037] In some embodiments, Figure 1 As shown, a pyramid velvet structure is formed on the front side of the N-type silicon substrate 1 .

[0038] In some embodiments, the N-type silicon substrate 1 is N-type single crystal silicon.

[0039] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0040] Figure 1 The specific manufacturing process of the TOPCon battery structure shown is as follows:

[0041] Step 1: Double-sided texturing: Double-sided texturing is performed on the N-type silicon substrate 1 to form a pyramid texture structure.

[0042] Step 2: Boron diffusion: Boron is diffused on the front side of the N-type silicon substrate 1 using a diffusion furnace to form a p-type emitter.

[0043] Step 3: Removing borosilicate glass and polishing the back surface: removing the borosilicate glass on the back surface and the side surface of the N-type silicon substrate 1, removing the velvet surface on the back surface, and making the back surface a smooth surface.

[0044] Step 4: grow a tunneling silicon oxide layer 2 + a transparent conductive layer 3 on the back side of the N-type silicon substrate 1 using LPCVD equipment or other vapor deposition equipment.

[0045] Step 5: The back side of the N-type silicon substrate 1 is subjected to plasma etching or roughening treatment in other ways to form a rough diffuse reflection layer surface on the transparent conductive layer 3 .

[0046] Step 6: deposit a phosphorus-doped polysilicon layer 4 on the back side of the N-type silicon substrate 1, clean and remove the borosilicate glass layer on the front side and the phosphorus-silicate glass layer on the back side, and polish the back side again to form a smooth back plane.

[0047] Step 7: Deposit an aluminum oxide film layer 8 on the front surface of the N-type silicon substrate 1 using an ALD device.

[0048] Step 8: Use PECVD equipment to deposit silicon nitride layers on both sides of the silicon wafer and print and sinter electrodes to obtain the final TOPCon battery.

[0049] ALD technology is a special vacuum thin film deposition method with high technical barriers. ALD technology forms a thin film by alternately passing gas phase precursor pulses into the reaction chamber and causing surface saturated chemical reactions on the deposition substrate. The ALD coating equipment can deposit the material layer by layer on the substrate surface in the form of a single atomic layer. Each coating time / layer is an atomic layer. According to the atomic properties, 10 coating times / layer is about 1nm.

[0050] Chemical vapor deposition (CVD) is a technology that uses various energy sources such as heating, plasma or light radiation to cause gaseous or vaporous chemicals to react in the gas phase or at the gas-solid interface in a reactor to form solid deposits. It is a process for depositing thin films on the surface of a substrate through a chemical reaction of gas mixtures, and can be applied to the deposition of insulating films, hard mask layers and metal film layers.

[0051] The TOPCON cell structure provided by the utility model is prepared by the above method, and a transparent conductive layer with a rough diffuse reflection surface on the bottom is inserted between the back tunneling silicon oxide layer and the polysilicon layer, which can randomize the direction of light entering the cell, increase the proportion of total reflection light, and reduce the proportion of light escaping to the outside of the cell, thereby increasing light absorption and improving cell efficiency. Inserting a transparent conductive layer at this position is the best choice, which does not affect the velvet design of the front of the cell, nor the passivation effect of the back of the cell, and does not affect the back electrode printing, and can also improve the uniformity of the grain size of the polysilicon layer, thereby improving the electrical performance of the polysilicon layer.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A TOPCON cell structure, comprising an N-type silicon substrate (1), characterized in that: The back side of the N-type silicon substrate (1) is provided with a tunneling silicon oxide layer (2), a transparent conductive layer (3), a polysilicon layer (4), a back silicon nitride layer (5) and a back metal electrode (6) in sequence from the inside to the outside, and the front side is provided with a P-type emitter (7), an aluminum oxide film layer (8), a front silicon nitride layer (9) and a front metal electrode (10) in sequence from the inside to the outside; a rough structure (31) is provided on the surface where the transparent conductive layer (3) is in contact with the polysilicon layer (4).

2. The TOPCON battery structure according to claim 1, characterized in that: The rough structure (31) is a concave-convex texture structure etched on the surface of the transparent conductive layer (3).

3. The TOPCON battery structure according to claim 1, characterized in that: The transparent conductive layer (3) is a zinc oxide layer doped with Al or Ga.

4. The TOPCON battery structure according to claim 1, characterized in that: The thickness of the transparent conductive layer (3) is between 2 nm and 5 nm.

5. The TOPCON battery structure according to claim 1, characterized in that: The thickness of the tunneling silicon oxide layer (2) is 1.5±0.5 nm.

6. The TOPCON battery structure according to claim 1, characterized in that: The polysilicon layer (4) is a phosphorus-doped N-type polysilicon layer.

7. The TOPCON battery structure according to claim 1, characterized in that: A pyramid velvet structure is formed on the front surface of the N-type silicon substrate (1).

8. The TOPCON battery structure according to claim 1, characterized in that: The N-type silicon substrate (1) is N-type single crystal silicon.

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