Signal processing circuit and electronic device

Abstract

The embodiment of the utility model discloses a signal processing circuit and electronic equipment. The signal processing circuit comprises a pixel array, k analog signal continuous cache accumulation circuits and k quantitative threshold comparison circuits, wherein the pixel array is composed of m rows * n columns of pixel units; wherein each analog signal continuous cache accumulation circuit corresponds to at least one column of pixel units, and each quantitative threshold comparison circuit corresponds to one analog signal continuous cache accumulation circuit; m and n are integers greater than or equal to 1 respectively; the pixel array outputs n reset signals and target signals and respectively sends the n reset signals and the target signals to the k analog signal continuous cache accumulation circuits; one end of the analog signal continuous cache accumulation circuit is connected with the pixel unit, and the other end of the analog signal continuous cache accumulation circuit is connected with the quantitative threshold comparison circuit; and the quantitative threshold comparison circuit is used for receiving the accumulation signal output by the analog signal continuous cache accumulation circuit and determining whether to output the pulse signal according to the accumulation signal.

Description

Technical Field

[0001] The present disclosure relates to the field of sensor technology, and in particular to a signal processing circuit and an electronic device. Background Art

[0002] Image sensors have been widely used in digital cameras, mobile phones, medical treatment, automobiles, drones, machine recognition and other fields. In particular, the rapid development of complementary metal oxide semiconductor (CMOS) image sensor technology has led to higher requirements for the output image quality of image sensors. CMOS image sensors can be divided into two categories based on the signal acquisition method: one method is to set the exposure time for the pixel and then measure the change in voltage signal; the second method is to set the voltage change for the pixel and then measure the exposure time. This type of image sensor is called a pulse sequence image sensor. Pulse sequence image sensors need to be reset during signal acquisition, but there is no effective way to suppress the noise introduced by the reset signal during signal processing. Utility Model Content

[0003] According to one aspect of an embodiment of the present disclosure, a signal processing circuit is provided, comprising: a pixel array consisting of m rows and n columns of pixel units, k analog signal continuous cache accumulation circuits, and k quantitative threshold comparison circuits; wherein each analog signal continuous cache accumulation circuit corresponds to at least one column of the pixel units, and each quantitative threshold comparison circuit corresponds to one analog signal continuous cache accumulation circuit; m and n are integers greater than or equal to 1, respectively;

[0004] The pixel array is used to quantize pixel signals of each row of pixel units row by row according to the control of an external control signal, output n reset signals and target signals and send them to k analog signal continuous buffer accumulation circuits respectively;

[0005] One end of the analog signal continuous buffer accumulation circuit is connected to the pixel unit, and the other end is connected to the quantitative threshold comparison circuit. When receiving the reset signal output from the pixel unit, the analog signal continuous buffer accumulation circuit latches the signal; when receiving the target signal output from the pixel unit, the analog signal continuous buffer accumulation circuit accumulates the target signal and outputs the accumulated signal to the quantitative threshold comparison circuit;

[0006] The quantitative threshold comparison circuit is used to receive the accumulated signal output by the analog signal continuous buffer accumulation circuit, and determine whether to output the pulse signal according to the accumulated signal.

[0007] Optionally, the analog signal continuous buffer accumulation circuit includes: a capacitor and a signal latch circuit;

[0008] The negative plate of the capacitor is connected to the output end of the pixel unit to receive a reset signal or a target signal output by the pixel unit, and the positive plate of the capacitor is connected to one end of the signal latch circuit;

[0009] One end of the signal latch circuit is connected to the positive plate of the capacitor, and the other end is connected to the quantitative threshold comparison circuit, and is used to latch the signal of the positive plate of the capacitor when the negative plate of the capacitor receives the reset signal according to the control of the external latch signal; when the negative plate of the capacitor receives the target signal, transmit the target signal to the positive plate of the capacitor.

[0010] Optionally, the signal latch circuit includes an analog voltage buffer and a signal latch switch connected in parallel;

[0011] One end of the analog voltage buffer is connected to the positive plate of the capacitor, and the other end is connected to the quantitative threshold comparison circuit as the output end of the analog signal continuous buffer accumulation circuit;

[0012] The signal latch switch is turned off or on according to the control of the external latch signal. In response to the signal latch switch being turned on, the analog voltage buffer latches the signal of the positive plate of the capacitor; in response to the signal latch switch being turned off, the positive plate of the capacitor changes following the signal change of the negative plate of the capacitor.

[0013] Optionally, the positive plate of the capacitor is also connected to a preset reset signal via at least one switching transistor.

[0014] Optionally, the at least one switching transistor comprises a first switching transistor and a second switching transistor;

[0015] The source of the first switch transistor is connected to the preset reset signal, the drain is connected to the positive plate of the capacitor, and the gate receives an initial control signal;

[0016] The source of the second switch transistor is connected to the preset reset signal, the drain is connected to the positive plate of the capacitor, and the gate receives the pulse signal output by the quantitative threshold comparison circuit.

[0017] Optionally, the negative plate of the capacitor is also connected to a bias current source.

[0018] Optionally, the quantitative threshold comparison circuit includes: a comparator, wherein the positive input terminal of the comparator receives the accumulated signal output by the analog signal continuous cache accumulation circuit, and the negative input terminal receives a preset threshold signal, and in response to the accumulated signal being greater than the preset threshold signal, a pulse signal is output through the output terminal.

[0019] According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, comprising: a processor, and a memory communicatively connected to the processor, and further comprising the signal processing circuit according to any one of the embodiments;

[0020] The memory stores computer-executable instructions;

[0021] The processor executes computer-implemented instructions stored in the memory to control the signal processing circuit.

[0022] Optionally, the electronic device is included in any one of the following: a pulse camera, a high-speed camera, an audio / video player, a navigation device, a fixed-position terminal, an entertainment unit, a smart phone, a communication device, a device in a motor vehicle, a camera, a sports or wearable camera, a detection device, a flight device, a medical device, a security device.

[0023] A signal processing circuit and an electronic device provided based on the above-mentioned embodiments of the present disclosure include: a pixel array composed of m rows and n columns of pixel units, k analog signal continuous cache accumulation circuits, and k quantitative threshold comparison circuits; wherein each analog signal continuous cache accumulation circuit corresponds to at least one column of the pixel units, and each quantitative threshold comparison circuit corresponds to one analog signal continuous cache accumulation circuit; m and n are integers greater than or equal to 1 respectively; the pixel array is used to quantize the pixel signals of the pixel units in each row row by row according to the control of an external control signal, output n reset signals and target signals and send them to the k analog signal continuous cache accumulation circuits respectively; one end of the analog signal continuous cache accumulation circuit is connected to the pixel unit, and the other end is connected to the pixel unit. The end is connected to the quantitative threshold comparison circuit, and the analog signal continuous cache accumulation circuit latches the signal when receiving the reset signal output from the pixel unit; when receiving the target signal output from the pixel unit, the target signal is accumulated and the obtained accumulated signal is output to the quantitative threshold comparison circuit; the quantitative threshold comparison circuit is used to receive the accumulated signal output by the analog signal continuous cache accumulation circuit, and determine whether to output the pulse signal according to the accumulated signal; the embodiment of the present disclosure realizes correlated double sampling of the reset signal and the target signal through the analog signal continuous cache accumulation circuit, realizes noise suppression through correlated double sampling, and realizes high-speed pulse sequence imaging by replacing the continuous accumulation of photogenerated charges with the accumulation of the target signal.

[0024] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0026] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0027] Figure 1 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0028] Figure 2 is a circuit structure diagram of an analog signal continuous buffer accumulation circuit in a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0029] Figure 3 is a circuit structure diagram of an analog signal continuous buffer accumulation circuit in a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0030] Figure 4 is a circuit structure diagram of an analog signal continuous buffer accumulation circuit in a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0031] Figure 5 is a circuit structure diagram of a quantitative threshold comparison circuit in a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0032] Figure 6 is a circuit structure diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0033] Figure 7 yes Figure 6 An optional example workflow diagram of the signal processing circuit shown;

[0034] Figure 8 A block diagram of an electronic device according to an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0035] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0036] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0037] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0038] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0039] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0040] In addition, the term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this disclosure generally indicates that the previous and next associated objects are in an "or" relationship. The data referred to in this disclosure may include unstructured data such as text, images, and videos, and may also be structured data.

[0041] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0042] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0043] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0044] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0045] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0046] In the process of realizing the present disclosure, the inventors found that the pulse sequence image sensor reflects the light intensity by recording the time when the photoelectric signal accumulates to a specific threshold value. Therefore, the accumulation time of the photogenerated charge is uncertain, and it is difficult to set a specific time to perform correlated double sampling on the image sensor, and correlated double sampling is an important means to suppress noise signals in the image sensor. Therefore, the inventors proposed the following technical solution to solve the noise suppression problem.

[0047] Figure 1 FIG. 1 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure. Figure 1 As shown, the signal processing circuit provided in this embodiment includes: a pixel array 110 composed of m rows and n columns of pixel units 111, k analog signal continuous cache accumulation circuits 120, and k quantitative threshold comparison circuits 130; wherein each column of analog signal continuous cache accumulation circuits 120 corresponds to at least one column of pixel units 111; m, n, k are integers greater than or equal to 1, respectively, and k can be an integer greater than or equal to 1 and less than or equal to n.

[0048] The pixel array 110 is used to quantize the pixel signals of each row of pixel units 111 row by row according to the control of the external control signal, output n reset signals and target signals and send them to k analog signal continuous cache accumulation circuits 120 respectively. Each analog signal continuous cache accumulation circuit 120 can correspond to at least one column of pixel units 111 (for example, each analog signal continuous cache accumulation circuit 120 corresponds to n / k columns of pixel units 111, and when n / k cannot be divided evenly, the quotient of n / k plus 1 is taken as the number of pixel unit columns corresponding to the analog signal continuous cache accumulation circuit, and one analog signal continuous cache accumulation circuit 120 corresponds to a smaller number of pixel unit columns). For ease of understanding, Figure 1 The illustrated embodiment shows an optional situation, namely, including n analog signal continuous buffer accumulation circuits 120 and n quantitative threshold comparison circuits 130 , and each analog signal continuous buffer accumulation circuit 120 corresponds to a column of pixel units 111 .

[0049] In this embodiment, the structure of the pixel unit 111 can be any pixel structure in the prior art that can output a reset signal and a target signal, for example, a pixel unit with a 4T structure in the prior art.

[0050] One end of the analog signal continuous cache accumulation circuit 120 is connected to the pixel unit 111, and the other end is connected to the quantitative threshold comparison circuit 130. When the analog signal continuous cache accumulation circuit 120 receives the reset signal output from the pixel unit 111, it latches the signal; when receiving the target signal output from the pixel unit 111, it accumulates the target signal and outputs the obtained accumulated signal to the quantitative threshold comparison circuit 130.

[0051] In this embodiment, double sampling of the reset signal and the target signal is achieved through the analog signal continuous cache accumulation circuit 120, and the problem of the noise signal introduced into the reset signal is solved by signal latching. By accumulating the target signal, the accumulation of the target signal replaces the continuous accumulation of the photogenerated charge.

[0052] The quantitative threshold comparison circuit 130 is used to receive the accumulated signal output by the analog signal continuous buffer accumulation circuit 120, and determine whether to output a pulse signal according to the accumulated signal.

[0053] In this embodiment, the quantitative threshold comparison circuit 130 determines whether to output a pulse signal according to the accumulated signal. Optionally, the quantitative threshold comparison circuit 130 may include a comparison circuit, for example, to compare the accumulated signal with a preset threshold signal, and determine whether to output a pulse signal based on the comparison result. In response to the output pulse signal, the analog signal continuous buffer accumulation circuit 120 is reset according to the pulse signal.

[0054] Optionally, when the pixel array 110 performs pixel signal quantization row by row, each analog signal continuous cache accumulation circuit 120 performs pixel signal quantization on the corresponding at least one pixel unit 111 one by one, and when the analog signal continuous cache accumulation circuit 120 performs target signal accumulation, it targets the target signal of the same pixel unit 111. Figure 1 In the illustrated embodiment, when a row of pixel units 111 performs pixel signal quantization, the analog signal continuous buffer accumulation circuit 120 accumulates the target signals output by the corresponding pixel units 111 in the row.

[0055] Optionally, the target signal may include at least one of the following signals: a pulse signal, a potential signal, a finite value, and the like.

[0056] In this embodiment, the analog signal continuous cache accumulation circuit 120 accumulates the target signal input by a pixel unit 111 in turn, and only when the accumulated signal is greater than the preset threshold signal, the pulse signal is output through the quantitative threshold comparison circuit 130, so that the greater the light intensity, the denser the pulse signal output, and the smaller the light intensity, the sparser the pulse signal output; therefore, by reading the time interval between the pulse signals, the light intensity can be evaluated to complete the image sensing function.

[0057] The above embodiment of the present disclosure provides a signal processing circuit, comprising: a pixel array composed of m rows and n columns of pixel units, k analog signal continuous cache accumulation circuits, and k quantitative threshold comparison circuits; wherein each analog signal continuous cache accumulation circuit corresponds to at least one column of the pixel units, and each quantitative threshold comparison circuit corresponds to one analog signal continuous cache accumulation circuit; m, n, and k are integers greater than or equal to 1 respectively; the pixel array is used to quantize pixel signals of each row of the pixel units row by row according to the control of an external control signal, output n reset signals and target signals and send them to k analog signal continuous cache accumulation circuits respectively; one end of the analog signal continuous cache accumulation circuit is connected to the pixel unit, and the other end is connected to the The quantitative threshold comparison circuit is connected, and the analog signal continuous cache accumulation circuit latches the signal when receiving the reset signal output from the pixel unit; when receiving the target signal output from the pixel unit, the target signal is accumulated, and the obtained accumulated signal is output to the quantitative threshold comparison circuit; the quantitative threshold comparison circuit is used to receive the accumulated signal output by the analog signal continuous cache accumulation circuit, and determine whether to output the pulse signal according to the accumulated signal; the embodiment of the present disclosure realizes correlated double sampling of the reset signal and the target signal through the analog signal continuous cache accumulation circuit, realizes noise suppression through correlated double sampling, and realizes high-speed pulse sequence imaging by replacing the continuous accumulation of photogenerated charges with the accumulation of the target signal.

[0058] Figure 2 FIG. 1 is a schematic diagram of a circuit structure of an analog signal continuous buffer accumulation circuit in a signal processing circuit provided by another exemplary embodiment of the present disclosure. Figure 2 As shown, the analog signal continuous buffer accumulation circuit 120 includes: a capacitor 121 and a signal latch circuit 122 .

[0059] The negative plate of the capacitor 121 is connected to the output end of the pixel unit 111 for receiving a reset signal or a target signal output by the pixel unit 111 , and the positive plate of the capacitor 121 is connected to one end of the signal latch circuit 122 .

[0060] One end of the signal latch circuit 122 is connected to the positive plate of the capacitor 121, and the other end is connected to the quantitative threshold comparison circuit 130. It is used to latch the signal Vc1 of the positive plate of the capacitor when the negative plate of the capacitor receives a reset signal according to the control of the external latch signal; when the negative plate of the capacitor receives a target signal, the target signal is transmitted to the positive plate of the capacitor.

[0061] In this embodiment, the characteristics of the capacitor are utilized, and the negative plate of the capacitor is used as the input end of the analog signal continuous buffer accumulation circuit 120 to receive the reset signal or the target signal; when receiving the reset signal, considering the existence of noise, the signal of the positive plate of the capacitor is latched by the signal latch circuit 122 at this time. Since the signal is latched, the signal Vc1 of the positive plate of the capacitor does not change with the signal Vc2 of the negative plate of the capacitor, thereby isolating the influence of the noise on the signal Vc1 of the positive plate of the capacitor. When receiving the target signal, the signal latch circuit 122 does not latch the signal Vc1 of the positive plate of the capacitor. At this time, the signal Vc1 of the positive plate of the capacitor changes with the signal Vc2 of the negative plate of the capacitor, and the target signal is stored on the positive plate of the capacitor. After receiving the target signal for many times, the target signal is accumulated on the positive plate of the capacitor. At this time, the signal Vc2 accumulated on the positive plate of the capacitor does not include the noise signal introduced by the reset signal, thereby removing the influence of the noise on the target signal, improving the accuracy of the accumulated signal, and further improving the accuracy of the output pulse signal.

[0062] Figure 3 FIG. 1 is a circuit structure diagram of a continuous buffer accumulation circuit for analog signals in a signal processing circuit provided by another exemplary embodiment of the present disclosure. Figure 3 As shown, the signal latch circuit 122 includes an analog voltage buffer 123 and a signal latch switch 124 connected in parallel.

[0063] Optionally, one end of the signal latch switch 124 is connected to the input end of the analog voltage buffer 123, and the other end of the signal latch switch 124 is connected to the output end of the analog voltage buffer 123. When the signal latch switch 124 is turned on, the input end and the output end of the analog voltage buffer 123 are short-circuited together. At this time, the signal Vc1 of the positive plate of the capacitor is latched, and no matter how the signal Vc2 of the negative plate of the capacitor changes, the signal Vc1 of the positive plate of the capacitor does not change. The analog voltage buffer in this embodiment is a common circuit unit in an analog circuit, and its basic characteristic is that the output signal is always equal to the input signal. The internal circuit structure of the analog voltage buffer can be of various designs and is an existing technology, so it is not repeated. Those skilled in the art should understand that all analog voltage buffers that can achieve an output signal that is always equal to the input signal can be applied to the embodiments provided in the present disclosure.

[0064] Optionally, the analog voltage buffer may also be implemented by an adder in the prior art.

[0065] One end of the analog voltage buffer 123 is connected to the positive plate of the capacitor 121 , and the other end is connected to the quantitative threshold comparison circuit 130 as the output end of the analog signal continuous buffer accumulation circuit 120 .

[0066] The signal latch switch 124 is turned on or off according to the control of the external latch signal. In response to the signal latch switch 124 being turned on, the analog voltage buffer 123 latches the signal Vc1 of the positive plate of the capacitor; in response to the signal latch switch 124 being turned off, the signal Vc1 of the positive plate of the capacitor changes following the change of the signal Vc2 of the negative plate of the capacitor.

[0067] In this embodiment, the control of the latch signal of the analog voltage buffer 123 is implemented by the signal latch switch 124, and its external latch signal corresponds to the reset signal received in the pixel unit 121. When the pixel unit outputs the reset signal according to the control, the signal latch switch 124 receives the corresponding external latch signal to control the analog voltage buffer 123 to latch the signal Vc1 of the positive plate of the capacitor, so as to avoid the noise signal contained in the reset signal affecting the generation of the pulse signal.

[0068] like Figure 3 As shown, the positive plate of the capacitor is also connected to the preset reset signal Vr through at least one switching transistor 125 (for ease of understanding and display, only one switching transistor is shown in this embodiment), and in response to one switching transistor in at least one switching transistor (when multiple switching transistors are included, multiple switching transistors are connected in parallel, and only one switching transistor needs to be turned on to connect the preset reset signal Vr with the positive plate of the capacitor) being turned on, the positive plate of the capacitor is reset according to the preset reset signal Vr.

[0069] By resetting, the voltage signal Vc1 of the positive plate of the capacitor is reset to Vr. Usually, the resetting of the positive plate of the capacitor is performed before the analog signal continuous cache accumulation circuit receives the signal. Moreover, since the analog signal continuous cache accumulation circuit 120 needs to be used to accumulate the target signal, after the high-level pulse signal is output, the signal Vc1 of the positive plate of the capacitor also needs to be reset to avoid signal accumulation errors. Based on the above problems, in another optional embodiment of the present disclosure, if Figure 4 As shown, at least one switch transistor 125 includes a first switch transistor 1251 and a second switch transistor 1252;

[0070] The source of the first switch transistor 1251 is connected to the preset reset signal Vr, the drain is connected to the positive plate of the capacitor, and the gate receives the initial control signal. In response to the initial control signal being at a high level, the positive plate of the capacitor is reset by the preset reset signal Vr.

[0071] The source of the second switching transistor 1252 is connected to the preset reset signal Vr, the drain is connected to the positive plate of the capacitor, and the gate receives the pulse signal output by the quantitative threshold comparison circuit 130. In response to the pulse signal being at a high level, the positive plate of the capacitor is reset by the preset reset signal Vr.

[0072] In this embodiment, the positive plate of the capacitor is connected to the preset reset signal Vr through two switch transistors (the first switch transistor 1251 and the second switch transistor 1252). In response to one of the two switch transistors being turned on, the positive plate of the capacitor is reset according to the preset reset signal Vr. The first switch transistor 1251 and the second switch transistor 1252 provided in this embodiment are respectively connected to the preset reset signal Vr and the positive plate of the capacitor. When the positive plate of the capacitor is initially reset, the initial control signal can be input to the gate of the first switch transistor 1251 to turn on the first switch transistor 1251. The gate of the second switch transistor 1252 is connected to the output end of the quantitative threshold comparison circuit 130. When the pulse signal output by the quantitative threshold comparison circuit 130 is at a high level, the second switch transistor 1252 is turned on, and then the positive plate of the capacitor is reset by the preset reset signal Vr, and the signal Vc1 of the positive plate of the capacitor is reset to Vr, so that the target signal output by the pixel unit next time is obtained, and then the next pulse signal is accumulated.

[0073] Optionally, the negative plate of the capacitor is also connected to a bias current source 126, one end of the bias current source 126 is connected to the negative plate of the capacitor, and the other end is grounded GND. With the assistance of the bias current source 126, the signal output by the pixel unit 111 can flow smoothly into the negative plate of the capacitor.

[0074] In some optional embodiments, Figure 5 1 is a circuit structure diagram of a quantitative threshold comparison circuit in a signal processing circuit provided by an exemplary embodiment of the present disclosure. The quantitative threshold comparison circuit 130 includes: a comparator 131, wherein the positive input terminal of the comparator 131 receives the accumulated signal output by the analog signal continuous buffer accumulation circuit 120, and the negative input terminal receives the preset threshold signal Vth. In response to the accumulated signal being greater than the preset threshold signal Vth, a pulse signal is output through the output terminal.

[0075] Figure 6 FIG. 1 is a circuit structure diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure. Figure 6 As shown, in this embodiment, only a single pixel unit 111 is taken as an example to illustrate the connection relationship between the pixel unit 111 and various components included in the analog signal continuous buffer accumulation circuit 120.

[0076] In this embodiment, the pixel unit 111 is a common 4T structure pixel unit, including a photodiode PD, a transfer transistor TX, a floating diffusion capacitor FD, a reset transistor Rst, a source follower SF, and a row selection transistor Sel.

[0077] The photodiode PD is used to collect photogenerated charges. When the transfer transistor TX is turned on, the photogenerated charges collected by the photodiode PD are transferred to the floating diffusion capacitor FD. One end of the floating diffusion capacitor FD is grounded GND, and the other end is connected to the reset transistor Rst and the power signal VDD.

[0078] Optionally, the floating diffusion capacitor FD is reset when the reset transistor Rst is turned on; when the reset transistor Rst is turned off and the transfer transistor TX is turned on, the floating diffusion capacitor FD receives the photogenerated charges generated by the photodiode PD.

[0079] In this embodiment, the floating diffusion capacitor FD is a common structure in the pixel unit of the 4T structure. The light detection function is realized by the floating diffusion capacitor FD, and when the transfer transistor TX is turned on, the photogenerated charge generated in the photodiode PD is read to the floating diffusion capacitor FD. Optionally, when the reset transistor Rst is turned on, the floating diffusion capacitor FD is turned on with the power supply signal VDD to reset the floating diffusion capacitor FD and charge the voltage on the floating diffusion capacitor FD to a high level. Under illumination conditions, photogenerated charges are generated in both the photodiode PD and the floating diffusion capacitor FD, wherein the voltage on the floating diffusion capacitor FD gradually decreases under the action of the photogenerated charges. Normally, the floating diffusion capacitor FD is reset before the photogenerated charges are generated.

[0080] The source follower SF has a gate terminal connected to the floating diffusion capacitor FD, a source terminal connected to the row selection transistor Sel, and a drain terminal receiving a power supply signal VDD; it is used to detect and follow the charge change of the floating diffusion capacitor FD to determine the target signal.

[0081] The drain terminal of the row selection transistor Sel is connected to the source terminal of the source follower SF, the source terminal is connected to the analog signal continuous buffer accumulation circuit 120, the gate terminal receives an external control signal, and determines whether to output the target signal according to the control of the external control signal.

[0082] In this embodiment, the gate terminal of the source follower SF is connected to the floating diffusion capacitor FD, and follows the potential change of the floating diffusion capacitor FD to obtain a potential signal. This process does not affect the photoelectric conversion of the photodiode PD. Under the premise that the transfer transistor TX is disconnected, the source follower SF reads the potential change of the floating diffusion capacitor FD, and the photodiode PD continues to perform photoelectric conversion to collect charge. The row selection transistor Sel selects whether to output the target signal according to the control of the external control signal. The external control signal can be an external clock signal or an external pulse signal, etc.; the timing of the external control signal is set according to the specific scenario. Optionally, based on the external clock circuit, an external control signal can be sent regularly to control the row selection transistor Sel to output the target signal.

[0083] In this embodiment, the analog signal continuous buffering and accumulating circuit 120 includes: a capacitor 121, an analog voltage buffer 123, a signal latch switch 124, a first switch transistor 1251 and a second switch transistor 1252; the quantitative threshold comparison circuit 130 includes a comparator 131. The analog signal continuous buffering and accumulating circuit 120 also includes a bias current source 126.

[0084] The negative terminal of the capacitor 121 is connected to the output terminal of the pixel unit 111 and the bias current source 126 ; the positive plate of the capacitor 121 is connected to the analog voltage buffer 123 and one end of the signal latch switch 124 .

[0085] After the analog voltage buffer 123 is connected in parallel with the signal latch switch 124, the input end is connected to the positive plate of the capacitor, and the output end is connected to the positive input end of the comparator 131, so as to output the accumulated signal to the comparator 131. One end of the analog voltage buffer 123 is also connected to the preset reset signal Vr through the first switch transistor 1251 and the second switch transistor 1252 respectively.

[0086] The positive input terminal of the comparator 131 is connected to the output terminal of the analog voltage buffer 123 to receive the accumulated signal, the negative input terminal is connected to the preset threshold signal Vth, and the output terminal outputs a pulse signal. Optionally, the output terminal of the comparator 131 is also connected to the gate of the second switch transistor 1252, and the pulse signal is used to control whether the second switch transistor 1252 is turned on.

[0087] In some optional embodiments, Figure 7 yes Figure 6 An optional example workflow diagram of the signal processing circuit shown in FIG. Figure 7 The following stages may be included:

[0088] First, before performing signal processing, it is necessary to perform an initial reset on the analog signal continuous cache accumulation circuit 120. Initial reset stage: the first switch transistor 1251 is turned on according to the control of the initial control signal (only a high level is given in the initial reset stage, and the subsequent process is a low level, that is, the first switch transistor 1251 is subsequently disconnected), and the upper plate of the capacitor (corresponding to the positive plate of the capacitor in the above embodiment) is reset to a preset reset signal Vr (the signal can be a preset voltage value, and the specific value can be set according to the specific application scenario). In this stage, the pixel unit 111 is not started and no operation is performed.

[0089] Exposure phase: the pixel unit 111 is activated, and the photogenerated charges are collected and stored through the photodiode PD.

[0090] Reset signal sampling stage: the reset transistor Rst in the pixel unit 111 is turned on according to the control of the clock signal sent by the row controller, and the power signal VDD resets the floating diffusion capacitor FD. The reset signal is input to the lower plate of the capacitor (corresponding to the negative plate of the capacitor in the above embodiment) through the source follower SF. At this time, the signal latch switch 124 remains closed, and the analog voltage buffer 123 performs signal latching. Therefore, the capacitor upper plate voltage Vc1 is maintained at Vr, and the capacitor lower plate voltage Vc2 is equal to the reset signal read this time. Considering the existence of noise, the capacitor lower plate voltage Vc2 = Vnoise1 at this time, and Vnoise1 represents the reset signal including noise.

[0091] Exposure signal (corresponding to the target signal in the above embodiment) sampling stage: the transfer transistor TX is turned on, and the photogenerated charge on the photodiode PD is transferred to the floating diffusion capacitor FD, and is input to the lower plate of the capacitor through the source follower SF. At this time, the signal latch switch 124 is disconnected, so the capacitor upper plate voltage Vc1 will change with the voltage change of the capacitor lower plate voltage Vc2. The capacitor lower plate voltage Vc2 is superimposed on the target signal V1 and changes from Vnoise1 to Vnoise1+V1, and the capacitor upper plate voltage Vc1 also changes by the same amount, so the capacitor upper plate voltage Vc1 changes from Vr to Vr+V1. It can be seen that the signal of the capacitor upper plate voltage Vc1 has removed the influence of noise, realizing the function of correlated double sampling.

[0092] Pulse generation stage: the comparator 131 determines whether the capacitor upper plate voltage Vc1 reaches the preset threshold signal Vth. If it reaches the specific threshold, a pulse signal is output and the pulse signal is input to the gate terminal of the second switching transistor 1252. The capacitor upper plate is reset through the second switching transistor 1252. If it does not reach the specific threshold, no pulse signal is generated and no reset is performed. The capacitor upper plate voltage Vc1 continues to accumulate in the next working cycle.

[0093] To illustrate the continuous accumulation function of the signal processing circuit provided by the present invention, the working process of the next exposure cycle is described below when no pulse signal is generated in the previous exposure cycle. When no pulse signal is generated, the following exposure stage, reset signal sampling stage, exposure signal sampling stage and pulse generation stage are repeatedly executed.

[0094] Exposure phase: Photogenerated charges are collected and stored by the photodiode PD.

[0095] Reset signal sampling stage: the reset transistor Rst in the pixel unit 111 is turned on according to the control of the clock signal sent by the row controller, and the power signal VDD resets the floating diffusion capacitor FD. The reset signal is input to the lower plate of the capacitor (corresponding to the negative plate of the capacitor in the above embodiment) through the source follower SF. At this time, the signal latch switch 124 remains closed, and the analog voltage buffer 123 performs signal latching, so the capacitor upper plate voltage Vc1 is maintained at Vr+V1, and the signal of the capacitor lower plate voltage Vc2 is equal to the reset signal read out this time. Considering the existence of noise, the capacitor lower plate voltage Vc2=Vnoise2 at this time, and Vnoise2 represents the reset signal including noise.

[0096] Exposure signal sampling stage: the transfer transistor TX is turned on, and the photogenerated charge on the photodiode PD is transferred to the floating diffusion capacitor FD, and is input to the lower plate of the capacitor through the source follower SF. At this time, the signal latch switch 124 is disconnected, so the capacitor upper plate voltage Vc1 will change with the change of the capacitor lower plate voltage Vc2. The capacitor lower plate voltage Vc2 superimposed on the exposure signal changes from Vnoise2 to Vnoise1+V2, and the capacitor upper plate voltage Vc1 also changes by the same amount, so the capacitor upper plate voltage Vc1 changes from Vr+V1 to Vr+V1+V2. It can be seen that the signal of the capacitor upper plate voltage Vc1 has removed the influence of noise, realizing the function of correlated double sampling, and also realizing the accumulation of two signals.

[0097] Pulse generation stage: the comparator 131 determines whether the capacitor upper plate voltage Vc1 reaches the preset threshold signal Vth. If it reaches the specific threshold, a pulse signal is output and the pulse signal is input to the gate terminal of the second switching transistor 1252. The capacitor upper plate is reset through the second switching transistor 1252. If it does not reach the specific threshold, no pulse signal is generated and no reset is performed. The capacitor upper plate voltage Vc1 continues to accumulate in the next working cycle.

[0098] In this way, the light intensity can be evaluated by reading the time interval between the pulse signals. Optionally, the shorter the time interval between the two pulse signals, the stronger the light intensity; the longer the time interval between the two pulse signals, the weaker the light intensity; thus completing the image sensing function.

[0099] According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, comprising: a processor, and a memory communicatively connected to the processor, and further comprising the signal processing circuit described in any one of the above embodiments;

[0100] The memory stores computer-executable instructions;

[0101] The processor executes computer-implemented instructions stored in the memory to control the signal processing circuit.

[0102] The electronic device provided by the present disclosure may be incorporated into any of the following: pulse cameras, high-speed cameras, audio / video players, navigation devices, fixed-position terminals, entertainment units, smart phones, communication devices, devices in motor vehicles, cameras, sports or wearable cameras, detection equipment, flight equipment, medical equipment, security equipment, etc.

[0103] The electronic device provided by the present disclosure can be applied to any of the following: pulse cameras, high-speed cameras, audio / video players, navigation equipment, fixed-position terminals, entertainment units, smart phones, communication equipment, equipment in motor vehicles, cameras, sports or wearable cameras, detection equipment, flight equipment, medical equipment, security equipment, etc.

[0104] Below, reference Figure 8 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0105] Figure 8 A block diagram of an electronic device according to an embodiment of the present disclosure is illustrated.

[0106] like Figure 8 As shown, the electronic device includes one or more processors and memory.

[0107] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0108] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the signal processing circuits and / or other desired functions of the various embodiments of the present disclosure described above.

[0109] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0110] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0111] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0112] Of course, to simplify, Figure 8 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0113] In addition to the above methods and devices, embodiments of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the signal processing circuit according to various embodiments of the present disclosure described in the above part of this specification.

[0114] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0115] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the signal processing circuit according to various embodiments of the present disclosure described in the above part of this specification.

[0116] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0117] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0118] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0119] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0120] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0121] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0122] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0123] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A signal processing circuit, characterized in that: include: A pixel array consisting of m rows and n columns of pixel units, k analog signal continuous cache accumulation circuits, and k quantitative threshold comparison circuits; wherein each analog signal continuous cache accumulation circuit corresponds to at least one column of the pixel units, and each quantitative threshold comparison circuit corresponds to one analog signal continuous cache accumulation circuit; wherein m, n, and k are integers greater than or equal to 1 respectively; The pixel array is used to quantize pixel signals of each row of pixel units row by row according to the control of an external control signal, output n reset signals and target signals and send them to k analog signal continuous buffer accumulation circuits respectively; One end of the analog signal continuous buffer accumulation circuit is connected to the pixel unit, and the other end is connected to the quantitative threshold comparison circuit. When receiving the reset signal output from the pixel unit, the analog signal continuous buffer accumulation circuit latches the signal; when receiving the target signal output from the pixel unit, the analog signal continuous buffer accumulation circuit accumulates the target signal and outputs the accumulated signal to the quantitative threshold comparison circuit; The quantitative threshold comparison circuit is used to receive the accumulated signal output by the analog signal continuous buffer accumulation circuit, and determine whether to output a pulse signal according to the accumulated signal.

2. The circuit according to claim 1, characterized in that The analog signal continuous buffer accumulation circuit comprises: a capacitor and a signal latch circuit; The negative plate of the capacitor is connected to the output end of the pixel unit to receive a reset signal or a target signal output by the pixel unit, and the positive plate of the capacitor is connected to one end of the signal latch circuit; One end of the signal latch circuit is connected to the positive plate of the capacitor, and the other end is connected to the quantitative threshold comparison circuit, and is used to latch the signal of the positive plate of the capacitor when the negative plate of the capacitor receives the reset signal according to the control of the external latch signal; when the negative plate of the capacitor receives the target signal, transmit the target signal to the positive plate of the capacitor.

3. The circuit according to claim 2, characterized in that The signal latch circuit includes an analog voltage buffer and a signal latch switch connected in parallel; One end of the analog voltage buffer is connected to the positive plate of the capacitor, and the other end is connected to the quantitative threshold comparison circuit as the output end of the analog signal continuous buffer accumulation circuit; The signal latch switch is turned off or on according to the control of the external latch signal. In response to the signal latch switch being turned on, the analog voltage buffer latches the signal of the positive plate of the capacitor; in response to the signal latch switch being turned off, the positive plate of the capacitor changes following the signal change of the negative plate of the capacitor.

4. The circuit according to claim 2, characterized in that The positive plate of the capacitor is also connected to a preset reset signal through at least one switching transistor.

5. The circuit according to claim 4, characterized in that The at least one switching transistor comprises a first switching transistor and a second switching transistor; The source of the first switch transistor is connected to the preset reset signal, the drain is connected to the positive plate of the capacitor, and the gate receives an initial control signal; The source of the second switch transistor is connected to the preset reset signal, the drain is connected to the positive plate of the capacitor, and the gate receives the pulse signal output by the quantitative threshold comparison circuit.

6. The circuit according to any one of claims 2 to 5, characterized in that: The negative plate of the capacitor is also connected to a bias current source.

7. The circuit according to any one of claims 1 to 5, characterized in that: The quantitative threshold comparison circuit includes: a comparator, wherein the positive input terminal of the comparator receives the accumulated signal output by the analog signal continuous cache accumulation circuit, and the negative input terminal receives a preset threshold signal. In response to the accumulated signal being greater than the preset threshold signal, a pulse signal is output through the output terminal.

8. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor, further comprising the signal processing circuit according to any one of claims 1 to 7; The memory stores computer-executable instructions; The processor executes computer-implemented instructions stored in the memory to control the signal processing circuit.

9. The electronic device according to claim 8, characterized in that: The electronic device is included in any of the following: pulse camera, high-speed camera, audio / video player, navigation equipment, fixed position terminal, entertainment unit, smart phone, communication equipment, equipment in motor vehicle, camera, sports or wearable camera, detection equipment, flight equipment, medical equipment, security equipment.

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