Display device

Abstract

The utility model provides a display device. The display device comprises a display panel, a printed circuit board, a time schedule controller, a memory, an I2C bus and a burr eliminating circuit. The printed circuit board is connected with the display panel. The time schedule controller is arranged on the printed circuit board. The memory is arranged on the printed circuit board. The I2C bus is arranged on the printed circuit board and is connected with the time schedule controller and the memory. And the burr eliminating circuit is connected to the I2C bus. Thus, the burr eliminating circuit plays a role in eliminating burrs possibly occurring during communication between the time schedule controller and the memory through the I2C bus, the transmission quality and stability of signals between the time schedule controller and the memory through the I2C bus are improved, and then the display effect of the display device is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] When designing a display device, the timing controller and power management chip are connected through I 2 C bus (Inter-Integrated Circuit) to achieve communication. However, when using I 2 In the case of a C bus, the display device may have display abnormalities during the display process.

[0003] Therefore, it is necessary to propose a technical solution to improve the use of display devices. 2 C bus display abnormality problem. Utility Model Content

[0004] In view of this, the present application provides a display device to improve the display effect of the display device.

[0005] In a first aspect, the present application provides a display device, the display device comprising a display panel, a printed circuit board, a timing controller, a memory, an I 2 C bus and burr elimination circuit. The printed circuit board is connected to the display panel. The timing controller is arranged on the printed circuit board. The memory is arranged on the printed circuit board. 2 The I C bus is set on the printed circuit board and connects the timing controller and the memory. The burr elimination circuit is connected to the I 2 C bus.

[0006] In some embodiments, the display device further comprises: an external interface, which is disposed on the printed circuit board and is connected to the display device through the I 2 The C bus is connected to the timing controller and the memory.

[0007] In some embodiments, the burr elimination circuit includes a crosstalk suppression unit connected to the I 2 C bus.

[0008] In some embodiments, the I 2 C bus includes:

[0009] A serial data line, comprising a first segment, a second segment and a third segment, each of the first segment, the second segment and the third segment comprising an opposite end and another end, one end of the first segment being connected to the timing controller, one end of the second segment being connected to the memory, one end of the third segment being connected to the external interface, and the other end of the first segment, the other end of the second segment and the other end of the third segment being connected to each other;

[0010] A serial clock line, comprising a fourth segment, a fifth segment and a sixth segment, each of the fourth segment, the fifth segment and the sixth segment comprising an opposite end and another end, one end of the fourth segment being connected to the timing controller, one end of the fifth segment being connected to the memory, one end of the sixth segment being connected to the external interface, and the other ends of the fourth segment, the fifth segment and the sixth segment being connected to each other;

[0011] The crosstalk suppression unit includes a first resistor connected to the first segment, and / or the crosstalk suppression unit includes a second resistor connected to the fourth segment.

[0012] In some embodiments, the crosstalk suppression unit further includes a third resistor connected to the third segment, and / or the crosstalk suppression unit further includes a fourth resistor connected to the sixth segment.

[0013] In some embodiments, the glitch elimination circuit further includes a first pull-up resistor and a first pull-up power signal terminal, one end of the first pull-up resistor is connected to the second segment, and the other end of the first pull-up resistor is connected to the first pull-up power signal terminal; and / or,

[0014] The glitch elimination circuit also includes a second pull-up resistor and a second pull-up power signal terminal, one end of the second pull-up resistor is connected to the fifth segment, and the other end of the second pull-up resistor is connected to the second pull-up power signal terminal.

[0015] In some embodiments, the I 2 C bus includes serial data line and serial clock line;

[0016] The display device further includes a ground line on the printed circuit board, wherein an orthographic projection of the ground line on the printed circuit board is at least between an orthographic projection of the serial data line on the printed circuit board and an orthographic projection of the serial clock line on the printed circuit board.

[0017] In some embodiments, a line width of the ground line is greater than a line width of at least one of the serial data line and the serial clock line.

[0018] In some embodiments, the serial data line and the serial clock line are located in different film layers, and / or at least a portion of the serial data line and at least a portion of the serial clock line are staggered.

[0019] In some embodiments, the display device further comprises:

[0020] A power management chip is disposed on the printed circuit board and is connected to the power supply via the I 2 The C bus is connected to the timing controller and the external interface.

[0021] In some embodiments of the present application, the glitch elimination circuit performs the I 2 C bus communication can eliminate the glitches that may occur during communication, and improve the signal transmission between the timing controller and the memory through I 2 C bus transmission quality and stability, thereby improving the display effect of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a planar structure of a display device provided in some embodiments of the present application;

[0023] Figure 2 for Figure 1 A partial schematic diagram of the display device shown.

[0024] The reference numerals are as follows:

[0025] 100, display device; 11, display panel; 12, gate driving circuit; 13, source driving circuit;

[0026] 14, printed circuit board; 15, flexible connection film; 16, timing controller; 17, memory; 18, external interface; 19, power management chip;

[0027] 20,I 2 C bus; 21, serial data line; 211, first segment; 212, second segment; 213, third segment; 214, seventh segment;

[0028] 22, serial clock line; 221, fourth segment; 222, fifth segment; 223, sixth segment; 224, eighth segment;

[0029] 30, burr elimination circuit; 31, crosstalk suppression unit; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, first pull-up resistor; VDD1, first pull-up power signal terminal; R6, second pull-up resistor; VDD2, second pull-up power signal terminal;

[0030] 40, grounding wire; 401, first grounding section; 402, second grounding section; 403, third grounding section; 404, fourth grounding section; 405, fifth grounding section. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0032] Please refer to Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of a planar structure of a display device provided in some embodiments of the present application, Figure 2 for Figure 1 A partial schematic diagram of the display device shown.

[0033] The display device 100 can be applied to mobile phones, tablets, laptop computers, and televisions, etc. The display device 100 can be any one of a liquid crystal display device, an organic light emitting diode display device, a quantum dot display device, a micro-light emitting diode (micro-LED) display device, and a sub-millimeter light emitting diode (mini-LED) display device.

[0034] The display device 100 includes a display panel 11, an 2 C (Inter-Integrated Circuit) bus 20 , gate driving circuit 12 , source driving circuit 13 , printed circuit board 14 , timing controller 16 and memory 17 .

[0035] The display panel 11 includes a plurality of scan lines (not shown) and a plurality of data lines (not shown), the plurality of scan lines and the plurality of data lines intersecting each other in an insulated manner. The display panel 11 also includes a plurality of display units (not shown), the display units being connected to the scan lines and the data lines.

[0036] It should be noted that, in the present application, connection may include direct connection and indirect connection. When A and B are directly connected, A and B are directly connected in contact with each other. When A and B are indirectly connected, A and B may be connected through C which is different from A and B.

[0037] The gate drive circuit 12 outputs a scan signal to the scan line. The gate drive circuit 12 can be integrated into the display panel 11 or can be bound to the display panel 11. The source drive circuit 13 outputs a data signal to the data line. The source drive circuit 13 can be directly bound to the display panel 11. The source drive circuit 13 can also be set on a flexible film, and then the flexible film is bound to the display panel 11.

[0038] Timing controller 16, I 2The C bus 20 and the memory 17 are both disposed on the printed circuit board 14. The printed circuit board 14 can be directly bound to the display panel 11, or the printed circuit board 14 can be connected to the display panel 11 through a flexible connection film 15. The flexible connection film 15 can be a chip-on-film carrying the source drive circuit 13 and / or the gate drive circuit 12, or can be a flexible circuit board.

[0039] The timing controller 16 is connected to the source driving circuit 13 and the gate driving circuit 12 to output corresponding signals to the two.

[0040] The memory 17 is used to store basic display setting information. The memory 17 may include a non-volatile memory, and the non-volatile memory includes an electrically erasable programmable read only memory (EEPROM).

[0041] I 2 The I2C bus 20 connects the timing controller 16 and the memory 17. The glitch elimination circuit 30 is connected to the I2C bus 20. In this way, the glitch elimination circuit 30 performs the communication between the timing controller 16 and the memory 17 through the I2C bus. 2 C bus 20 communication burrs to eliminate the role of improving the signal between the timing controller 16 and the memory 17 through the I 2 The transmission quality and stability of the C bus 20 can improve the display effect of the display device 100.

[0042] It should be noted that glitch refers to a short, regular or irregular pulse in the circuit output waveform, which is useless for the design or has other effects. Excessive glitch increases the risk of data signal transmission errors. When the data transmission direction sends high-level data to the non-volatile memory, if the high-level data is on the I 2 When a glitch below the normal level occurs in the transmission on the I2C bus 20, the non-volatile memory will recognize it as a low level, resulting in data transmission errors and display abnormalities. Therefore, the glitch below the normal level has a great impact on the non-volatile memory. In the present application, the glitch elimination circuit 30 is connected to the I2C bus 20, which can eliminate the glitch between the timing controller 16 and the memory 17 through the I2C bus 20. 2 The burrs during communication on the C bus 20 are eliminated, thereby improving the display effect of the display device 100.

[0043] In some embodiments, Figure 2 As shown, the display device 100 further includes an external interface 18, which is disposed on the printed circuit board 14. The external interface 18 is connected to the printed circuit board 14 by I 2The I2C bus 20 is connected to the timing controller 16 and the memory 17. In this way, the glitch elimination circuit 30 can improve the quality and stability of the voltage transmitted between the external interface 18 and the timing controller 16, and between the external interface 18 and the memory 17 through the I2C bus 20, and reduce the risk of data transmission errors between the external interface 18 and the timing controller 16 and the memory 17.

[0044] In some embodiments, Figure 2 As shown, the display device 100 further includes a power management chip 19, which is disposed on the printed circuit board 14. The power management chip 19 is connected to the gate drive circuit 12 and the source drive circuit 13 to supply power to both. 2 The C bus 20 is connected to the timing controller 16 and the external interface 18. In this way, the glitch elimination circuit 30 can improve the communication between the power management chip 19 and the timing controller 16 and between the power management chip 19 and the external interface 18 through the I 2 The quality and stability of the voltage transmitted by the C bus 20 reduces the risk of data transmission errors between the power management chip 19 and the external interface 18 and the timing controller 16.

[0045] The I2C bus 20 includes a serial data line 21 and a serial clock line 22. In some embodiments, the glitch elimination circuit 30 includes a crosstalk suppression unit 31 connected to the I 2 C bus 20. The crosstalk suppression unit 31 is on the I 2 When the C line transmits a signal, the mutual crosstalk between the serial data line 21 and the serial clock line 22 is suppressed, thereby improving the burr problem caused by the crosstalk.

[0046] The serial data line 21 includes a first segment 211, a second segment 212, a third segment 213, and a seventh segment 214 (which may be four segments connected to the black dot A, but is not limited thereto). Each of the first segment 211, the second segment 212, the third segment 213, and the seventh segment 214 includes an opposite end and the other end. One end of the first segment 211 is connected to the timing controller 16. One end of the second segment 212 is connected to the memory 17. One end of the third segment 213 is connected to the external interface 18. One end of the seventh segment 214 is connected to the power management chip 19. The other end of the first segment 211, the other end of the second segment 212, the other end of the third segment 213, and the other end of the seventh segment 214 are connected to each other. The other end of the first segment 211, the other end of the second segment 212, the other end of the third segment 213, and the other end of the seventh segment 214 may be directly connected to each other at the black dot A, or may be directly connected at two or more different positions. The other end of the first segment 211, the other end of the second segment 212, the other end of the third segment 213, and the other end of the seventh segment 214 may also be indirectly connected.

[0047] In some embodiments, the first segment 211 , the second segment 212 , the third segment 213 , and the seventh segment 214 may include at least one of a straight line segment and a non-straight line segment.

[0048] The serial clock line 22 includes a fourth segment 221, a fifth segment 222, a sixth segment 223, and an eighth segment 224 (which may be four segments connected to the black dot B, but is not limited thereto). Each of the fourth segment 221, the fifth segment 222, the sixth segment 223, and the eighth segment 224 includes an opposite end and the other end. One end of the fourth segment 221 is connected to the timing controller 16. One end of the fifth segment 222 is connected to the memory 17. One end of the sixth segment 223 is connected to the external interface 18. One end of the eighth segment 224 is connected to the power management chip 19. The other end of the fourth segment 221, the other end of the fifth segment 222, the other end of the sixth segment 223, and the other end of the eighth segment 224 are connected to each other. The other end of the fourth segment 221, the other end of the fifth segment 222, the other end of the sixth segment 223, and the other end of the eighth segment 224 may be directly connected at the black dot B, or may be directly connected at two or more different positions. The other end of the fourth segment 221, the other end of the fifth segment 222, the other end of the sixth segment 223, and the other end of the eighth segment 224 may also be indirectly connected.

[0049] In some embodiments, the fourth segment 221 , the fifth segment 222 , the sixth segment 223 , and the eighth segment 224 may include at least one of a straight line segment and a non-straight line segment.

[0050] In some embodiments, the fourth segment 221 may be disposed in parallel and spaced apart from the first segment 211. The fifth segment 222 may be disposed in parallel and spaced apart from the second segment 212. The sixth segment 223 may be disposed in parallel and spaced apart from the third segment 213. The eighth segment 224 may be disposed in parallel and spaced apart from the seventh segment 214.

[0051] In some embodiments, the crosstalk suppression unit 31 includes a first resistor R1 connected to the first segment 211, and / or the crosstalk suppression unit 31 includes a second resistor R2 connected to the fourth segment 221. In this way, the first resistor R1 and / or the second resistor R2 can reduce signal reflection and crosstalk, improve signal quality and stability, and thus eliminate I 2 The burrs when the C bus 20 transmits signals improve the quality and stability of data transmission between the timing controller 16 and any one of the external interface 18, the memory 17 and the power management chip 19.

[0052] Optionally, the crosstalk suppression unit 31 includes a first resistor R1 connected to the first segment 211, and the crosstalk suppression unit 31 also includes a second resistor R2 connected to the fourth segment 221. In this way, the quality and stability of data transmission between the timing controller 16 and any one of the external interface 18, the memory 17 and the power management chip 19 can be better improved.

[0053] In some embodiments, the first resistor R1 and the second resistor R2 may be equal to ensure that the first resistor R1 has the same effect on the serial data line 21 as the second resistor R2 has on the serial clock line 22. In other embodiments, the first resistor R1 and the second resistor R2 may be different.

[0054] In some embodiments, the resistance of the first resistor R1 and the second resistor R2 is greater than or equal to 22Ω and less than or equal to 36Ω. 2 C bus 20 glitch, and makes I 2 The signal transmitted by the C bus 20 meets the specification. If the resistance of the first resistor R1 and the second resistor R2 is too small, it is not conducive to ensuring that the I 2 The signal transmitted by the C bus 20 meets the requirements. The resistance of the first resistor R1 and the second resistor R2 is too large, which is not conducive to ensuring the I 2 The integrity of the signals transmitted by C bus 20.

[0055] In some embodiments, the crosstalk suppression unit 31 further includes a third resistor R3 connected to the third segment 213, and / or the crosstalk suppression unit 31 further includes a fourth resistor R4 connected to the sixth segment 223. In this way, the third resistor R3 and / or the fourth resistor R4 can reduce signal reflection and crosstalk, improve signal quality and stability, and thus eliminate I2 The burrs when the C bus 20 transmits signals can improve the quality and stability of data transmission between the external interface 18 and any one of the timing controller 16, the memory 17 and the power management chip 19. In addition, the third resistor R3 and the fourth resistor R4 can also improve the anti-static impact capability of the external interface 18.

[0056] Optionally, the crosstalk suppression unit 31 further includes a third resistor R3 connected to the third segment 213, and the crosstalk suppression unit 31 further includes a fourth resistor R4 connected to the sixth segment 223. In this way, the quality and stability of data transmission between the external interface 18 and any one of the timing controller 16, the memory 17 and the power management chip 19 can be better improved.

[0057] In some embodiments, the resistance of the third resistor R3 and the fourth resistor R4 is greater than or equal to 22Ω and less than or equal to 36Ω. 2 C bus 20 glitch, and makes I 2 The signal transmitted by the C bus 20 meets the specification. The resistance of the third resistor R3 and the fourth resistor R4 is too small, which is not conducive to ensuring the I 2 The signal transmitted by the C bus 20 meets the requirements. The resistance of the third resistor R3 and the fourth resistor R4 is too large, which is not conducive to ensuring the I 2 The integrity of the signals transmitted by C bus 20.

[0058] In some embodiments, the glitch elimination circuit 30 further includes a first pull-up resistor R5 and a first pull-up power signal terminal VDD1, one end of the first pull-up resistor R5 is connected to the second segment 212, and the other end of the first pull-up resistor R5 is connected to the first pull-up power signal terminal VDD1; and / or, the glitch elimination circuit 30 further includes a second pull-up resistor R6 and a second pull-up power signal terminal VDD2, one end of the second pull-up resistor R6 is connected to the fifth segment 222, and the other end of the second pull-up resistor R6 is connected to the second pull-up power signal terminal VDD2. In this way, at least one of the first pull-up resistor R5 and the second pull-up resistor R6 can pull up the signal below the normal level transmitted to the memory 17, ensuring that the memory 17 can receive the high-level signal output by the timing controller 16, etc., ensuring that the memory 17 can work normally, thereby improving the display effect of the display device 100.

[0059] Optionally, the glitch elimination circuit 30 also includes a first pull-up resistor R5 and a first pull-up power signal terminal VDD1, and the glitch elimination circuit 30 also includes a second pull-up resistor R6 and a second pull-up power signal terminal VDD2, one end of the first pull-up resistor R5 is connected to the second segment 212, the other end of the first pull-up resistor R5 is connected to the first pull-up power signal terminal VDD1, one end of the second pull-up resistor R6 is connected to the fifth segment 222, and the other end of the second pull-up resistor R6 is connected to the second pull-up power signal terminal VDD2.

[0060] In some embodiments, Figure 2 As shown, the display device 100 further includes a ground line 40 located on the printed circuit board 14, and the positive projection of the ground line 40 on the printed circuit board 14 is at least located between the positive projection of the serial data line 21 on the printed circuit board 14 and the positive projection of the serial clock line 22 on the printed circuit board 14. In this way, the ground line 40 shields the serial data line 21 and the serial clock line 22, further improving the burr problem caused by the crosstalk between the serial data line 21 and the serial clock line 22.

[0061] In some embodiments, the grounding line 40 may include a plurality of grounding segments that are interconnected and spaced apart, and the plurality of grounding segments may function as shields at different locations.

[0062] In some embodiments, the grounding line 40 may include a first grounding segment 401 , a second grounding segment 402 , a third grounding segment 403 , and a fourth grounding segment 404 , which are spaced apart and connected to each other.

[0063] The orthographic projection of the first grounding segment 401 on the printed circuit board 14 is located between the orthographic projection of the first segment 211 and the orthographic projection of the fourth segment 221 on the printed circuit board 14 , so as to shield the first segment 211 and the fourth segment 221 .

[0064] The orthographic projection of the second grounding segment 402 on the PCB 14 is located between the orthographic projections of the second segment 212 and the fifth segment 222 on the PCB 14 , so as to shield the second segment 212 and the fifth segment 222 .

[0065] The orthographic projection of the third grounding segment 403 on the PCB 14 is located between the orthographic projections of the sixth segment 223 and the third segment 213 on the PCB 14 , so as to shield the sixth segment 223 and the third segment 213 .

[0066] The orthographic projection of the fourth grounding segment 404 on the PCB 14 is located between the orthographic projections of the eighth segment 224 and the seventh segment 214 on the PCB 14 , so as to shield the seventh segment 214 and the eighth segment 224 .

[0067] In some embodiments, the width of the first grounding segment 401 may be greater than the width of at least one of the third grounding segment 403 and the fourth grounding segment 404. In this way, the first grounding segment 401 has a larger width, which can better shield the first segment 211 and the fourth segment 221, thereby better improving the quality and stability of data transmission between the timing controller 16 and any one of the external interface 18, the memory 17, and the power management chip 19.

[0068] In some embodiments, the width of the second grounding segment 402 may be greater than the width of at least one of the third grounding segment 403 and the fourth grounding segment 404. In this way, the second grounding segment 402 has a greater width, which can better shield the second segment 212 and the fifth segment 222, thereby better ensuring that the memory 17 receives signals normally to work normally, thereby improving the display effect of the display device 100.

[0069] In some embodiments, the grounding line 40 may further include a fifth grounding segment 405. The fifth grounding segment 405 is spaced apart from and connected to the first grounding segment 401 to the fourth grounding segment 404. The orthographic projection of the fifth grounding segment 405 on the printed circuit board 14 may be located in an area defined by two of the first segment 211, the second segment 212, the third segment 213, and the seventh segment 214 and two of the fourth segment 221, the fifth segment 222, the sixth segment 223, and the eighth segment 224. In this way, the fifth grounding segment 405 plays a shielding role between the segments located on both sides thereof.

[0070] In some embodiments, the orthographic projection of the fifth grounding segment 405 on the printed circuit board 14 is located in a region defined by the orthographic projections of the interconnected sixth segment 223 and the fifth segment 222 on the printed circuit board 14 and the orthographic projections of the interconnected first segment 211 and the seventh segment 214 on the printed circuit board 14, the first segment 211 intersects with the sixth segment 223 in an insulated manner, and the seventh segment 214 intersects with the fifth segment 222 in an insulated manner. In this way, the fifth grounding segment 405 shields the segments located on both sides thereof, for example, the fifth segment 222 and the first segment 211 located on both sides of the fifth grounding segment 405, and the sixth segment 223 and the seventh segment 214 located on both sides of the fifth grounding segment 405.

[0071] In some embodiments, the ground line 40 can be set on the same layer as the serial data line 21 and one of the serial clock lines 22, so that the ground line 40 can better wrap around at least one of the serial data line 21 and the serial clock line 22, and better play a shielding role between the serial data line 21 and the serial clock line 22.

[0072] In some embodiments, when the orthographic projection of the ground line 40 on the printed circuit board 14 is located between the orthographic projection of the serial data line 21 on the printed circuit board 14 and the orthographic projection of the serial clock line 22 on the printed circuit board 14, the line width of the ground line 40 is greater than the line width of at least one of the serial data line 21 and the serial clock line 22. In this way, the line width of the ground line 40 is larger, which improves the shielding effect of the ground line 40 and increases the spacing between the serial data line 21 and the serial clock line 22, further improving the burrs generated by the crosstalk between the serial data line 21 and the serial clock line 22.

[0073] It should be noted that the ground line 40 , the serial data line 21 and the serial clock line 22 may all be metal wires, for example, the ground line 40 , the serial data line 21 and the serial clock line 22 may all be copper wires formed on the printed circuit board 14 .

[0074] In some embodiments, the serial data line 21 and the serial clock line 22 are located in different film layers, and / or at least a portion of the serial data line 21 is staggered with at least a portion of the serial clock line 22. In this way, the distance between the serial data line 21 and the serial clock line 22 is increased, or the overlap between the serial data line 21 and the serial clock line 22 is reduced, further improving the burrs generated by the crosstalk between the serial data line 21 and the serial clock line 22. Optionally, the serial data line 21 and the serial clock line 22 are located in two different film layers, and a portion of the serial data line 21 is staggered with a portion of the serial clock line 22.

[0075] In summary, in the display device of some embodiments of the present application, the glitch elimination circuit performs the glitch elimination between the timing controller and the memory via I 2 C bus communication can eliminate the glitches that may occur during communication, and improve the signal transmission between the timing controller and the memory through I 2 C bus transmission quality and stability, thereby improving the display effect of the display device.

[0076] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized in that: include: Display panel; A printed circuit board connected to the display panel; A timing controller is arranged on the printed circuit board; A memory is arranged on the printed circuit board; I 2 C bus, disposed on the printed circuit board and connecting the timing controller and the memory; as well as The glitch elimination circuit is connected to the I 2 C bus.

2. The display device according to claim 1, characterized in that The display device further includes: The external interface is arranged on the printed circuit board and is connected to the printed circuit board through the I 2 The C bus is connected to the timing controller and the memory.

3. The display device according to claim 2, characterized in that: The burr elimination circuit includes a crosstalk suppression unit connected to the I 2 C bus.

4. The display device according to claim 3, characterized in that: I 2 C bus includes: A serial data line, comprising a first segment, a second segment and a third segment, each of the first segment, the second segment and the third segment comprising an opposite end and another end, one end of the first segment being connected to the timing controller, one end of the second segment being connected to the memory, one end of the third segment being connected to the external interface, and the other end of the first segment, the other end of the second segment and the other end of the third segment being connected to each other; A serial clock line, comprising a fourth segment, a fifth segment and a sixth segment, each of the fourth segment, the fifth segment and the sixth segment comprising an opposite end and another end, one end of the fourth segment being connected to the timing controller, one end of the fifth segment being connected to the memory, one end of the sixth segment being connected to the external interface, and the other ends of the fourth segment, the fifth segment and the sixth segment being connected to each other; The crosstalk suppression unit includes a first resistor connected to the first segment, and / or the crosstalk suppression unit includes a second resistor connected to the fourth segment.

5. The display device according to claim 4, characterized in that: The crosstalk suppression unit further includes a third resistor connected to the third segment, and / or the crosstalk suppression unit further includes a fourth resistor connected to the sixth segment.

6. The display device according to claim 4, characterized in that: The glitch elimination circuit further includes a first pull-up resistor and a first pull-up power signal terminal, one end of the first pull-up resistor is connected to the second segment, and the other end of the first pull-up resistor is connected to the first pull-up power signal terminal; and / or, The glitch elimination circuit also includes a second pull-up resistor and a second pull-up power signal terminal, one end of the second pull-up resistor is connected to the fifth segment, and the other end of the second pull-up resistor is connected to the second pull-up power signal terminal.

7. The display device according to claim 1, characterized in that I 2 C bus includes serial data line and serial clock line; The display device further includes a ground line on the printed circuit board, wherein an orthographic projection of the ground line on the printed circuit board is at least between an orthographic projection of the serial data line on the printed circuit board and an orthographic projection of the serial clock line on the printed circuit board.

8. The display device according to claim 7, characterized in that: The line width of the ground line is greater than the line width of at least one of the serial data line and the serial clock line.

9. The display device according to claim 7, characterized in that: The serial data line and the serial clock line are respectively located in different film layers, and / or at least a portion of the serial data line and at least a portion of the serial clock line are staggered.

10. The display device according to any one of claims 2 to 6, characterized in that: The display device further includes: A power management chip is disposed on the printed circuit board and is connected to the power supply via the I 2 The C bus is connected to the timing controller and the external interface.

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