Semiconductor structure

Abstract

A semiconductor structure includes a first semiconductor substrate, a first interconnect structure, a second interconnect structure, a metal-containing through-silicon via, and a dielectric through-silicon via. A first interconnect structure is on a front side of the first semiconductor substrate. A second interconnect structure is on the backside of the first semiconductor substrate. A metal-containing through silicon via passes through the first semiconductor substrate and is electrically coupled with the first interconnect structure and the second interconnect structure. The dielectric through silicon via passes through the first semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid development. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each generation of circuits is smaller and more complex than the previous generation. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and in order to achieve these advances, similar developments in integrated circuit processing and manufacturing are needed.

[0003] In the process of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally brings benefits by improving production efficiency and reducing related costs. This shrinking also produces relatively high power dissipation values, which can be addressed by using low-power devices, such as complementary metal-oxide-semiconductor (CMOS) devices. Utility Model Content

[0004] In some embodiments, a semiconductor structure includes a first semiconductor substrate, a first interconnect structure, a second interconnect structure, a metal-containing through-silicon via, and a dielectric through-silicon via. The first interconnect structure is located on the front side of the first semiconductor substrate. The second interconnect structure is located on the back side of the first semiconductor substrate. The metal-containing through-silicon via passes through the first semiconductor substrate and is electrically coupled to the first interconnect structure and the second interconnect structure. The dielectric through-silicon via passes through the first semiconductor substrate.

[0005] In some embodiments, a semiconductor structure includes a substrate, a semiconductor element, a first source / drain contact, a front-side interconnect structure, a first dielectric through-silicon via, and a back-side interconnect structure. The semiconductor element is located on the front side of the substrate, wherein the semiconductor element includes a channel region, a gate structure spanning the channel region, and a plurality of source / drain regions located on the channel region and on opposite sides of the gate structure. The first source / drain contact is located on a first of the plurality of source / drain regions. The front-side interconnect structure is located on the first source / drain contact. The first dielectric through-silicon via passes through the substrate from a cross-sectional view, wherein from a top view, the first dielectric through-silicon via overlaps with the first source / drain contact. The back-side interconnect structure is located on the back side of the substrate, wherein the back side surface of the first dielectric through-silicon via contacts the back-side interconnect structure.

[0006] In some embodiments, a semiconductor structure includes a substrate, an interconnect structure, a dielectric through-silicon via, and a redistribution layer. The interconnect structure is located on the front side of the substrate. The dielectric through-silicon via extends from the back side of the substrate to the interconnect structure. The redistribution layer is located on the back side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practices in the industry, various features are not drawn to scale and are only used for illustration purposes. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A A schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown;

[0009] Figure 1B Draws the Figure 1A A schematic top view of a semiconductor structure corresponding to the region in FIG.

[0010] Figure 1C and Figure 1D According to some embodiments of the present disclosure, Figure 1B a schematic top view of the corresponding semiconductor structure;

[0011] Figure 1E , Figure 1F and Figure 1G According to some embodiments of the present disclosure, Figure 1A a schematic cross-sectional view corresponding to the obtained cross-sectional view;

[0012] Figure 2 and Figure 3 A schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown;

[0013] Figures 4A to 4K , Figure 4M and Fig.4O depicts a cross-sectional view of an intermediate stage of forming a semiconductor structure according to some embodiments;

[0014] Figure 4L , Figure 4N and Figure 4P According to some embodiments of the present disclosure, Figure 4K , Figure 4M and Fig.4O Schematic cross-sectional views of the semiconductor structures respectively corresponding thereto;

[0015] Figures 4Q to 4T According to some embodiments of the present disclosure, Fig.4Ocorresponding schematic cross-sectional views of different semiconductor structures;

[0016] FIG. 5A to FIG. 5I , Figure 5K and Figure 5M depicts a cross-sectional view of an intermediate stage of forming a semiconductor structure according to some embodiments;

[0017] Figure 5J , Figure 5L and Figure 5N According to some embodiments of the present disclosure, Fig.5I , Figure 5K and Figure 5M Schematic cross-sectional views of the semiconductor structures respectively corresponding thereto;

[0018] FIG. 5O to FIG. 5T According to some embodiments of the present disclosure, Fig.5I Schematic cross-sectional views of corresponding different semiconductor structures.

[0019]

Explanation of symbols

[0020] 100:Carrier wafer

[0021] 101: Adhesive

[0022] 102: Back-end process structure

[0023] 102f: Surface

[0024] 103: Front-end process structure

[0025] 104: Base material

[0026] 104b: back surface

[0027] 105:Connection pad

[0028] 106: Hard Mask Layer

[0029] 107: Photoresist layer

[0030] 109:Redistribute structure

[0031] 109a: dielectric layer

[0032] 109b: conductive layer

[0033] 110: Heat dissipation element

[0034] 114c: Dielectric layer

[0035] 119a: Dielectric Through Silicon Via

[0036] 119b:Through Silicon Via

[0037] 119c:Through Silicon Via

[0038] 119d:Through Silicon Via

[0039] 119e:Through Silicon Via

[0040] 119s: Dorsal surface

[0041] 129a: Through silicon via opening

[0042] 149: Dielectric materials

[0043] 152: Back-end process structure

[0044] 153:Front-end process structure

[0045] 154: Base material

[0046] 162: and back-end process structure

[0047] 162f: Surface

[0048] 163:Front-end process structure

[0049] 164: Base material

[0050] 200: Base material

[0051] 201: Etching stop layer

[0052] 202: Covering layer

[0053] 202b: Dorsal

[0054] 203: Front-end process structure

[0055] 204: Bonding dielectric structure

[0056] 205:Carrier wafer

[0057] 206: Hard Mask Layer

[0058] 206b: Backside interconnection structure

[0059] 207: Photoresist layer

[0060] 208b: Metallization layer

[0061] 210b: Dielectric layer

[0062] 213: Back-end process structure

[0063] 214b: Interconnection structure

[0064] 214c: Dielectric layer

[0065] 214d: Dielectric layer

[0066] 214e: Dielectric layer

[0067] 218d:Built-in power cord

[0068] 218e:Built-in power cord

[0069] 219a:Through Silicon Via

[0070] 219b:Through Silicon Via

[0071] 219c:Through Silicon Via

[0072] 219d:Through Silicon Via

[0073] 219e:Through Silicon Via

[0074] 229a: Through silicon via opening

[0075] 249: Dielectric materials

[0076] 300:Semiconductor structure

[0077] 302: Base material

[0078] 302b: back surface

[0079] 302f: front side

[0080] 303: Fin structure

[0081] 303b: Dorsal

[0082] 304:Semiconductor components

[0083] 305: shallow trench isolation area

[0084] 306a: front-side interconnection structure

[0085] 306b: Backside interconnection structure

[0086] 307: Gate structure

[0087] 308a: Metallization layer

[0088] 308b: Metallization layer

[0089] 310a: dielectric layer

[0090] 310b: dielectric layer

[0091] 311a: Dielectric layer

[0092] 311b: Dielectric layer

[0093] 312: Contact

[0094] 313: Interlayer dielectric layer

[0095] 314a: Wire

[0096] 314b: Wire

[0097] 315: Source / drain region

[0098] 316a: Conductive via

[0099] 316b: Conductive via

[0100] 318:Built-in power cord

[0101] 318b: back surface

[0102] 317: Interval structure

[0103] 319a:Through Silicon Via

[0104] 319b:Through Silicon Via

[0105] 319c:Through Silicon Via

[0106] 319f: front surface

[0107] 319k: back surface

[0108] 319r: front surface

[0109] 319s: dorsal surface

[0110] 329a: Through Silicon Via Opening

[0111] 329b: Through Silicon Via Opening

[0112] 329c: Through Silicon Via Opening

[0113] 339b: Isolation layer

[0114] 339c: Isolation layer

[0115] 401:Semiconductor fins

[0116] 402: Base material

[0117] 402f: front surface

[0118] 403:Semiconductor fins

[0119] 407: Gate structure

[0120] 407a: gate dielectric layer

[0121] 407b: work function layer

[0122] 407c: Gate electrode layer

[0123] 411: Dielectric layer

[0124] 412: Source / drain contact

[0125] 415: Source / drain region

[0126] 417: Gate spacing

[0127] 419a: Dielectric Through Silicon Via

[0128] 514: Dielectric layer

[0129] 600:Semiconductor Structure

[0130] 602: Heat sink

[0131] 610: Redistribute structure

[0132] 611: Patterned conductive layer

[0133] 619a: Dielectric Through Silicon Via

[0134] 619s: Surface

[0135] 620:Through Silicon Via

[0136] 622: Lining

[0137] 623: Empty Area

[0138] 629a: Through Silicon Via Opening

[0139] 630: Component packaging

[0140] 632:Semiconductor substrate

[0141] 634: Connecting element

[0142] 640: Component packaging

[0143] 641: Back-end process structure

[0144] 641s: Surface

[0145] 642:Semiconductor substrate

[0146] 643: Dielectric layer

[0147] 644: Connecting element

[0148] 644b:Signal line

[0149] X: Direction

[0150] Z: Direction

[0151] Y: direction DETAILED DESCRIPTION

[0152] Many different embodiments or examples for implementing the different features of the present disclosure are provided below. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and do not limit the scope of the present disclosure. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features are formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or text in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0153] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "on," and other related terms) are used herein to simply describe the relationship of an element or feature as shown in the figures to another element or feature. During use or operation, these spatially relative terms encompass different orientations of the elements in addition to the orientation shown in the figures. Furthermore, the elements may be rotated (90 degrees or other angles), and the spatially relative descriptors used herein may be interpreted accordingly.

[0154] As used herein, "about," "roughly," "approximately," or "substantially" may mean within 20%, within 10%, or within 5% of a given value or range. However, those skilled in the art will appreciate that the values ​​or ranges listed throughout the description are merely examples and may decrease as integrated circuits shrink. The values ​​disclosed herein are approximate, meaning that the terms "about," "roughly," "approximately," or "substantially" may be inferred if not explicitly stated.

[0155] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this disclosure, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined herein.

[0156] Embodiments of the present disclosure relate to, but are not limited to, fin-like field-effect transistor (FinFET) devices. For example, the fin-like field-effect transistor device can be a complementary metal oxide semiconductor (CMOS) device, including a P-type metal oxide semiconductor (PMOS) fin field effect transistor device and an N-type metal oxide semiconductor (NMOS) fin field effect transistor device. The following disclosure will continue with one or more fin field effect transistor examples to illustrate various embodiments of the present disclosure. However, it is understood that the application should not be limited to a specific type of device unless otherwise stated.

[0157] The fin structure can be patterned using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a smaller pitch than can be obtained with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fin.

[0158] The gate all around (GAA) transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a smaller pitch than can be obtained with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the gate surround structure.

[0159] The present disclosure relates to integrated circuit (IC) structures and methods for forming the same. More specifically, some embodiments of the present disclosure relate to gate wraparound devices including improved isolation structures to reduce current leakage from a channel to a substrate. The gate wraparound device includes a device having a gate structure or a portion thereof formed on four sides of a channel region (e.g., surrounding a portion of the channel region). The channel region of the gate wraparound device may include a nanosheet channel, a rod-shaped channel, and / or other suitable channel configurations. In some embodiments, the channel region of the gate wraparound device may have a plurality of horizontal nanosheets or vertically spaced horizontal strips, such that the gate wraparound device is a stacked horizontal gate wraparound (S-HGAA) device. The gate wraparound device presented herein includes a p-type metal oxide semiconductor gate wraparound device and an n-type metal oxide semiconductor gate wraparound device stacked together. In addition, the gate wraparound device may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure or multiple gate structures. A person of ordinary skill may recognize other examples of semiconductor devices that may benefit from various aspects of the present disclosure. In some embodiments, a nanosheet may be interchangeably referred to as a nanowire, a nanoslab, a nanoring, or a nanostructure having a nanoscale size (e.g., a few nanometers), depending on its geometry. In addition, embodiments of the present disclosure may also be applied to various metal oxide semiconductor transistors (e.g., complementary-field effect transistors (CFETs) and fin field effect transistors).

[0160] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects for use in planar components, such as planar FETs or FinFETs. For example, a FinFET may include fins located on a substrate that serve as a channel region for the FinFET. Similarly, a planar FET may include a substrate, portions of which serve as a channel region for the planar FET.

[0161] In the integrated circuit evolution process, functional density (i.e., the number of interconnected elements per wafer area) generally increases, while geometry size (i.e., the smallest component (or line) that can be created using the process) decreases. However, the smaller and denser the metal wires in the integrated circuit structure, the higher the thermal density and the poorer the thermal dissipation performance. The increase in thermal density in the integrated circuit structure may lead to electromigration and reliability issues. Therefore, nano through-silicon vias (nano through-silicon vias) or dummy thermal through-silicon vias (TSVs) that connect the front side of the wafer to the back side of the wafer to form the back side wiring of the wafer can be provided in 3D packaging to improve the heat dissipation in the integrated circuit structure. However, the metal in the nano through-silicon vias and dummy thermal through-silicon vias can cause parasitic capacitance and / or induce leakage circuits, which in turn affect the performance of the integrated circuit structure.

[0162] Therefore, various embodiments of the present disclosure provide a through-silicon via made of a dielectric material having a higher thermal conductivity than a substrate to improve heat dissipation of an integrated circuit structure. The through-silicon via may be metal-free. The dielectric through-silicon via may be used as a heat sink for the integrated circuit structure to discharge heat generated by semiconductor components from local hot spots in the circuit to outside the integrated circuit structure. In some embodiments, the thermal conductivity of the dielectric through-silicon via may be greater than about 150 W / m / K (kth). Because the dielectric through-silicon via may be metal-free, parasitic capacitance is not generated in the integrated circuit structure around the dielectric through-silicon via, which in turn prevents additional leakage paths in the integrated circuit structure, thereby improving the performance of the integrated circuit structure.

[0163] Reference Figure 1A and Figure 1B . Figure 1A A schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown. Figure 1B Draws the Figure 1A Schematic top view of the semiconductor structure corresponding to the region in FIG. Figure 1AAs shown, semiconductor structure 300 may include a substrate 302. Substrate 302 may include, for example, polysilicon, with or without doping, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, a semiconductor dielectric substrate includes a semiconductor material layer, such as silicon, formed on a dielectric layer. The dielectric layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The dielectric layer is disposed on a substrate, such as a silicon substrate or a glass substrate. In addition, substrate 302 may also include another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination of these. Other substrates, such as multilayer substrates or gradient substrates, may also be used.

[0164] In some embodiments, one or more active and / or passive components (eg, semiconductor component 304) may be formed on the front side 302f of the substrate 302, such as Figure 1A As shown. The one or more active and / or passive components may include various N-type metal oxide semiconductor (NMOS) and / or P-type metal oxide semiconductor (PMOS) components, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc. Professionals will understand that the above examples are provided for illustrative purposes only and are not intended to limit the present disclosure in any way. Other circuits may also be formed according to a given application. In the depicted embodiment, the semiconductor element 304 is a three-dimensional metal oxide semiconductor field effect transistor (MOSFET) structure formed in a fin structure of a semiconductor protrusion referred to as a fin structure 303. Figure 1AThe cross section shown is taken in a direction perpendicular to the long axis of the fin. In some embodiments, the fin structure 303 can be interchangeably referred to as a channel region, a channel pattern, a fin structure, a fin pattern, or a semiconductor strip. The fin structure 303 can be formed by patterning the substrate 302 using photolithography and etching techniques from the front side of the substrate 302. For example, a spatial image transfer (SIT) patterning technique can be used. In this method, a sacrificial layer is formed on the substrate and patterned into a chip using appropriate photolithography and etching processes. A self-alignment process is used to form a spacer next to the chip. Then, the sacrificial layer is removed by an appropriate selective etching process. Each remaining spacer can be used as a hard mask to etch a groove in the substrate 302 to pattern the respective fin structures 303 by, for example, reactive ion etching (RIE). In some embodiments, the substrate 302 can include any number of fins. In some other embodiments, the semiconductor element 304 can be a planar transistor or a gate-around transistor.

[0165] In some embodiments, Figure 1A and Figure 1BA shallow trench isolation (STI) region 305 is shown formed on opposing sidewalls of the fin structure 303 and a buried power rail 318 is formed in the shallow trench isolation region 305. The shallow trench isolation region 305 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trench around the fin and then lowering the top surface of the dielectric material. The dielectric material of the shallow trench isolation region 305 can be deposited using high density plasma chemical vapor deposition (HDP-CVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric CVD (SACVD), flowable CVD (FCVD), spin coating, and / or other similar, or combinations thereof. After deposition, a heat treatment or curing process can be performed. In some cases, the shallow trench isolation region 305 may include a substrate, such as a thermal oxide substrate grown by oxidizing a silicon surface. The recessing process may use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)) followed by a selective etching process (e.g., wet etching or dry etching, or a combination thereof), which may recess the top surface of the dielectric material of the shallow trench isolation region 305, so that the upper portion of the fin structure 303 protrudes from the surrounding dielectric shallow trench isolation region 305. In some cases, the patterned hard mask used to form the fin structure 303 may also be removed by the planarization process. In some embodiments, the buried power line 318 can be formed by forming a trench across the shallow trench isolation region 305 and into the substrate 302 from the front side 302f of the substrate 302. Then, a conductive material is filled into the trench to form the buried power line 318. The conductive material may include a metal, such as tungsten (W), ruthenium (Ru), aluminum (Al), copper (Cu), or other suitable conductive materials. In some embodiments, the conductive material may be deposited by chemical vapor deposition, physical vapor deposition (PVD), sputtering deposition, or other suitable techniques for depositing conductive materials.

[0166] In some embodiments, Figure 1A and Figure 1B The gate structure 307 of the semiconductor device 304 is shown (see Figure 1B) is a high-k metal gate (HKMG) structure that can be formed using a gate-last process flow. In the gate-last process flow, after the shallow trench isolation region 305 is formed, a sacrificial dummy gate structure (not shown) is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, or the like) may be deposited. Next, a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, or the like) may be deposited on the dummy gate dielectric and then planarized (e.g., by chemical mechanical polishing). A hard mask layer (e.g., silicon nitride, silicon carbide, or the like) may be formed on the dummy gate material. The dummy gate structure is then formed by patterning the hard mask and transferring the pattern to the dummy gate dielectric and the dummy gate material using suitable lithography and etching techniques. The dummy gate structure may extend along multiple sides of the protruding fin and extend across the fin on the surface of the shallow trench isolation region 305. As described in detail below, the dummy gate structure may be Figure 1A and Figure 1B 307 is replaced by the gate structure 307 depicted in . The materials used to form the dummy gate structure and the hard mask may be deposited using any suitable method, such as chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (atomic layer deposition, ALD), plasma enhanced atomic layer deposition (plasma-enhanced ALD, PEALD) or the like, or by thermal oxidation of the semiconductor surface, or a combination of these methods. In some embodiments, the gate structure 307 can be interchangeably referred to as a gate, a functional gate, a gate strip, a gate pattern, or a gate layer.

[0167] like Figure 1B As shown, a spacer 317 is formed, for example, to be self-aligned with the dummy gate structure. Figure 1B As shown, the spacer structure 317 may be formed by depositing and anisotropically etching a spacer structure dielectric layer after the dummy gate patterning is completed. The spacer structure dielectric layer may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof. The anisotropic etching process removes the spacer structure dielectric layer from the top of the dummy gate structure so that the spacer structure 317 extends along the sidewall of the dummy gate structure and laterally to a portion of the surface of the fin structure 303.

[0168] like Figure 1A As shown, a source / drain region 315 of the semiconductor element 304 is formed. Figure 1AAs shown, the source / drain region 315 is a semiconductor region that is in direct contact with the semiconductor fin structure 303. In some embodiments, the source / drain region 315 may include a highly doped region and a relatively lightly doped drain extension region, or a lightly doped source / drain (LDD) region. Typically, the highly doped region is spaced apart from the dummy gate structure using a spacer structure 317, and the lightly doped source / drain region may be formed before forming the spacer structure 317, and therefore, may be below the spacer structure 317 and further extend to the portion of the semiconductor fin structure 303 under the dummy gate structure in some embodiments. For example, it can be formed by implanting dopants (e.g., As, P, B, In, or the like) using an ion implantation process. The source / drain region 315 may include an epitaxial growth region. For example, after forming the lightly doped source / drain regions, the spacer structure 317 is formed, and then the heavily doped source and drain regions can be formed by first etching the fins to form recesses, and then by depositing a crystalline semiconductor material in the recesses through a selective epitaxial growth process to align the spacer structure 317. This may fill the recesses and may further extend beyond the original surface of the fin structure 303 to form an epitaxial structure of the raised source / drain regions. The crystalline semiconductor material may be an element (e.g., Si, or Ge, or the like), or an alloy (e.g., Si 1-x C x , or Si 1-x Ge x , or the like). The selective epitaxial growth process may use any suitable epitaxial growth method, such as vapor / solid / liquid phase epitaxy (VPE / SPE / LPE), or metal-organic chemical vapor deposition (MOCVD), or molecular beam epitaxy (MBE), or the like. High dose (e.g., from about 30 14 cm -2 to 30 16 cm -2) may introduce heavily doped source and drain regions 315 in an ion implantation process performed during or after selective epitaxial growth, or a combination thereof. In some embodiments, the source / drain region 315 may be alternately referred to as a source / drain structure, a source / drain pattern, an epitaxial structure, or an epitaxial pattern. In semiconductor components such as transistors, "source" and "drain" may refer to ports or regions for charge carriers (electrons or holes) of two input or output components. "Source" is the portion of a transistor where charge carriers come from. In an N-type transistor, the charge carriers are electrons, and in a P-type transistor, the charge carriers are holes. "Drain" is where the charge carriers go. The gate is the control port of the transistor. By applying a voltage to the gate, the flow of charge carriers from the source to the drain can be controlled. Therefore, in semiconductor components, the term "source / drain" refers to the region that inputs (e.g., source) and collects (e.g., drain) charge carriers to flow with a current controlled by the gate voltage.

[0169] Once the source / drain regions 315 are formed, an interlayer dielectric layer 313 is deposited on the source / drain regions 315. In some embodiments, a contact etch stop layer (CESL) of a suitable dielectric (e.g., silicon nitride, silicon carbide, etc., or a combination thereof) may be deposited (not shown) prior to depositing the dielectric material. A planarization process (e.g., chemical mechanical polishing) may be performed to remove excess dielectric material and any remaining hard mask material on the dummy gate to form a top surface, wherein the top surface of the dummy gate material is exposed and may be substantially coplanar with the top surface of the interlayer dielectric layer 313. Next, the gate structure 307 may be formed by first removing the dummy gate structure using one or more etching techniques to create recesses between corresponding spacer structures 317, such as Figure 1B Next, a replacement gate dielectric layer composed of one or more dielectric materials is deposited, and then a replacement gate metal layer composed of one or more metals is deposited to completely fill the groove. Excessive portions of the gate structure layer can be removed from the top surface of the interlayer dielectric layer 313 by, for example, a chemical mechanical polishing process. Figure 1BAs shown, the final structure may include the remaining portion of the high-k metal gate layer, which is embedded between the corresponding spacer structures 317. In some embodiments, the dielectric material forming the interlayer dielectric layer 313 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low-k dielectrics such as fluorosilicate glass (FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (CDO), flowable oxide, or porous oxide (e.g., dry glue / aerogel), etc., or a combination thereof. The dielectric material forming the interlayer dielectric layer 313 can be deposited using any suitable method, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, shallow trench isolation layer deposition, chemical vapor deposition, spin coating, etc., or a combination thereof.

[0170] The gate dielectric layer may include, for example, a high-k dielectric material, such as metal oxides and / or silicates (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti and other metals), silicon nitride, silicon oxide, etc., or combinations thereof, or multilayers thereof. In some embodiments, the gate metal layer may be a multilayer metal gate stack consisting of a barrier layer, a work function layer, and a gate fill layer, which are formed one by one on the gate dielectric layer. Example materials for the barrier layer include TiN, TaN, Ti, Ta, etc., or multilayer combinations thereof. The work function layer may include TiN, TaN, Ru, Mo, Al for p-type field effect transistors, and Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, etc. for n-type field effect transistors. Other suitable work function materials, or combinations thereof, or multilayers thereof may be used. The gate filling layer filling the remaining groove may include a metal such as Cu, Al, W, Co, Ru, etc., or a combination thereof, or a multilayer thereof. The material forming the gate structure may be deposited by any suitable method, such as chemical vapor deposition, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, etc.

[0171] In some embodiments, contacts 312 are formed through source / drain regions 315 to electrically connect the overlying front-side interconnect structure 306a and the underlying semiconductor device 304, such as Figure 1A and Figure 1B As shown. Figure 1A As shown, semiconductor element 304 can be electrically connected to conductive lines 314a and conductive vias 316a using contacts 312 formed through a dielectric layer. Figure 1A In the example shown, the contact 312 is electrically connected to the source / drain region 315 of the semiconductor element 304. The contact 312 may be formed using photolithography, etching and deposition techniques. For example, a patterned mask may be formed on the interlayer dielectric layer 313 and used to etch an opening through the interlayer dielectric layer 313 to expose the gate structure 307 and the source / drain region 315. Then, a conductive substrate may be formed in the opening of the interlayer dielectric layer 313. Subsequently, the opening is filled with a conductive filling material. The substrate includes a barrier metal to reduce the diffusion of conductive material from the contact 312 into the surrounding dielectric material. In some embodiments, the substrate may include two barrier metal layers. The first barrier metal contacts the semiconductor material of the source / drain region 315 and may chemically react with the heavily doped semiconductor of the source / drain region 315 to form a low-impedance ohmic contact, and then the unreacted metal may be removed. For example, if the heavily doped semiconductor of the source / drain region 315 is silicon or a silicon-germanium alloy semiconductor, the first barrier metal layer may include Ti, Ni, Pt, Co, other suitable metals, or alloys thereof, and may form a silicide with the source / drain region 315. The second barrier metal layer of the conductive substrate may also include other metals (e.g., TiN, TaN, Ta, or other suitable metals, or alloys thereof). The conductive fill material (e.g., W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, etc.) may be deposited on the conductive substrate layer using any acceptable deposition technique (e.g., chemical vapor deposition, ALD, PEALD, PECVD, PVD, ECP, electroless plating, or the like, or any combination thereof) to fill the contact opening. Next, a planarization process (e.g., CMP) may be used to remove any excess of the conductive material from the surface of the interlayer dielectric layer 313. The resulting conductive layer extends into the interlayer dielectric layer 313 and forms contacts 312, making physical and electrical connections to the electrodes of the electronic device, e.g. Figure 1A The semiconductor element 304 is shown. In some embodiments, the contacts 312 may be referred to interchangeably as source / drain contacts or source / drain plugs.

[0172] After forming the contact 312, a front-side interconnect structure 306a including multiple interconnect layers may be formed according to a back-end ofline (BEOL) scheme adopted for integrated circuit design and stacked vertically above the contact layer 312. Figure 1A In the back-end process scheme shown, the various interconnect layers have similar characteristics. However, it is understood that other embodiments may use alternative integration schemes, in which the various interconnect layers may use different characteristics. For example, the contact 312 shown as a vertical connection element may be extended to form a wire that transmits current laterally. In some embodiments, the front-side interconnect structure 306a electrically connects one or more active and / or passive devices to form a functional circuit in the semiconductor structure 300. The front-side interconnect structure 306a may include one or more metallization layers 308a. In some embodiments, the number of metallization layers may vary according to the design specifications of the semiconductor structure 300. The metallization layers 308a include dielectric layers 310a and 311a, respectively. The dielectric layer 311 is formed on the corresponding dielectric layer 310a. The metallization layer 308a includes one or more horizontal interconnects, such as wires 314a extending horizontally or laterally in the dielectric layer 311 and conductive vias 316a extending vertically in the dielectric layer 310a. Conductive wire 314a and conductive via 316a may be formed using any suitable method, such as a single damascene process, a dual damascene process, or the like. In some embodiments, dielectric layers 310a and 311a may include a low dielectric constant dielectric material, such as a material with a dielectric constant value of less than about 4.0 or even 2.0, configured between such conductor characteristics. In some embodiments, the dielectric layer may be made of, for example, phosphate glass, borophosphate glass, fluorosilicate glass, SiO x C y, spin-coated glass, spin-coated polymer, silicon oxide, silicon nitride, combinations thereof, or the like, and may be formed using any suitable method, such as spin coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition, or the like. The conductive wire 314a and the conductive via 316a may include conductive materials such as copper, aluminum, tungsten, combinations thereof, or the like. In some embodiments, the conductive wire 314a, and the conductive via 316a may further include one or more barrier / adhesion layers (not shown) to protect the corresponding dielectric layers 310a and 311a from metal diffusion (e.g., copper diffusion) and metal poisoning. The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. Forming the front-side interconnect structure 306a may be referred to as a back-end process. In some embodiments, the front-side interconnect structure 306a may be alternately referred to as a back-end process structure or a front-side interconnect structure. The structure before forming the front-side interconnect structure 306a may be referred to as a front-end-of-line (FEOL). In some embodiments, the structure before forming the front-side interconnect structure 306a may be alternately referred to as a front-end process structure. After forming the front-side interconnect structure 306a, the substrate 302 may be thinned from the front side of the substrate using grinding and / or wet or dry etching techniques (for example only and not limitation). In some embodiments, the substrate 302 may be alternately referred to as a thin substrate.

[0173] In the integrated circuit (IC) evolution process, the functional density (i.e., the number of interconnected devices per chip area) generally increases, while the geometric size (i.e., the smallest component (or line) that can be created using the process) decreases. However, the smaller and denser the metal lines in the integrated circuit structure, the higher the thermal density and the poorer the thermal dissipation performance. The increase in thermal density in the integrated circuit structure may lead to electromigration and reliability issues. Therefore, dummy thermal vias (nano-through silicon vias) in connecting the front side of the chip to the back side of the chip to form chip backside routing or three-dimensional (3D) packaging can be provided to improve thermal dissipation in the integrated circuit structure. However, the metal in the nano-through silicon vias and the dummy thermal conductive through silicon vias will cause parasitic capacitance and / or induce leakage paths, which in turn affect the performance of the integrated circuit structure.

[0174] Therefore, the present disclosure provides, in various embodiments, a through-silicon via 319a made of a dielectric material having a higher thermal conductivity than the substrate 302 (see Figure 1A) to improve the heat dissipation of the semiconductor structure 300. The through silicon via 319a may be metal-free. That is, the dielectric through silicon via 319a may be used as a heat sink for the semiconductor structure 300 to discharge the heat generated by the semiconductor element from the local hot spot of the circuit to the outside of the semiconductor structure 300. In some embodiments, the thermal conductivity of the dielectric through silicon via 319a may be greater than about 150W / m / K (kth). Since the dielectric through silicon via 319a may be metal-free, no parasitic capacitance is generated in the semiconductor structure 300 around the dielectric through silicon via 319a, which in turn prevents the generation of additional leakage paths in the semiconductor structure 300, thereby improving the performance of the semiconductor structure 300. In some embodiments, the dielectric through silicon via 319a may also be used in three-dimensional (3D) packaging as a dummy thermal conductive through silicon via.

[0175] like Figure 1A As shown, dielectric through silicon via 319a is formed through substrate 302, shallow trench isolation region 305 and interlayer dielectric layer 313, and contacts contact 312. Dielectric through silicon via 319a can be used as a thermal path to reduce heat in the circuit. In some embodiments, dielectric through silicon via 319a can be alternately referred to as thermal conductive nano through silicon via. Specifically, forming dielectric through silicon via 319a is to form a through silicon via opening 329a, through substrate 302, shallow trench isolation region 305, and interlayer dielectric layer 313 until reaching contact 312 connected to signal, power, or ground. When defining the through silicon via opening 329a, a hard mask layer (not shown) may be formed on the back side surface 302b of the substrate 302, and then a patterned photoresist layer (not shown) is formed thereon. The hard mask layer may be a silicon nitride layer, a silicon oxynitride layer, or the like, for example but not limited thereto. The photoresist layer is patterned by exposure, baking, developing, and / or other photolithography processes to provide an open exposed hard mask layer. The exposed hard mask layer is then etched using the pattern of the photoresist layer as a masking element to provide an opening. Using the hard mask layer and the patterned photoresist layer as masking elements, an etching process is performed to etch the exposed substrate 302, the shallow trench isolation region 305, and the interlayer dielectric layer 313, and form a through silicon via opening 329a through the substrate 302, the shallow trench isolation region 305, and the interlayer dielectric layer 313. The contact 312 may also serve as an etch stop layer for etching the substrate 302 until the contact 312 is exposed. In some embodiments, the through silicon via opening 329a may be formed by performing any suitable etching process including, for example, plasma etching, chemical wet etching, laser drilling, and / or other processes. In some embodiments, the etching process includes a deep reactive ion etching process to etch the substrate 302 from the backside surface 302 b of the substrate 302 .

[0176] Subsequently, a dielectric through-silicon via 319a is formed in the through-silicon via opening 329a, and its front side surface 319f contacts the contact 312, connected to the signal, power or ground. Specifically, a dielectric material is deposited on the substrate 302 from the back side surface 302b of the substrate 302 and fills the through-silicon via opening 329a. In some embodiments, the dielectric material may have a thermal conductivity greater than about 150 W / m / K (kth), such as about 150, 285, 300, 400, 500, 600, 700, 800, 900, or 1000 W / m / K, and has a high resistivity and a rupture field strength. By way of example only and not limiting the present disclosure, the dielectric material may have a thermal conductivity of about 1×10 14 ohm×cm resistivity, for example, about 1×10 14 , 1×10 15 , 1×10 16 , or 1×10 17 ohm×cm. The dielectric material may have a rupture field strength greater than about 0.16 MV / cm, such as about 0.2, 0.3, or 0.31 MV / cm. In some embodiments, the dielectric material may include a metal oxide (e.g., beryllium oxide (BeO)) or a metal nitride (e.g., aluminum nitride (AlN)). In some embodiments, the dielectric material may include chemical vapor deposition (CVD) diamond. In some embodiments, the dielectric material is formed by a deposition process including a chemical vapor deposition process, such as high density plasma chemical vapor deposition, flowable chemical vapor deposition), etc., or a combination thereof. Other suitable materials formed by any accepted process may be used to form the dielectric through silicon via 319a. In some embodiments, there may be no metal in the through silicon via opening 329a. Subsequently, the excess portion of the dielectric material is removed by etching, chemical mechanical polishing or the like, so that the backside surface 319s of the dielectric material filling the opening is substantially planar with the backside surface 302b of the substrate 302. The remaining portion of the dielectric material in the TSV opening 329a forms a dielectric TSV 319a.

[0177] like Figure 1B As shown, most of the dielectric TSVs 319a are located on both sides of the gate structure 307. In some embodiments, the dielectric TSVs 319a may be located on the first side of the gate structure 307, rather than on the second side of the gate structure 307, which is opposite to the first side of the gate structure 307. Figure 1E As shown, two dielectric through silicon vias 419a may be located on both sides of a gate structure 407. Figure 1FAs shown, the dielectric through silicon via 419a may be located on a first side of the gate structure 407 (e.g., a side of the gate structure 407 close to the source node), rather than on a second side of the gate structure 407 (e.g., a side of the gate structure 407 close to the drain node), the second side being opposite to the first side of the gate structure 407. Figure 1G As shown, the dielectric TSV 419a may be located on the second side of the gate structure 407 instead of on the first side of the gate structure 407. Figure 1E to Figure 1G When simulating self-heating of a structure, Figure 1E The structure may have a temperature reduction of about 70°C, Figure 1F The structure may have a temperature reduction of about 47°C, Figure 1G The structure may have a temperature reduction of about 58°C. That is, a semiconductor structure having a dielectric TSV adjacent to a drain node may have a greater temperature reduction than adjacent to a source node. In addition, a semiconductor structure having dielectric TSVs on both sides of a gate structure may have a better temperature reduction than a structure having a dielectric TSV on one side of the gate structure.

[0178] Figure 1E to Figure 1G A schematic cross-sectional view of a semiconductor structure having a transistor according to some embodiments of the present disclosure is shown. Figure 1F and Figure 1G Draws the Figure 1EEmbodiments of semiconductor structures having different heat scattering paths in the semiconductor structure. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between various embodiments and / or settings. In some embodiments, these transistors may be gate-wrap field effect transistors. The silicon channel region of these transistors is formed by semiconductor fins 403. The semiconductor fins 403 are stacked on the semiconductor fins 401 on the front side surface 402f of the substrate 402 along the direction Z and are surrounded by the gate structure 407, which includes a gate dielectric layer 407a, a work function layer 407b and a gate electrode layer 407c in sequence. Direction Z is perpendicular to the plane formed by the direction X and the direction Y. Source / drain regions 415 are formed on both sides of the semiconductor fins 403. The source / drain contacts 412 are located on the source / drain regions 415. A silicide layer 416 can be formed between the source / drain contacts 412 and the source / drain regions 415 to reduce Rc. A gate spacer 417 is formed on the sidewalls of the gate structure 407. In some embodiments, the gate spacer 417 may be made of silicon nitride or silicon oxynitride, although any suitable material may be used, such as a low-k material having a k value of less than about 3.5. An inner spacer 418 may serve as an isolation feature and may be formed between the source / drain region 415 and the gate electrode layer 407c. A dielectric layer (dielectric) 411 is formed on the gate structure 407 and the source / drain region 415. In some embodiments, the dielectric layer 411 may be made of an oxide, such as phosphate glass, borate glass, boron-doped phosphate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, etc., which may be formed by a chemical vapor deposition process, such as high-density plasma, flowable chemical vapor deposition, etc., or a combination thereof.

[0179] Reference Figure 1A, through silicon via 319b is formed through substrate 302, shallow trench isolation region 305 and interlayer dielectric layer 313, and contacts contact 312, while through silicon via 319c is formed through substrate 302 and has a front side surface 319r in contact with buried power rail 318. In some embodiments, through silicon via 319b can be interchangeably referred to as signal nano through silicon via (power delivery node nano through-silicon vias), and through silicon via 319c can be interchangeably referred to as power delivery node nano through silicon via (PDN nano through silicon via). Specifically, the method of forming through silicon vias 319b and 319c is to first form through silicon via openings 329b and 329c. Specifically, the operation of forming through silicon via openings 329b and 329c is substantially the same as the operation of forming through silicon via opening 329a, as described in the above description, and therefore, for clarity, it is not repeated here. A through silicon via opening 329b is formed through the substrate 302, the shallow trench isolation region 305, and the interlayer dielectric layer 313 until a contact 312 connected to a signal, power, or ground is reached. A through silicon via opening 329c is formed through the substrate 302 until a buried power line 318 connected to power or ground is reached. In some embodiments, the operation of forming the through silicon via opening 329b may be performed simultaneously with the operation of forming the through silicon via opening 329a, so that the front side of the through silicon via opening 329b may be flush with the front side of the through silicon via opening 329a. In some embodiments, the operation of forming the through silicon via opening 329c may be performed before or after the operation of forming the through silicon via opening 329a, so that the front side of the through silicon via opening 329c may not be flush with the front side of the through silicon via opening 329a.

[0180] Subsequently, a through silicon via 319b is formed in the through silicon via opening 329b and contacts the contact 312 to connect to a signal, power or ground, and a through silicon via 319c is formed in the through silicon via opening 329c of the substrate 302 and contacts the embedded power line 318 to connect to power or ground. In more detail, the through silicon vias 319b and 319c are formed by filling the high aspect ratio openings using a metallization process and a metal plating technique to avoid seam or void defects. In some embodiments, in order to avoid diffusion of through silicon via metal into the silicon substrate, an isolation layer (barrier layer) 339b and 339c are used between the dielectric layer and the through silicon via metal. The isolation layers 339b and 339c may be attached to the inner walls of the through silicon via openings 319b and 319c. The isolation layers 339b and 339c act as diffusion barriers to prevent metal diffusion and act as adhesion layers between the metal and the dielectric. For example, but not limited to, refractory metals, refractory metal nitrides, refractory metal silicon nitrides, and combinations thereof may be used as isolation layers 339b and 339c, such as TaN, Ta, Ti, TiN, TiSiN, WN, or combinations thereof. In some embodiments, isolation layers 339b and 339c may include a TaN layer and a Ta layer. In some embodiments, isolation layers 339b and 339c may be TiN layers. In some embodiments, isolation layers 339b and 339c may be Ti layers. In some embodiments, a metal seed layer (not shown) may be subsequently formed on isolation layers 339b and 339c. In some embodiments, the metal seed layer may be a copper seed layer formed by physical vapor deposition. Subsequently, semiconductor structure 300 may be transferred to an electroplating machine, such as an electrochemical electroplating machine, and a conductive layer is plated on wafer W1 by an electroplating process to fill through-silicon via openings 329b and 329c. Although an electrochemical plating process is described herein, embodiments are not limited to electrochemical plating deposited metals. The conductive layer may include a low impedance conductor material selected from a conductor material group including but not limited to copper and copper-based alloys. Alternatively, the conductive layer may contain various materials such as tungsten, osmium, aluminum, gold, silver, etc. In some embodiments, the conductive layer is a copper-containing layer formed on a copper seed layer. Subsequently, excess portions of the conductive layer, metal seed layer, and isolation layers 339b and 339c are removed by etching, chemical mechanical polishing, or the like, so that the upper surface of the metal-filled opening is substantially coplanar with the backside surface 302b of the substrate 302. The remaining portions of the conductive layer and isolation layers 339b and 339c in the through-silicon via openings 329b and 329c form through-silicon vias 319b and 319c.

[0181] In some embodiments, the through silicon vias 319a, 319b and / or 319c may have a Figure 1B1. The through silicon via 119a, 319b and / or 319c may have a rectangular top view (or top view) cross section as shown. In addition, the through silicon via 119c may have a circular top view cross section, an elliptical top view cross section or a diamond top view cross section. In some embodiments, the through silicon vias 319a, 319b and / or 319c may have a lateral dimension of about 10nm to about 20μm. In some embodiments, the through silicon vias 319a, 319b and / or 319c may have a vertical dimension of about 50nm to about 200μm.

[0182] After forming the front-side interconnect structure 306a, the front-side interconnect structure 306a may be formed using Figure 1A The back-end process scheme shown forms a back-side interconnect structure 306b including multiple interconnect levels stacked vertically on the back side of the substrate 302. In some embodiments, the back-side interconnect structure 306b electrically connects the embedded power line 318 and the front-side interconnect structure 306a to form a functional circuit in the semiconductor structure 300. The back-side interconnect structure 306b may include one or more metallization layers 308b. In some embodiments, the number of metallization layers may vary according to the design specifications of the semiconductor structure 300. The metallization layers 308b include dielectric layers 310b and 311b, respectively. The dielectric layer 311b is formed on the corresponding dielectric layer 310b. The metallization layer 308b includes one or more horizontal interconnects, such as a wire 314b extending laterally or laterally in the dielectric layer 311b, and a vertical interconnect extending vertically in the dielectric layer 310b, such as a conductive via 316b. The backside surface 319s of the dielectric TSV 319a and / or the backside surface 319k of the dielectric TSV 319c may contact the conductive line 314b. In some embodiments, the conductive line 314b may be interchangeably referred to as a metal line or a metal strip.

[0183] In some embodiments, the conductive lines 314b and the conductive vias 316b may be formed using any suitable method, such as a single damascene process, a dual damascene process, etc. In some embodiments, the dielectric layers 310b and 311b may include low dielectric constant materials having a dielectric constant k value of less than about 4.0 or even 2.0, which are between such conductor characteristics. In some embodiments, the dielectric layers may be made of, for example, phosphate glass, borophosphate glass, fluorosilicate glass, SiO x C y, spin-coated glass, spin-coated polymer, silicon dioxide, silicon oxide nitride, combinations of these substances, etc., and can be formed by any suitable method, such as spin coating, chemical vapor deposition, plasma enhanced chemical vapor deposition, etc. The wire 314b and the conductive via 316b can include a conductor material, such as copper, aluminum, tungsten, combinations of these substances, etc. In some embodiments, the wire 314b and the conductive via 316b may further include one or more barrier / adhesion layers (not shown) to protect the corresponding dielectric layers 310b and 311b from metal diffusion (such as copper diffusion) and metal poisoning. The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, etc., and can be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. Forming the backside interconnect structure 306b can be referred to as a back end of line (BEOL) process. In some embodiments, the through-silicon vias 319 a and 319 c fall on the innermost one of the conductive lines 314 b in the metallization layer 308 b of the backside interconnect structure 306 b .

[0184] Reference Figure 1C and Figure 1D . Figure 1C and Figure 1D Some embodiments of the present disclosure correspond to Figure 1B Schematic top view of the semiconductor structure. Figure 1C and Figure 1D Draw with Figure 1A and Figure 1B Embodiments of semiconductor structures with different heat scattering paths in the semiconductor structure. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations. It should be noted that Figure 1C The implementation method and Figure 1A and Figure 1B The difference between the embodiments in FIG. 1 and FIG. 2 is that the dielectric through silicon via 319a is formed on the back side surface 318b of the buried power line 318 (see FIG. 31). Figure 1A ) as a through silicon via 319c. Therefore, the front side of the dielectric through silicon via 319a can be level with the front side of the dielectric through silicon via 319c on the back side surface of the embedded power line 318b. In addition, Figure 1D The implementation method and Figure 1A and Figure 1B The difference between the embodiments in FIG. 3 is that the dielectric through silicon via 319a is formed on the backside surface of the gate structure 307. In some embodiments, Figures 1B to 1DThe layout depicted in FIG. 1 is represented by a plurality of masks generated by one or more processors and / or stored in one or more non-transitory readable computer storage media. Other formats for representing the layout are within the scope of various embodiments. Examples of non-transitory readable computer storage media include, but are not limited to, external / removable and / or internal / built-in storage or memory elements, such as one or more optical disks, such as DVDs, magnetic disks, such as hard disks, semiconductor memory elements, such as ROM, RAM, memory cards, etc.

[0185] Reference Figure 2 . Figure 2 A schematic cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure is shown. Figure 2 Draw a Figure 1A and Figure 1B Embodiments of semiconductor structures having different heat scattering paths in the semiconductor structure. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations. It should be noted that Figure 2 The implementation method and Figure 1A and Figure 1B The difference from the embodiment in FIG. 1 is that an additional dielectric layer 514 is formed on the back side 303b of the substrate 303 and is at the same level as the innermost layer of the wire 314b in the metallization layer 308b of the backside interconnect structure 306b. The backside surface 319s of the through silicon via 319a is in contact with the dielectric layer 514, so that the through silicon via 319a and the dielectric layer 514 can serve as a heat dissipation path connecting the metal layer of the front side of the wafer and the back side of the wafer.

[0186] In some embodiments, the dielectric layer 514 may be made of a dielectric material having a thermal conductivity greater than about 150 W / m / K (kth). In some embodiments, the dielectric layer 514 may include a metal oxide (e.g., beryllium oxide (BeO)) or a metal nitride (e.g., aluminum nitride (AlN)). In some embodiments, the dielectric layer 514 may include chemical vapor deposition (CVD) diamond. In some embodiments, the dielectric layer 514 is formed by a deposition process including a chemical vapor deposition (CVD) process, such as high density plasma CVD (HDP-CVD), flow chemical vapor deposition (FCVD), the like or a combination thereof. Other suitable materials formed by any acceptable process may be used to form the dielectric layer 514. In some embodiments, the dielectric layer 514 is metal-free. For example, the dielectric layer 514 may be made of a metal oxide (e.g., beryllium oxide (BeO)), a metal nitride (e.g., aluminum nitride (AlN)), a combination thereof, or other suitable materials. In some embodiments, the dielectric layer 514 may be made of the same material as the through-silicon via 319a. In some embodiments, the dielectric layer 514 may be made of a different material than the through-silicon via 319a. In some embodiments, the dielectric layer 514 may be interchangeably referred to as a dielectric side structure.

[0187] Reference Figure 3 . Figure 3 A schematic cross-sectional view of a semiconductor structure 600 according to some embodiments of the present disclosure is shown. In some embodiments, the semiconductor structure 600 may be a three-dimensional packaging structure. Figure 3As shown, a redistribution structure 610 can be formed on a heat sink 602. In some embodiments, the redistribution structure 610 may include a dielectric layer and a patterned conductive layer 611 embedded in the dielectric layer as a redistribution conductive line. In some embodiments, one or more dielectric material layers are collectively represented as dielectric layers, and the patterned conductive layer may be a redistribution line including apertures, pads and / or traces forming electrical connections. These redistribution lines are formed layer by layer and alternately stacked on the dielectric material layer. In some embodiments, the dielectric layer may be made of polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or other suitable materials that can be made using photolithography. For example, the dielectric layer may be formed using any suitable method, such as a spin coating process, a deposition process, and the like. In some embodiments, the patterned conductive layer may be made of a conductive material, such as copper, titanium, tungsten, aluminum, a metal alloy, a combination of these, or the like). The number of dielectric layers and patterned conductive layers can be selected as required and is not limited in the present disclosure. In some embodiments, the redistribution structure 610 can be interchangeably referred to as a redistribution layer.

[0188] A device package 630 may be provided and disposed on the redistribution structure 610. Figure 3 In the figure, only one component package 630 is depicted as an example, but it should be understood that the electronic component may contain more than one semiconductor chip or different types of semiconductor chips. In some embodiments, the component package 630 is formed in a component wafer, which may include different chip areas that are singulated in a subsequent step to form a plurality of semiconductor chips 630. After singulation, the component package 630 is placed at a predetermined position by, for example, a pick-and-place process. In some embodiments, the component package 630 includes a semiconductor substrate 632 and a plurality of connecting elements 634 distributed on the semiconductor substrate 632. In some embodiments, the component package 630 is connected to the redistribution structure 610 by a die attach film (DAF) configured on the component package 630 to better adhere the component package 630 to the redistribution structure 610. Alternatively, the die attach film is omitted. The connecting element 634 is configured on the redistribution structure 610 for further electrical connection.

[0189] The semiconductor substrate 632 may include a bulk semiconductor substrate, a semiconductor dielectric bulk substrate, a multi-layer semiconductor substrate, and the like. The semiconductor material of the semiconductor substrate 632 may be silicon, germanium, a compound semiconductor (e.g., silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, indium phosphide, and the like), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, and the like), or a combination thereof. The semiconductor substrate 632 may be doped or undoped. In some embodiments, a multi-layer or gradient semiconductor substrate is used. The connecting element 634 may be or include a conductive pad (e.g., an aluminum pad, a copper pad, or other suitable metal pad) and / or a conductive pillar (e.g., a copper pillar or a copper alloy pillar). Note that the depiction of the component package 630 is simplified, and multiple layers and / or components may be included in the component package 630. The connecting element 634 and the dielectric layer 633 on the semiconductor substrate 632 are formed in a back-end-of-line (BEOL) process and may be interchangeably referred to as a back-end-of-line structure 631.

[0190] In some embodiments, the component package 630 includes integrated passive devices (IPDs). In other embodiments, the component package 630 includes active devices (e.g., transistors, etc.) and / or passive devices (e.g., resistors, capacitors, inductors, etc.) formed in and / or on the semiconductor substrate 632. For example, the component package 630 includes one or more types of chips selected from application-specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless and radio frequency chips, voltage regulator chips, or memory chips. In some embodiments, the component package 630 is a bridge chip (e.g., a silicon bridge) that may not contain active devices and / or passive devices. In other embodiments, the component package 630 as a silicon bridge includes passive devices but no built-in active devices.

[0191] A component package 640 may be provided and placed on the component package 630. The component package 640 may be electrically connected to the component package 630 through the connection element 634. Figure 3 In the embodiment, only one component package 640 is shown as an example, but it should be understood that the electronic component may include more than one semiconductor chip or different types of semiconductor chips. In some embodiments, the component package 640 includes a semiconductor substrate 642 and a plurality of connecting elements 644 distributed on the semiconductor substrate 642. The connecting elements 644 are arranged on the component package 630 for further electrical connection.

[0192] The semiconductor substrate 642 may include a bulk semiconductor substrate, a semiconductor dielectric bulk substrate, a multi-layer semiconductor substrate, and the like. The semiconductor material of the semiconductor substrate 642 may be silicon, germanium, a compound semiconductor (e.g., silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, indium phosphide, and the like), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, and the like), or a combination thereof. The semiconductor substrate 642 may be doped or undoped. In some embodiments, a multi-layer or gradient semiconductor substrate is used. The connecting element 644 may be or include a conductive pad (e.g., an aluminum pad, a copper pad, or other suitable metal pad) and / or a conductive pillar (e.g., a copper pillar or a copper alloy pillar). Note that the depiction of the component package 640 is simplified, and multiple layers and / or components may be included in the component package 640. The connecting element 644 and the dielectric layer on the dielectric layer 643 are formed in a back-end-of-line (BEOL) process and may be interchangeably referred to as a back-end-of-line process structure 641. The connecting element 644 may include a ground line 644a and a signal line 644b. The signal line 644b of the connecting element 644 in the component package 640 may be electrically connected to the connecting element 634 in the component package 630 through a through silicon via 620. The through silicon via 619a may be interchangeably referred to as a signal through silicon via. The through silicon via 619a is separated by a liner 622 surrounding the through silicon via 620 to separate it from the semiconductor substrate 632. In some embodiments, the through silicon via 620 is conductive and may be or include a conductive material such as copper, aluminum, other suitable metals, the like, or a combination thereof. In some embodiments, the liner 622 may be made of a dielectric material such as silicon oxide, silicon nitride, the like, or other suitable dielectric materials. In addition, a depletion region 623 is formed to surround the TSV 620 and prevent charges from migrating from the vicinity of the TSV 620 to the semiconductor substrate 642 .

[0193] In some embodiments, the component package 640 includes integrated passive components. In other embodiments, the component package 640 includes active components (e.g., transistors or similar components) and / or passive components (e.g., resistors, capacitors, inductors, etc.) formed on or / and in the semiconductor substrate 642. For example, the component package 640 includes one or more chips selected from application-specific integrated circuit chips, analog chips, sensor chips, wireless and wireless frequency chips, voltage regulator chips, or memory chips. In some embodiments, the component package 640 is a bridge chip (e.g., a silicon bridge) that may not contain active components and / or passive components. In other embodiments, the component package 640 acting as a silicon bridge includes passive components, but no active components are built into it. Please note that Figure 3The component packages shown in the figure are only illustration examples, and other three-dimensional integrated circuit (3DIC) packages may be used. For example, component package 630 or component package 640 may include a chip-on-wafer (CoW) package, a flip chip package, a package-on-package (PoP) structure, etc. It is understood that Figure 3 The component packages 630 and 640 in FIG. 1 are shown in a simplified manner, and various features and layers may be omitted. It is also understood that Figure 3 The number of device packages shown in the figure is only an example, and one or more device packages may be placed on the redistribution structure 610. The number of device packages and the mounting method of the device packages are not limited in this disclosure.

[0194] like Figure 3 As shown, dielectric through-silicon vias 619a are formed through component packages 630 and 640 and contact conductive metal lines (not shown) in redistribution structure 610. Dielectric through-silicon vias 619a may be used to serve as heat dissipation paths to relieve heat in the circuit. In some embodiments, dielectric through-silicon vias 619a may be interchangeably referred to as thermally conductive nano-through-silicon vias. Since through-silicon vias 619a are made of a dielectric material having a higher thermal conductivity than semiconductor substrates 632 and 642, the heat dissipation efficiency of semiconductor structure 600 may be improved. Through-silicon vias 619a may be metal-free. That is, dielectric through-silicon vias 619a may be used to serve as a heat sink for semiconductor structure 600, discharging heat generated by semiconductor components at local hot spots in the circuit to outside semiconductor structure 600. In some embodiments, the thermal conductivity of dielectric through-silicon vias 619a may be greater than about 150 W / m / K (kth). Since the dielectric TSV 619 a may be metal-free, no parasitic capacitance will be generated in the semiconductor structure 600 around the dielectric TSV 619 a , thereby preventing an additional leakage path from being generated in the semiconductor structure 600 , thereby improving the performance of the semiconductor structure 600 .

[0195] Specifically, the process of forming the dielectric through-silicon via 619a is to form a through-silicon via opening 629a, passing through the component packages 630 and 640, until reaching the patterned conductive layer in the redistribution structure 610. When defining the through-silicon via opening 629a, a hard mask layer (not shown) is formed on the component package 640, and then a patterned photoresist layer (not shown) is formed thereon. The hard mask layer may be a silicon nitride layer, a silicon oxynitride layer, or the like, which is merely an example and is not restrictive. The photoresist layer is patterned by exposure, baking, developing and / or other photolithography processes to provide an opening to expose the hard mask layer. The exposed hard mask layer is then etched using the patterned photoresist layer as a mask element, such as a wet etching or dry etching process, to provide an opening. Using the hard mask layer and the patterned photoresist layer as masking elements, an etching process is performed to etch the exposed portions of the device packages 630 and 640 and form through-silicon via openings 629a through the device packages 630 and 640. The patterned conductive layer in the redistribution structure 610 may also serve as an etching stop layer for etching the device packages 630 and 640 until the patterned conductive layer in the redistribution structure 610 is exposed. In some embodiments, the through-silicon via openings 629a may be formed by performing any suitable etching process, such as a deep reactive ion etching process, plasma etching, chemical wet etching, laser drilling, and / or other processes.

[0196] Thereafter, a dielectric through-silicon via 619a is formed in the through-silicon via opening 629a and contacts the patterned conductive layer in the redistribution structure 610. Specifically, a dielectric material is deposited on the component package 640 and fills the through-silicon via opening 629a. In some embodiments, the dielectric material may have a thermal conductivity greater than about 150 W / m / K (kth). In some embodiments, the dielectric material may include a metal oxide (e.g., beryllium oxide (BeO)) or a metal nitride (e.g., aluminum nitride (AlN)). In some embodiments, the dielectric material may include chemical vapor deposition (CVD) diamond. In some embodiments, the dielectric material is formed by a deposition process including a chemical vapor deposition process, such as high-density plasma chemical vapor deposition, flow chemical vapor deposition, etc., or a combination thereof. Other suitable materials formed by any acceptable process may be used to form the dielectric through-silicon via 619a. In some embodiments, there is no metal in the TSV opening 629a. Then, the excess portion of the dielectric material is removed by etching, chemical mechanical polishing or the like, so that the surface 619s of the dielectric material filling the opening is substantially in the same plane as the surface 641s of the back-end process structure 641. The remaining portion of the dielectric material in the TSV opening 629a forms a dielectric TSV 619a.

[0197] Please refer to FIG. 4A to FIG. 4L , Figure 4N and Figure 4P . FIG. 4A to FIG. 4L , Figure 4N and Figure 4P Depicted is a cross-sectional view of an intermediate stage in the formation of a semiconductor structure according to some embodiments.

[0198] Please refer to Figure 4A . An etch stop layer 201 is formed on the substrate 200. Then, a capping layer 202 is formed on the etch stop layer 201. In some embodiments, the substrate 200 may include, for example, bulk silicon, a thin film, a pre-patterned element, a doped or undoped substance, or an active layer of a semiconductor dielectric body substrate. The substrate 200 may be in the form of a wafer and may have a circular top view shape or a rectangular top view shape. The diameter of the substrate 200 may be 3 inches, 12 inches or larger. The etch stop layer 201 may be made of a material (e.g., SiGe) having a high etching selectivity relative to the substrate 200 and the capping layer 202. In some embodiments, the capping layer 202 may be made of a semiconductor material, such as silicon.

[0199] Please refer to Figure 4B A front-end process structure 203 is formed on the cover layer 202. Then, a back-end process structure 213 is formed on the front-end process structure 203. The materials and manufacturing methods for forming the back-end process structure 213 and the front-end process structure 203 are substantially the same as the materials and manufacturing methods for forming the interconnect structure 306a and the structures before the front-side interconnect structure 306a described in the foregoing description, and therefore are not repeated here for clarity.

[0200] Please refer to Figure 4C . Figure 4B The structure is "flipped" over and bonded to the carrier wafer 205 via the bonding dielectric structure 204. In some embodiments, the carrier wafer 205 may include, for example, bulk silicon, a thin film, a pre-patterned element, a doped or undoped substance, or an active layer of a semiconductor dielectric body substrate. The carrier wafer 205 may have a circular top view shape or a rectangular top view shape. The diameter of the carrier wafer 205 may be 3 inches, 12 inches, or larger. In some embodiments, the bonding dielectric structure 204 may be made of a dielectric material, such as SiCN.

[0201] Please refer to Figure 4DThe substrate 200 is removed by multiple processing operations, such as chemical mechanical polishing from the back side of the substrate 200, nitric acid (acetic acid, HNA) and / or tetramethylammonium hydroxide (tetramethylammoniumhydroxide, TMAH) etching, which stops at the etch stop layer 201. After the removal process, as shown in FIG. Figure 4D As shown, the etch stop layer 201 is exposed.

[0202] Please refer to Figure 4E The etch stop layer 201 is removed by multiple processing operations, such as chemical mechanical polishing, nitric acid (HNA) and / or tetramethylammonium hydroxide (TMAH) etching from the back side of the substrate 200, which stops at the cap layer 202. After the removal process, as shown in FIG. Figure 4E As shown, the capping layer 202 is exposed. The etch stop layer 201 may be removed using any acceptable etching process that etches the material of the etch stop layer 201 faster than the material of the capping layer 202. The etching may be isotropic. For example, when the etch stop layer 201 is formed of silicon germanium and the capping layer 202 is formed of silicon, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0203] Please refer to Figure 4F . A hard mask layer 206 is formed on the cap layer 202. Next, a patterned photoresist layer 207 is formed on the hard mask layer 206. In some embodiments, the hard mask layer 206 may be a silicon nitride layer, a silicon nitride oxide layer, etc., for example but not limited to, using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. The hard mask layer 206 is used as a hard mask in a subsequent photolithography process. The photoresist layer 207 is formed on the hard mask layer 206 and then patterned to form openings in the photoresist layer 207, thereby exposing areas of the hard mask layer 206. In some embodiments, the photoresist layer 207 is patterned by exposure, baking, development and / or other photolithography processes to provide openings to expose the hard mask layer 206.

[0204] Please refer to Figure 4G. Using the hard mask layer 206 and the patterned photoresist layer 207 as masking elements, an etching process is performed to etch the exposed cover layer 202 and form a through-silicon via opening 229a through the cover layer 202. In some embodiments, the through-silicon via opening 229a can be formed by performing any suitable etching process including, for example, plasma etching, chemical wet etching, laser drilling and / or other processes. In some embodiments, the etching process includes a deep reactive ion etching process to etch the cover layer 202 from the back side surface 202b of the cover layer 202. After the etching process, a pre-cleaning process may be performed, and in some embodiments, hydrofluoric acid (HF) or other suitable solutions are used to clean the through-silicon via opening 229a.

[0205] Please refer to Figure 4H After etching the capping layer 202, the photoresist layer 207 is removed. Next, a cleaning step may be optionally performed to remove the native oxide of the capping layer 202. The cleaning may be performed using dilute hydrofluoric acid (HF), for example but not limited to.

[0206] Please refer to Fig. 4I and Figure 4J . Dielectric through silicon via 219a (see Figure 4J ) is formed in the through silicon via opening 229a and contacts the metal element (not shown) in the front-end process structure 203 to connect the signal, power or ground, so that the through silicon via 219a can serve as a heat dissipation path for the metal layer connecting the front side of the wafer and the back side of the wafer. Specifically, the dielectric material 249 (see FIG. 24) is deposited on the cover layer 202 from the back side 202b of the cover layer 202. Fig. 4I ) and fill the through silicon via opening 229a. In some embodiments, the dielectric material 249 may have a thermal conductivity of about 150 W / m / K (kth) or more. In some embodiments, the dielectric material 249 may include a metal oxide (e.g., beryllium oxide (BeO)) or a metal nitride (e.g., aluminum nitride (AlN)). In some embodiments, the dielectric material 249 may include chemical vapor deposition (CVD) diamond. In some embodiments, the dielectric material 249 is formed by a deposition process including a chemical vapor deposition (CVD) process, such as high-density plasma chemical vapor deposition, flow chemical vapor deposition, etc., or a combination thereof. Other suitable materials can be formed by any acceptable process to form a dielectric through silicon via 219a. In some embodiments, the through silicon via opening 229a does not contain metal inside. Next, excess portions of the dielectric material 249 are removed, which may be performed by etching, chemical mechanical polishing, etc., so that the backside surface 219s of the dielectric-filled opening is substantially planar with the backside surface 202b of the capping layer 202. The remaining portion of the dielectric material 249 in the through-silicon via opening 229a forms a dielectric through-silicon via 219a.

[0207] Please refer to Figure 4K and Figure 4M You can use Figure 1A The back-end process scheme shown in FIG. 1 forms a back-side interconnect structure 206 b including multiple interconnect levels on the back side of the cover layer 202 (see FIG. 2 ). Figure 4M ). In some embodiments, the backside interconnect structure 206b electrically connects the buried power line (not shown) and the front-end process structure 203 to form a functional circuit within the semiconductor structure. The backside interconnect structure 206b may include at least one metallization layer 208b. In some embodiments, the number of metallization layers may vary depending on the design specifications of the semiconductor structure. The metallization layer 208b includes a dielectric layer 210b. The metallization layer 208b includes at least one interconnect structure 214b extending laterally or laterally in the dielectric layer 210b. The interconnect structure 214b may be formed using any suitable method, such as a single damascene process, a dual damascene process, etc. In some embodiments, the dielectric layer 210b may include a low-k dielectric material having a k value, for example, less than about 4.0 or even 2.0, and is configured between such conductive features. In some embodiments, the dielectric layer may be made of, for example, phosphate glass, borophosphate glass, fluorosilicate glass, SiO x C y , spin-coated glass, spin-coated polymer, silicon oxide, silicon oxynitride, a combination thereof, or the like, and may be formed by any suitable method, such as spin coating, chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like. The interconnect structure 214b may include copper, aluminum, tungsten, a combination thereof, or the like, or a similar conductive material. In some embodiments, the interconnect structure 214b may further include one or more barrier / adhesion layers (not shown) to protect the dielectric layer 210b from metal diffusion (e.g., copper diffusion) and metal poisoning. One or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like. Forming the back-side interconnect structure 206b may be referred to as a back-end-of-line (BEOL) process. The hard mask layer 206 may then be removed from the back-end process structure 213, for example by etching. Next, as Fig.4O As shown, the carrier wafer 205 and the bonding dielectric 204 may be removed from the back end processing structure 213 .

[0208] See also Figure 4L , Figure 4N , Figure 4P ,as well as Figures 4Q to 4T . Figure 4M , Figure 4N ,and Figure 4P Some embodiments of the present disclosure corresponding to Figure 4K , Figure 4M ,and Fig.4O Schematic cross-sectional view of a semiconductor structure. Figure 4Q-4T Some embodiments of the present disclosure correspond to Fig.4O Schematic cross-sectional view of different semiconductor structures. However, Figure 4L , Figure 4N , Figure 4P ,as well as Figures 4Q to 4T Draws the FIG. 4A to FIG. 4L , Figure 4N ,and Figure 4P In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself define the relationship between various embodiments and / or configurations.

[0209] like Figure 4L , Figure 4N ,and Figure 4P As shown, Figure 4K , Figure 4M ,and Fig.4O Implementation Methods and FIG. 4A to FIG. 4L , Figure 4N ,and Figure 4PThe difference between the embodiments is that an additional dielectric layer 214c is formed on the back side 202b of the cover layer 202 and is at the same level as the innermost interconnect structure 214b in the metallization layer 208b of the backside interconnect structure 206b. The through silicon via 219a is in contact with the dielectric layer 214c, so the through silicon via 219a and the dielectric layer 214c can serve as a heat dissipation path for connecting the metal layer on the front side of the wafer and the back side of the wafer. In some embodiments, the dielectric layer 214c may be made of a dielectric material having a thermal conductivity greater than about 150W / m / K (kth). In some embodiments, the dielectric layer 214c may include a metal oxide (e.g., beryllium oxide (BeO)) or a metal nitride (e.g., aluminum nitride (AlN)). In some embodiments, the dielectric layer 214c may include chemical vapor deposition (CVD) diamond. In some embodiments, the dielectric layer 214c is formed by a deposition process including a chemical vapor deposition process, such as high-density plasma chemical vapor deposition, flowable chemical vapor deposition, the like, or a combination thereof. Other suitable materials formed by any acceptable process may be used to form the dielectric layer 214c. In some embodiments, the dielectric layer 214c is metal-free. For example, the dielectric layer 214c may be made of a metal oxide (e.g., beryllium oxide (BeO)), a metal nitride (e.g., aluminum nitride (AlN)), a combination thereof, or other suitable materials. In some embodiments, the dielectric layer 214c may be made of the same material as the through-silicon via 219a. In some embodiments, the dielectric layer 214c may be made of a material different from the through-silicon via 219a. In some embodiments, the materials selected for the dielectric layer 214c and the through-silicon via 219a may be compatible with the manufacturing process of the semiconductor structure. Certain materials may be easier to deposit or etch than other materials, affecting the complexity and cost of manufacturing. In some embodiments, the dielectric layer 214c may be alternatively referred to as a dielectric lateral structure.

[0210] like Figure 4Q and Figure 4R As shown, Figure 4Q and Figure 4R The implementation method and FIG. 4A to FIG. 4L , Figure 4N ,and Figure 4P The difference between the embodiments in FIG. 1 and FIG. 2 is that the through silicon via 219b (see Figure 4Q ) / Through silicon via 219c (see Figure 4Q ) further extends to the back-end process structure 213, so that the through silicon via 219b / through silicon via 219c can serve as a heat dissipation path for the metal layer connecting the front side of the wafer and the back side of the wafer. In addition, Figure 4Q The semiconductor ratio shown in FIG. 4A to FIG. 4L , Figure 4N ,and Figure 4P The semiconductor shown in FIG. 1 has an additional dielectric layer 214d formed on the back side 202b of the cover layer 202 and at the same level as the innermost interconnect structure 214b in the metallization layer 208b of the backside interconnect structure 206b. The materials and manufacturing methods for forming the through silicon via 219b / through silicon via 219c and the dielectric layer 214d are substantially the same as those for forming the through silicon via 219a and the dielectric layer 214c, and are not repeated here for clarity.

[0211] like Figure 4S and Figure 4T As shown, Figure 4Q Implementation method and diagram in FIG. 4A to FIG. 4L , Figure 4N ,and Figure 4P The difference between the embodiments in FIG. 1 and FIG. 2 is that the embedded power line 218d (see Figure 4S ) / Built-in power cord 218e (see Figure 4T ) is formed between the front-end process structure 203 and the back-side interconnect structure 206b. A through silicon via 219d (see Figure 4S ) / Through Silicon Via 219e (see Figure 4T ) further extends to the buried power line 218d / buried power line 218e, so the through silicon via 219d / through silicon via 219e can serve as a heat dissipation path connecting the metal layer on the front side of the wafer and the back side of the wafer. In some embodiments, the buried power line 218d / buried power line 218e can be formed by forming a groove that passes through the shallow trench isolation area of ​​the front-end process structure 203 and enters the cover layer 202. Next, a conductive material is filled into the groove to form the buried power line 218d / buried power line 218e. The conductive material may include a metal, such as tungsten (W), steel (Ru), aluminum (Al), copper (Cu) or other suitable conductive materials. In some embodiments, the conductive material may be deposited by chemical vapor deposition, physical vapor deposition, sputtering deposition or other techniques suitable for depositing conductive materials. In addition, Figure 4T The semiconductor ratio shown in FIG. 4A to FIG. 4L , Figure 4N and Figure 4P The semiconductor shown in FIG. 1 has an additional dielectric layer 214e formed on the back side 202b of the cover layer 202 and at the same level as the innermost interconnect structure 214b in the metallization layer 208b of the backside interconnect structure 206b. The materials and manufacturing methods for forming the through silicon via 219d / through silicon via 219e and the dielectric layer 214e are substantially the same as the materials and manufacturing methods for forming the through silicon via 219a and the dielectric layer 214c, and are not repeated here for clarity.

[0212] Please refer to FIG. 5A to FIG. 5I , Figure 5K ,and Figure 5M . FIG. 5A to FIG. 5I , Figure 5K ,and Figure 5M Depicted is a cross-sectional view of an intermediate stage in the formation of a semiconductor structure according to some embodiments.

[0213] Please refer to Figure 5A and Figure 5B . A front-end process structure 103 (see Figure 5B ) is formed on the substrate 104. Subsequently, a back-end process structure 102 (see Figure 5B ). In some embodiments, the substrate 104 may be made of a semiconductor material, such as silicon. The materials and manufacturing methods for forming the back-end process structure 102 and the front-end process structure 103 are substantially the same as the materials and manufacturing methods for forming the interconnect structure 306a and the structures formed before the front-side interconnect structure 306a, and are not repeated here for clarity.

[0214] Please refer to Figure 5C . Figure 5C The structure is "flipped" over and bonded to a carrier wafer 100 via an adhesive 101 having a connection pad 105 therein, and the connection pad 105 can be connected to the back-end process structure 102. In some embodiments, the carrier wafer 100 may include, for example, a whole piece of silicon, a thin film, a pre-patterned device, doped or undoped, or an active layer of a semiconductor dielectric substrate. The carrier wafer 100 may have a circular top-view shape or a rectangular top-view shape. The diameter of the carrier wafer 100 may be 3 inches, 12 inches, or larger. In some embodiments, the adhesive 101 may include glue, a laminate coating, a foil, or other type of adhesive, for example.

[0215] Please refer to Figure 5D . A hard mask layer 106 is formed on the substrate 104. Subsequently, a patterned photoresist layer 107 is formed on the hard mask layer 106. In some embodiments, the hard mask layer 106 may be a silicon nitride layer, a silicon oxynitride layer, etc., for example but not limited to using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. The hard mask layer 106 is used as a hard film in a subsequent photolithography process. The photoresist layer 107 is formed on the hard mask layer 106 and then patterned to form an opening in the photoresist layer 107, so that an area of ​​the hard mask layer 106 is exposed. In some embodiments, the photoresist layer 107 is patterned by exposure, baking, development and / or other photolithography processes to provide an opening that exposes the hard mask layer 106.

[0216] refer to Figure 5E. Using the hard mask layer 106 and the patterned photoresist layer 107 as masking elements, an etching process is performed to etch the exposed substrate 104 and the front-end process structure 103 until the metal elements (not shown) in the back-end process structure 102 are exposed and a through-silicon via opening 129a is formed through the substrate 104. In some embodiments, the through-silicon via opening 129a can be formed by performing any suitable etching process, including, for example, plasma etching, chemical wet etching, laser drilling and / or other processes. In some embodiments, the etching process includes a deep reactive ion etching process to etch the substrate 104 from the backside surface 104b of the substrate 104. After the etching process, a pre-cleaning process can be performed to clean the through-silicon via opening 129a using hydrofluoric acid (HF) or other suitable solutions.

[0217] refer to Fig. 5F After etching the substrate 104, the photoresist layer 107 is removed. Next, a cleaning step may be optionally performed to remove the native oxide of the substrate 104. For example and without limitation, dilute hydrofluoric acid (HF) may be used for cleaning.

[0218] refer to Figure 5G and Figure 5H A dielectric TSV 119a is formed in the TSV opening 129a (see Figure 5H ) and contacts with metal elements (not shown) in the back-end process structure 102 to connect signals, power or ground, so the through silicon via 119a can serve as a heat dissipation path for connecting the metal layer of the front side of the wafer and the back side of the wafer. Specifically, a dielectric material 149 (see FIG. 14) is deposited on the substrate 104 from above the back side 104b of the substrate 104. Figure 5G) and fill the through-silicon via opening 129a. In some embodiments, the thermal conductivity of the dielectric material 149 may be greater than about 150 W / m / K (kth). In some embodiments, the dielectric material 149 may include a metal oxide (e.g., beryllium oxide (BeO)) or a metal nitride (e.g., aluminum nitride (AlN)). In some embodiments, the dielectric material 149 may include chemical vapor deposition (CVD) diamond. In some embodiments, the dielectric material 149 is formed by a deposition process including a chemical vapor deposition (CVD) process, such as high-density plasma chemical vapor deposition, flow chemical vapor deposition, the like, or a combination thereof. Other suitable materials formed by any acceptable process may be used to form the dielectric through-silicon via 119a. In some embodiments, there is no metal inside the through-silicon via opening 129a. Next, the excess portion of the dielectric material 149 is removed by etching, chemical mechanical polishing or the like, so that the back surface 119s of the opening filled with the dielectric material is substantially coplanar with the back surface 104b of the substrate 104. The remaining portion of the dielectric material 149 in the through-silicon via opening 129a forms a dielectric through-silicon via 119a.

[0219] refer to Fig.5I . A redistribution structure 109 may be formed on the back surface 104b of the substrate 104. In some embodiments, the redistribution structure 109 may include a dielectric layer 109a and a patterned conductive layer 109b embedded in the dielectric layer 109a. In some embodiments, one or more layers of dielectric material are collectively represented as dielectric layer 109a, and the patterned conductive layer 109b may be redistribution lines including through holes, pads and / or traces to form electrical connections. These redistribution lines are formed layer by layer and stacked on alternating layers of dielectric material. In some embodiments, the dielectric layer 109a may be formed of a polymer material such as polybenzoxazole, polyimide, benzocyclobutane, etc., or other suitable materials that can be patterned by photolithography. For example, the dielectric layer 109a may be formed using any suitable method, such as a spin coating process, a deposition process and / or the like. In some embodiments, patterned conductive layer 109b may be formed of a conductive material, such as copper, titanium, tungsten, aluminum, a metal alloy, a combination of these, or the like. The number of dielectric layers 109a and patterned conductive layers 109b may be selected as desired and is not limited by the present disclosure. In some embodiments, redistribution structure 109 may be interchangeably referred to as a redistribution layer.

[0220] refer to Figure 5K. A heat sink 110 is formed on the redistribution structure 109 to reduce the junction temperature of the redistribution structure 109. Therefore, the heat sink 110 may help to dissipate the heat generated from the redistribution structure 109. The heat sink 110 may be formed of copper, silver, gold, tungsten, aluminum, a combination thereof, or a similar conductive material. The heat sink 110 may be formed using various deposition methods, such as physical vapor deposition such as sputtering, evaporation, plasma enhanced chemical vapor deposition, and electroplating. Next, the carrier wafer 100, the bonding material 101, and the connection pads 105 may be removed from the back-end process structure 102, such as Figure 5M shown.

[0221] refer to Figure 5K , Figure 5L , Figure 5N ,and FIG. 5O to FIG. 5T . Figure 5J , Figure 5L ,and Figure 5N Draws the Fig.5I , Figure 5K and Figure 5M Schematic cross-sectional views of respective semiconductor structures according to some embodiments of the present disclosure. FIG. 5O to FIG. 5T Some embodiments of the present disclosure are shown. Fig.5I Schematic cross-sectional views of different corresponding semiconductor structures. Figure 5J , Figure 5L , Figure 5N ,and Fig.5O , Figure 5T The semiconductor structure embodiment shown has FIG. 5A to FIG. 5I , Figure 5K ,and Figure 5M In addition, the disclosure may repeatedly quote numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself define the relationship between various embodiments and / or configurations.

[0222] like Figure 5J , Figure 5L ,and Figure 5N As shown, Figure 4K , Figure 4M and Fig.4O The implementation method and FIG. 4A to FIG. 4L , Figure 4N and Figure 4PThe difference between the embodiments of is that an additional dielectric layer 114c is formed on the back side 104b of the substrate 104 and at the same layer height as the patterned conductor layer of the redistribution structure 109. The through silicon via 119a is in contact with the dielectric layer 114c, so that the through silicon via 119a and the dielectric layer 114c can serve as a heat conduction path connecting the metal layer on the front side of the wafer and the back side of the wafer. In some embodiments, the dielectric layer 114c may be made of a dielectric material having a thermal conductivity greater than about 150 W / m / K (kth). In some embodiments, the dielectric layer 114c may include a metal oxide (e.g., beryllium oxide (BeO)) or a metal nitride (e.g., aluminum nitride (AlN)). In some embodiments, the dielectric layer 114c may include chemical vapor deposition (CVD) diamond. In some embodiments, the dielectric layer 114c is formed by a deposition process including a chemical vapor deposition process, such as high-density plasma chemical vapor deposition, flow chemical vapor deposition, the like, or a combination thereof. Other suitable materials formed by any acceptable process may be used to form the dielectric layer 114c. In some embodiments, the dielectric layer 114c does not contain metal. For example, the dielectric layer 114c may be made of a metal oxide (e.g., beryllium oxide (BeO)), a metal nitride (e.g., aluminum nitride (AlN)), a combination thereof, or other suitable materials. In some embodiments, the dielectric layer 114c may be made of the same material as the through-silicon via 119a. In some embodiments, the dielectric layer 114c may be made of a material different from the through-silicon via 119a. In some embodiments, the dielectric layer 114c may be interchangeably referred to as a lateral dielectric structure.

[0223] like Fig.5O and Figure 5P As shown, Fig.5O and Figure 5P The implementation method and Figure 4L , Figure 4N and Figure 4P The difference between the embodiments is that the through silicon via 119b (see Fig.4O ) / Through silicon via 119c (see Figure 4P ) further extends to the outermost surface 102f of the back-end process structure 102, so that the through silicon via 119b / through silicon via 119c can serve as a heat conduction path connecting the metal layer on the front side of the wafer and the back side of the wafer. In addition, Figure 4P The semiconductor device shown in FIG. 1 has an additional dielectric layer 114d formed on the back side 104b of the substrate 104 and at the same level as the patterned conductor layer of the redistribution structure 109. FIG. 5A to FIG. 5I , Figure 5K ,and Figure 5MThe materials and manufacturing methods for forming the through silicon via 119b / through silicon via 119c and the dielectric layer 114d are substantially the same as those for forming the through silicon via 119a and the dielectric layer 114c, as described above, and thus will not be repeated here for clarity.

[0224] like Figure 5Q and Figure 5R As shown, Figure 5Q and Figure 5R The implementation method and FIG. 4A to FIG. 4L , Figure 4N and Figure 4P The difference between the embodiments of the present invention is that the substrate 154, the front-end process structure 153 and the back-end process structure 152 can be sequentially formed on the back-end process structure 102 before forming the through silicon via 119a, so that the through silicon via 119a can serve as a heat conduction path connecting the back side of the wafer and the metal layer of the front side of the wafer further including the substrate 154, the front-end process structure 153 and the back-end process structure 152. The materials and manufacturing methods for forming the substrate 154, the back-end process structure 152 and the front-end process structure 153 are substantially the same as the materials and manufacturing methods for forming the substrate 104, the back-end process structure 102 and the front-end process structure 103, as described above, and therefore will not be repeated here to maintain clarity.

[0225] like Figure 5S and Figure 5T As shown, Figure 5S and Figure 5T The implementation method and FIG. 4A to FIG. 4L , Figure 4N and Figure 4P The difference between the embodiments is that the substrate 164, the front-end process structure 163 and the back-end process structure 162 can be sequentially formed on the back-end process structure 102 before forming the through silicon via 119d, and the through silicon via 119d / through silicon via 119e further extends to the outermost surface 162f of the back-end process structure 162, so that the through silicon via 119d can serve as a heat conduction path connecting the back side of the wafer and the metal layer of the front side of the wafer further including the substrate 164, the front-end process structure 163 and the back-end process structure 162. The materials and manufacturing methods for forming the through silicon via 119d / through silicon via 119e, the substrate 164, the back-end process structure 162 and the front-end process structure 163 are substantially the same as the materials and manufacturing methods for forming the through silicon via 119a, the substrate 104, the back-end process structure 102 and the front-end process structure 103, as described above, and therefore will not be repeated here to maintain clarity.

[0226] Therefore, based on the above discussion, it can be seen that the present disclosure provides advantages. However, it is understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed here, and not all embodiments require specific advantages. Various embodiments of the present disclosure provide a through-silicon via, which is made of a dielectric material having a higher thermal conductivity than a substrate to improve the heat dissipation of an integrated circuit structure. The through-silicon via can be metal-free. The dielectric through-silicon via can be used as a heat sink for the integrated circuit structure to discharge the heat generated by the semiconductor element from the local hot spot of the circuit to the outside of the integrated circuit structure. In some embodiments, the thermal conductivity of the dielectric through-silicon via may be greater than about 150W / m / K (kth). Because the dielectric through-silicon via can be metal-free, parasitic capacitance will not be generated in the integrated circuit structure around the dielectric through-silicon via, which in turn prevents additional leakage paths in the integrated circuit structure, thereby improving the performance of the integrated circuit structure.

[0227] In some embodiments, the method includes forming a semiconductor element on a front side of a substrate, the semiconductor element including a channel region, a gate structure on the channel region, and a source / drain region on the channel region opposite the gate structure; forming a first source / drain contact on a first region of the source / drain region; forming a front side interconnect structure on the first source / drain contact; forming a first dielectric through-silicon via through the substrate from a cross-sectional view, and overlapping the first source / drain contact from a top view; forming a back side interconnect structure on a back side of the substrate, wherein the first dielectric through-silicon via has a back side surface in contact with the back side interconnect structure. In some embodiments, the first dielectric through-silicon via is made of a material having a thermal conductivity greater than about 150 W / m / K. In some embodiments, the first dielectric through-silicon via is made of a metal oxide. In some embodiments, the first dielectric through-silicon via is made of a metal nitride. In some embodiments, the first dielectric through-silicon via has a front side surface in contact with the first source / drain contact. In some embodiments, the method further includes forming a second source / drain contact on a second region in the source / drain region; forming a second dielectric through-silicon via through the substrate, the second dielectric through-silicon via having a front side surface in contact with the second source / drain contact. In some embodiments, the backside interconnect structure includes a dielectric layer and a metal line extending laterally in the dielectric layer, and the back side surface of the first dielectric through-silicon via is in contact with the metal line. In some embodiments, the backside interconnect structure includes a dielectric layer, a metal line extending laterally in the dielectric layer, and a dielectric lateral structure in the dielectric layer, and the back side surface of the first dielectric through-silicon via is in contact with the dielectric lateral structure. In some embodiments, the dielectric lateral structure is made of the same material as the first dielectric through-silicon via. In some embodiments, the method further includes forming an embedded power line on the front side of the substrate and forming a metal through-silicon via through the substrate, wherein the front side surface of the metal through-silicon via contacts the embedded power line and the back side surface contacts the metal line of the back-side interconnect structure.

[0228] In some embodiments, the method includes forming an interconnect structure on the front side of the substrate; etching the substrate from the back side of the substrate to form a through-silicon via opening until the interconnect structure is exposed; forming a metal-free through-silicon via in the through-silicon via opening; and forming a redistribution layer on the back side of the substrate. In some embodiments, the metal-free through-silicon via is made of beryllium oxide, aluminum nitride, chemical vapor deposited diamond, or a combination thereof. In some embodiments, the redistribution layer includes a dielectric layer and a metal line extending laterally in the dielectric layer, and the metal-free through-silicon via is in contact with the metal line. In some embodiments, the redistribution layer includes a dielectric layer and a dielectric lateral structure in the dielectric layer, and the metal-free through-silicon via is in contact with the dielectric lateral structure. In some embodiments, the dielectric lateral structure is made of the same material as the metal-free through-silicon via.

[0229] In some embodiments, the semiconductor structure includes a first semiconductor substrate, a first interconnect structure, a second interconnect structure, a metal-containing through-silicon via, and a dielectric through-silicon via. The first interconnect structure is located on the front side of the first semiconductor substrate. The second interconnect structure is located on the back side of the first semiconductor substrate. The metal-containing through-silicon via passes through the first semiconductor substrate and is electrically connected to the first and second interconnect structures. The dielectric through-silicon via passes through the first semiconductor substrate. The dielectric through-silicon via is made of a material having a thermal conductivity greater than about 150 W / m / K. In some embodiments, the semiconductor structure also includes a semiconductor element and a source / drain contact. The semiconductor element is located on the front side of the first semiconductor substrate. The semiconductor element includes a channel region, a gate structure passing through the channel region, and a source / drain region on the channel region and on the opposite side of the gate structure. The source / drain contact is located on one of the source / drain regions. The front side surface of the dielectric through-silicon via is in contact with the source / drain contact. In some embodiments, the second interconnect structure includes a dielectric layer and a metal line extending laterally in the dielectric layer, and the back surface of the dielectric through silicon via contacts the metal line. In some embodiments, the semiconductor structure further includes a second semiconductor substrate, which is located on the back surface of the second interconnect structure, and the dielectric through silicon via further passes downward through the second interconnect structure and the second semiconductor substrate. In some embodiments, the semiconductor structure further includes a redistribution layer located on the back surface of the second semiconductor substrate, wherein the dielectric through silicon via further extends to the redistribution layer.

[0230] In some embodiments, a semiconductor structure includes a substrate, a semiconductor element, a first source / drain contact, a front-side interconnect structure, a first dielectric through-silicon via, and a back-side interconnect structure. The semiconductor element is located on the front side of the substrate, wherein the semiconductor element includes a channel region, a gate structure spanning the channel region, and a plurality of source / drain regions located on the channel region and on opposite sides of the gate structure. The first source / drain contact is located on a first of the plurality of source / drain regions. The front-side interconnect structure is located on the first source / drain contact. The first dielectric through-silicon via passes through the substrate from a cross-sectional view, wherein from a top view, the first dielectric through-silicon via overlaps with the first source / drain contact. The back-side interconnect structure is located on the back side of the substrate, wherein a back-side surface of the first dielectric through-silicon via contacts the back-side interconnect structure. In some embodiments, a front-side surface of the first dielectric through-silicon via contacts the first source / drain contact. In some embodiments, the semiconductor junction further includes a second source / drain contact and a second dielectric through-silicon via. The second source / drain contact is located on a second one of the plurality of source / drain regions. A second dielectric TSV passes through the substrate, wherein a front surface of the second dielectric TSV contacts the second source / drain contact.

[0231] In some embodiments, a semiconductor structure includes a substrate, an interconnect structure, a dielectric through-silicon via, and a redistribution layer. The interconnect structure is located on the front side of the substrate. The dielectric through-silicon via extends from the back side of the substrate to the interconnect structure. The redistribution layer is located on the back side of the substrate. In some embodiments, the redistribution layer includes a dielectric layer and a lateral dielectric structure in the dielectric layer, and the dielectric through-silicon via contacts the lateral dielectric structure.

[0232] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: a first semiconductor substrate; a first interconnect structure located on a front side of the first semiconductor substrate; a second interconnect structure located on a back side of the first semiconductor substrate; a metal-containing through-silicon via that passes through the first semiconductor substrate and is electrically coupled to the first interconnect structure and the second interconnect structure; and A dielectric through silicon via passes through the first semiconductor substrate.

2. The semiconductor structure according to claim 1, wherein: Further including: a semiconductor device located on the front side of the first semiconductor substrate, the semiconductor device comprising a channel region, a gate structure spanning the channel region, and a plurality of source / drain regions located on the channel region and on opposite sides of the gate structure; as well as A source / drain contact is located on one of the plurality of source / drain regions, wherein a front side surface of the dielectric TSV contacts the source / drain contact.

3. The semiconductor structure according to claim 1, wherein: The second interconnection structure includes a dielectric layer and a metal line extending laterally in the dielectric layer, and a back side surface of the dielectric through silicon via contacts the metal line.

4. The semiconductor structure according to claim 1, wherein: Further including: A second semiconductor substrate is located on a backside surface of the second interconnect structure, and the dielectric through silicon via further passes downward through the second interconnect structure and the second semiconductor substrate.

5. The semiconductor structure according to claim 4, characterized in that Further including: A redistribution layer is located on a backside surface of the second semiconductor substrate, wherein the dielectric through silicon via further extends to the redistribution layer.

6. A semiconductor structure, characterized in that include: a substrate; a semiconductor device disposed on a front side of the substrate, wherein the semiconductor device comprises a channel region, a gate structure spanning the channel region, and a plurality of source / drain regions disposed on the channel region and on opposite sides of the gate structure; a first source / drain contact located on a first one of the plurality of source / drain regions; a front-side interconnect structure located on the first source / drain contact; a first dielectric TSV extending through the substrate in a cross-sectional view, wherein the first dielectric TSV overlaps the first source / drain contact in a top view; and A backside interconnection structure is located on a backside of the substrate, wherein a backside surface of the first dielectric through silicon via contacts the backside interconnection structure.

7. The semiconductor structure according to claim 6, wherein: A front surface of the first dielectric through silicon via contacts the first source / drain contact.

8. The semiconductor structure according to claim 7, wherein: Further including: a second source / drain contact located on a second one of the plurality of source / drain regions; as well as A second dielectric TSV passes through the substrate, wherein a front surface of the second dielectric TSV contacts the second source / drain contact.

9. A semiconductor structure, characterized in that: include: a substrate; an interconnect structure located on a front side of the substrate; a dielectric through-silicon via extending from a back side of the substrate to the interconnect structure; and A redistribution layer is located on the back side of the substrate.

10. The semiconductor structure according to claim 9, wherein: The redistribution layer includes a dielectric layer and a lateral dielectric structure in the dielectric layer, and the dielectric through silicon via contacts the lateral dielectric structure.

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