Sensor pixel unit, signal processing circuit and electronic equipment

Abstract

The embodiment of the utility model discloses a sensor pixel unit, a signal processing circuit and electronic equipment, and the sensor pixel unit comprises a signal collection module, a transmission tube, a signal processing module and a signal output module. The signal acquisition module is connected with the signal processing module through the transmission tube; the source end of the transmission tube is connected with the signal acquisition module, the drain end of the transmission tube is connected with the signal processing module, and the gate end of the transmission tube receives an external transmission signal; one end of the signal processing module is connected with the transmission tube, and the other end of the signal processing module is connected with the signal output module; and the signal output module is connected with the signal processing module.

Description

Technical Field

[0001] The present disclosure relates to the technical field of image sensors, and in particular to a sensor pixel unit, a signal processing circuit and an electronic device. Background Art

[0002] Image sensors have been widely used in digital cameras, mobile phones, medical treatment, automobiles, drones, machine recognition and other fields. In particular, the rapid development of complementary metal oxide semiconductor (CMOS) image sensor technology has led to higher requirements for the output image quality of image sensors. Dynamic range is an important evaluation index of photoelectric image sensors. Utility Model Content

[0003] According to one aspect of the embodiments of the present disclosure, there is provided a sensor pixel unit, comprising: the signal acquisition module is connected to the signal processing module via the transmission tube;

[0004] The source terminal of the transmission tube is connected to the signal acquisition module, the drain terminal is connected to the signal processing module, and the gate terminal receives an external transmission signal;

[0005] One end of the signal processing module is connected to the transmission tube, and the other end is connected to the signal output module;

[0006] The signal output module is connected to the signal processing module.

[0007] Optionally, the signal acquisition module includes: a photodiode, a first reset tube and a first switch transistor;

[0008] The anode terminal of the photodiode is grounded, and the cathode terminal is connected to the source terminal of the first reset tube and the source terminal of the transmission tube;

[0009] The drain terminal of the first reset tube receives a power supply signal, the gate terminal receives a first feedback signal, and the source terminal is connected to the cathode terminal of the photodiode and the source terminal of the transmission tube;

[0010] The source terminal of the first switch transistor is connected to the gate terminal of the first reset transistor, the drain terminal is connected to the first feedback signal, and the gate terminal receives the first switch signal.

[0011] Optionally, the signal processing module includes: a floating diffusion region, a second reset transistor and a second switch transistor;

[0012] One end of the floating diffusion region is grounded, and the other end is connected to the source end of the second reset tube as a connection end of the signal processing module; the connection end is connected to the drain end of the transmission tube and the signal output module;

[0013] The source terminal of the second reset transistor is connected to the floating diffusion area, the drain terminal receives a power signal, and the gate terminal is connected to the drain terminal of the second switch transistor;

[0014] The drain terminal of the second switch transistor is connected to the gate terminal of the second reset transistor, the gate terminal receives the second switch signal, and the source terminal receives the second feedback signal.

[0015] Optionally, the signal output module includes: a source follower transistor and a selection transistor;

[0016] The gate terminal of the source follower transistor is connected to the signal processing module, the source terminal is connected to the selection transistor, and the drain terminal receives a power supply signal;

[0017] The drain terminal of the selection transistor is connected to the source terminal of the source follower transistor, the source terminal is connected to the signal processing module, and the gate terminal receives an external control signal.

[0018] According to another aspect of the embodiments of the present disclosure, a signal processing circuit is provided, characterized in that it comprises: a pixel array composed of m rows and n columns of sensor pixel units as described in any one of the above embodiments, and n column processors; wherein each of the column processors corresponds to m sensor pixel units in a column; m and n are integers greater than or equal to 1 respectively;

[0019] Each column of the sensor pixel units in the pixel array is connected to one of the column processors.

[0020] Optionally, the column processor comprises: a comparator, a first feedback circuit and a second feedback circuit;

[0021] The negative input terminal of the comparator is connected to the output terminal of the sensor pixel unit, the positive input terminal receives a reference signal, the output terminal serves as the output terminal of the signal processing circuit, and the output terminal is connected to the input terminal of the first feedback circuit and the input terminal of the second feedback circuit;

[0022] The input end of the first feedback circuit is connected to the output end of the comparator, and the output end is connected to the sensor pixel unit;

[0023] The input end of the second feedback circuit is connected to the output end of the comparator, and the output end is connected to the sensor pixel unit.

[0024] Optionally, the first feedback circuit includes a first AND logic circuit and a first OR logic circuit;

[0025] One input end of the first AND logic circuit is used as the input end of the first feedback circuit and is connected to the output end of the comparator; the other input end receives the first AND signal; and the output end is connected to one input end of the first OR logic circuit;

[0026] One input terminal of the first OR logic circuit is connected to the output terminal of the first AND logic circuit, the other input terminal receives a first OR signal; and the output terminal is connected to the sensor pixel unit.

[0027] Optionally, the second feedback circuit includes a second AND logic circuit and a second OR logic circuit;

[0028] One input end of the second AND logic circuit is used as the input end of the second feedback circuit and is connected to the output end of the comparator; the other input end receives the second AND signal; and the output end is connected to one input end of the second OR logic circuit;

[0029] One input terminal of the second OR logic circuit is connected to the output terminal of the second AND logic circuit, the other input terminal receives a second OR signal; and the output terminal is connected to the sensor pixel unit.

[0030] Optionally, it further comprises: n digital readout circuits, each of the digital readout circuits corresponding to one of the column processors;

[0031] An input terminal of the digital readout circuit is connected to an output terminal of a corresponding comparator in the column processor.

[0032] Optionally, it further comprises: n digital encoding circuits, each of the digital encoding circuits corresponding to one of the digital readout circuits;

[0033] The input end of the digital encoding circuit is connected to the corresponding output end of the digital readout circuit.

[0034] Optionally, it further comprises: n double sampling readout circuits, each of the double sampling readout circuits corresponding to m sensor pixel units in a column;

[0035] An input terminal of the dual sampling readout circuit is connected to an output terminal of the sensor pixel unit.

[0036] According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, comprising: a processor, and a memory communicatively connected to the processor, and further comprising the sensor pixel unit described in any one of the above embodiments or the signal processing circuit described in any one of the above embodiments;

[0037] The memory stores computer-executable instructions;

[0038] The processor executes computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing circuit.

[0039] Optionally, the electronic device is included in any one of the following: a pulse camera, a high-speed camera, an audio / video player, a navigation device, a fixed-position terminal, an entertainment unit, a smart phone, a communication device, a device in a motor vehicle, a camera, a sports or wearable camera, a detection device, a flight device, a medical device, a security device.

[0040] A sensor pixel unit, a signal processing circuit and an electronic device provided based on the above-mentioned embodiments of the present disclosure include: a signal acquisition module, a transmission tube, a signal processing module and a signal output module; the signal acquisition module is connected to the signal processing module through the transmission tube; the source end of the transmission tube is connected to the signal acquisition module, the drain end is connected to the signal processing module, and the gate end receives an external transmission signal; one end of the signal processing module is connected to the transmission tube, and the other end is connected to the signal output module; the signal output module is connected to the signal processing module; this embodiment determines whether to read out the charge stored in the signal acquisition module by the signal change amount caused by the charge change in the signal processing module, and improves the efficiency of analog signal processing by synchronously outputting the signal amount accumulated in the signal acquisition module.

[0041] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0043] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0044] Figure 1 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0045] Figure 2 is a schematic diagram of the circuit structure of a signal acquisition module in a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0046] Figure 3 is a schematic diagram of the circuit structure of a signal processing module in a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0047] Figure 4 is a schematic diagram of an optional circuit structure of a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0048] Figure 5 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0049] Figure 6a is a circuit structure diagram of a column processor in a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0050] Figure 6b is a circuit structure diagram of a column processor in a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0051] Figure 7a is a circuit structure diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0052] Figure 7b It is a schematic diagram of the connection between a column processor and other circuits in a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0053] Figure 8a is a schematic diagram of the timing of multiple signals received in a pixel unit in a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0054] Figure 8b is an imaging partition control timing diagram of m rows of pixel units in a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0055] Figure 8c is a schematic diagram of digital and analog outputs in a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0056] Fig. 9 A signal processing circuit according to an exemplary embodiment of the present disclosure outputs raw data in the same format for any pixel;

[0057] Fig.10 A block diagram of an electronic device according to an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0058] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0059] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0060] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0061] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0062] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0063] In addition, the term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this disclosure generally indicates that the previous and next associated objects are in an "or" relationship. The data referred to in this disclosure may include unstructured data such as text, images, and videos, and may also be structured data.

[0064] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0065] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0066] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0067] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0068] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0069] In the process of realizing the present disclosure, the inventors found that in order to improve the dynamic range of the photoelectric image sensor, there are currently three main methods: the first method is multi-frame exposure synthesis, which continuously outputs images from underexposure to overexposure in time, and then fuses them to obtain images with high dynamic range. When the image sensor or the photographed object moves, since the images from underexposure to overexposure are obtained at different time points, the synthesized image may have motion artifacts, blur, etc. The second method is to set two large and small photodiodes (PD) in the pixel, and read out the accumulated charge in the two large and small photodiodes each time, so as to take into account the imaging of low dark areas and high bright areas. However, since the large and small photodiodes are integrated in the pixel respectively, the pixel area and the complexity of the process preparation are increased, and the signals in the large and small photodiodes need to be read out simultaneously each time, which increases the time for each signal readout and limits the imaging speed. The third method is LOFIC (Lateral Over Flow Integration Capacitor) technology. When the PD reaches half of the saturation well capacity during exposure, the relevant circuit action will be triggered and the charge on the PD will be transferred to a separately added storage capacitor, increasing the pixel's ability to store charge, thereby achieving high dynamic range imaging. The main challenge of this technology is to efficiently manufacture large-capacity storage capacitors, so a new pixel preparation process needs to be developed.

[0070] The above three technical approaches to achieve high dynamic range mainly include the synthesis of images exposed at different times, and adding PD or capacitance in the pixel to adjust the sensitivity of the pixel, which puts forward high requirements on the algorithm and pixel preparation process.

[0071] Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an exemplary embodiment of the present disclosure. Figure 1 As shown, it includes: a signal acquisition module 11, a transmission tube 12, a signal processing module 13 and a signal output module 14.

[0072] The signal acquisition module 11 is connected to the signal processing module 13 via the transmission tube 12, and is used for receiving the optical signal to generate photoelectric charge, and performing a reset operation according to the control of the first feedback signal.

[0073] Optionally, the main components in the signal acquisition module 11 can be photoelectric conversion components (for example, photodiodes, etc.), which can receive light signals during the exposure time and convert the light signals into photoelectric charges; and before transmitting the photoelectric charges to the signal processing module, the photoelectric charges are stored, and the light intensity is characterized by the number of photoelectric charges generated. Before the transmission tube 12 is turned on, the photoelectric charges are stored in the signal acquisition module. Among them, the first feedback signal can be determined based on the signal output by the signal output module 14 after processing, that is, the reset automatic control of the signal acquisition module 11 is formed. When the first feedback signal is at a high level, the signal acquisition module 11 is controlled to perform a reset operation; when the first feedback signal is at a low level, the signal acquisition module 11 does not perform a reset operation.

[0074] The source terminal of the transmission tube 12 is connected to the signal acquisition module 11, the drain terminal is connected to the signal processing module 13, and the gate terminal receives the external transmission signal Φ TX , used to transmit the photoelectric charge generated by the signal acquisition module 11 to the signal processing module 13 according to the control of the external transmission signal.

[0075] In this embodiment, the transmission tube 12 is configured to transmit the external transmission signal Φ TX The control is turned on or off. When turned on, the signal acquisition module 11 and the signal processing module 13 are connected, so that the photoelectric charge collected by the signal acquisition module 11 after the last reset before the turn-on moment is transmitted to the signal processing module 13, and the exposure time of the signal acquisition module 11 is determined according to the light intensity. The stronger the light intensity, the more frequent the reset of the signal acquisition module 11 controlled by the first feedback signal determined according to the signal output by the sensor pixel unit, and the shorter the time between the last reset and the moment when the transmission tube 12 is turned on. Therefore, this embodiment realizes high dynamic range imaging by controlling the exposure time.

[0076] One end of the signal processing module 13 is connected to the transmission tube 12, and the other end is connected to the signal output module 14, and is used to generate a first output signal when the transmission tube 12 is not conducting, and to generate a second output signal based on the photoelectric charge accumulated during the exposure time transmitted by the signal acquisition module 11 when the transmission tube is conducting.

[0077] Optionally, the signal processing module 13 also generates photoelectric charges under illumination to realize the light detection function, and resets when receiving a reset signal input from the outside. For example, the first output signal output during reset is high level, and when reset is not performed, the first output signal output is low level. When the transmission tube 12 is turned on, the accumulated photoelectric charges in the signal acquisition module 11 are read. Optionally, the reset signal can be a second feedback signal obtained by processing the signal output by the signal output module 14. When the second feedback signal is high level, the signal processing module 13 performs reset; when the second feedback signal is low level, the signal processing module 13 sequentially reads the photoelectric charges generated by each of the k signal acquisition modules 11.

[0078] The signal output module 14 is connected to the signal processing module 13 and is used for outputting the first output signal or the second output signal according to the control of the external control signal.

[0079] Optionally, the first output signal and the second output signal may include at least one of the following signals: a pulse signal, a potential signal, a numerical value with a finite bit, and the like.

[0080] The above embodiment of the present disclosure provides a sensor pixel unit, comprising: a signal acquisition module, a transmission tube, a signal processing module and a signal output module; the signal acquisition module is used to receive a light signal to generate a photoelectric charge, and perform a reset operation according to the control of a first feedback signal; the transmission tube is used to transmit the photoelectric charge generated by the signal acquisition module to the signal processing module according to the control of an external transmission signal; the signal processing module is used to generate a first output signal when the transmission tube is not turned on; when the transmission tube is turned on, the accumulated photoelectric charge transmitted by the signal acquisition module within the exposure time generates a second output signal; the signal output module is used to output the first output signal or the second output signal according to the control of an external control signal; this embodiment realizes the adjustable exposure time of the sensor pixel unit through the first feedback signal and the second feedback signal, determines whether to read out the charge stored in the signal acquisition module according to the signal change caused by the charge change in the signal processing module, and improves the efficiency of analog signal processing by synchronously outputting the signal amount accumulated on the signal acquisition module.

[0081] Figure 2 FIG. 1 is a schematic diagram of a circuit structure of a signal acquisition module in a sensor pixel unit provided by an exemplary embodiment of the present disclosure. Figure 2 As shown, the signal acquisition module 11 includes: a photodiode 111 and a first reset tube 112;

[0082] The anode terminal of the photodiode 111 is grounded GND, and the cathode terminal is connected to the source terminal of the first reset tube 112 and the source terminal of the transmission tube 12 .

[0083] Optionally, the photodiode 111 may also be other photoelectric conversion components that can realize photoelectric conversion, so as to realize the conversion of light signals into photoelectric charges. Under illumination conditions, the photodiode 111 generates photoelectric charges, and before the transmission tube is turned on, the photoelectric charges are confined in the depletion region of the photodiode 111 by the energy potential well, and the photoelectric charges in the photodiode 111 gradually accumulate.

[0084] The drain terminal of the first reset transistor 112 receives the power signal VDD, and the gate terminal receives the first feedback signal The source terminal is connected to the cathode terminal of the photodiode 111 and the source terminal of the transmission tube 12; and is used to generate a signal according to the first feedback signal. The photodiode 111 is reset under the control of .

[0085] Optionally, when the photodiode 111 is reset, the cathode terminal is connected to the power signal VDD, and the voltage on the photodiode 111 is charged to a high level.

[0086] In this embodiment, the photodiode 111 is connected to the power signal VDD through the first reset tube 112. When the first reset tube 112 is disconnected, the photodiode 111 accumulates light signals and converts them into photoelectric charges. When the first reset tube 112 is closed, the photodiode 111 is connected to the power signal VDD to perform a reset.

[0087] like Figure 2 As shown, the signal acquisition module 11 further includes: a first switch transistor 113;

[0088] The source terminal of the first switch transistor 113 is connected to the gate terminal of the first reset transistor 112, and the drain terminal is connected to the first feedback signal The gate terminal receives the first switch signal The first switch transistor 113 is used to generate a first switch signal When the first switch transistor 113 is turned on or off, the first feedback signal Transmitted to the first reset tube 112.

[0089] In this embodiment, the first feedback signal is realized by adding the first switch transistor 113. The control signal transmitted to the first reset tube 112 is When the first feedback signal is high, the first switch transistor 113 is turned on. The first feedback signal is transmitted to the gate terminal of the first reset tube 112 to realize the conduction control of the first reset tube 112. When the first feedback signal is high, the first reset tube 112 is turned on and the photodiode 111 is reset. When the first reset transistor 112 is at a low level, the first reset transistor 112 is disconnected. In this embodiment, the first feedback signal that allows external transmission is realized by adding the first switch transistor 113. The first reset tube 112 is controlled to realize the control of resetting the photodiode 111 .

[0090] Figure 3 FIG. 1 is a schematic diagram of a circuit structure of a signal processing module in a sensor pixel unit provided by an exemplary embodiment of the present disclosure. Figure 3 As shown, the signal processing module 13 includes: a floating diffusion area 131 , a second reset transistor 132 and a second switch transistor 133 .

[0091] One end of the floating diffusion area 131 is grounded GND, and the other end is connected to the source end of the second reset tube 132 as a connection end of the signal processing module; it is connected to the drain end of the transmission tube 12 and the signal output module 13 through the connection end.

[0092] Optionally, the floating diffusion area 131 performs reset when the second reset tube 132 is turned on; when the second reset tube 132 is turned off and the transmission tube 12 is turned on, the floating diffusion area 131 receives the photoelectric charge generated by the photodiode 111 of the signal acquisition module 11 to generate a second output signal.

[0093] In this embodiment, the floating diffusion area 131 is a common structure in the pixel unit of the 5T structure. The light detection function is realized by the floating diffusion area 131, and when the photodiode 111 and the signal processing module 13 are connected, the photoelectric charge generated in the photodiode 111 is read to the floating diffusion area 131.

[0094] The source terminal of the second reset transistor 132 is connected to the floating diffusion area 131, the drain terminal receives the power supply signal VDD, the gate terminal is connected to the drain terminal of the second switch transistor 133, and receives the second feedback signal through the second switch transistor 133. According to the second feedback signal The floating diffusion area 131 is controlled to be reset.

[0095] Optionally, when the second reset tube 132 is turned on, the floating diffusion area 131 is turned on by the power signal VDD, so as to reset the floating diffusion area 131 and charge the voltage on the floating diffusion area 131 to a high level. Under illumination conditions, photoelectric charges are generated in both the photodiode 111 and the floating diffusion area 131, wherein the voltage on the floating diffusion area 131 gradually decreases under the action of the photoelectric charges. Normally, the floating diffusion area 131 is reset before generating photoelectric charges.

[0096] The second switch transistor 133 is used to adjust the second switch signal When the second switch transistor 133 is turned on or off, the second feedback signal Transmitted to the second reset tube.

[0097] The source terminal of the second switch transistor 133 receives the second feedback signal The gate terminal receives the second switch signal The drain terminal is connected to the gate terminal of the second reset transistor 132 .

[0098] This embodiment uses the voltage signal variation caused by the photoelectric charge in the floating diffusion area 131 to determine whether to reset the photoelectric charge stored in the photodiode, and synchronously outputs the signal accumulated on the photodiode 111 through the floating diffusion area 131 .

[0099] The floating diffusion area 131 performs reset when the second reset tube 132 is turned on; when the second reset tube 132 is turned off and the transmission tube 12 is turned on, the floating diffusion area 131 receives and stores the photoelectric charge generated by the photodiode 111 in the signal acquisition module 11; and according to the external control signal Φ TX The control output generates a second output signal based on the stored photoelectric charge.

[0100] Optionally, the floating diffusion area 131 outputs a first output signal when the transmission tube 12 is not turned on, and the first output signal is output as a high-level first output signal when the floating diffusion area 131 is reset, and outputs a low-level first output signal when it is not reset. When the transmission tube 12 is turned on, the floating diffusion area 131 receives the photoelectric charge collected by the photodiode 111, so the second output signal output at this time corresponds to the amount of charge accumulated by the photodiode during the exposure time.

[0101] In this embodiment, whether the second reset transistor 132 is turned on depends on whether the level received by the gate terminal is a high level. When the second feedback signal is high, the second reset tube 132 is turned on. Whether the second switch signal can be transmitted to the gate terminal of the second reset transistor 132 depends on whether the second switch transistor 133 is turned on. When the second switching transistor 133 is high, the second switching transistor 133 is turned on. In this embodiment, the second feedback signal that allows external input is realized by providing the second switching transistor 133. The second reset tube 132 is controlled to realize the second switch signal and the second feedback signal The floating diffusion area 131 is reset or charged. The transmission tube 12 receives the external transmission signal Φ at every preset time interval (the preset time interval can be set according to the specific application scenario). TX , and according to the external transmission signal Φ TX The exposure of the photodiode 111 is ended by the control of the first feedback signal. At this time, the time from the last reset (high level output) of the photodiode 111 before the end of the exposure to the end of the exposure is the exposure time of the photodiode 111. That is, in this embodiment, the first feedback signal and the second feedback signal The reset of the photodiode 111 and the floating diffusion area 131 is controlled to achieve adaptive adjustment of the exposure time of the photodiode 111, thereby expanding the ability of the pixel unit to express light intensity, thereby achieving high dynamic range imaging. This embodiment can adaptively increase the exposure time of the sensor pixel unit in the dark light area by adaptively adjusting the exposure time of the photodiode 111, thereby improving the signal-to-noise ratio and the quality of the collected image.

[0102] Figure 4 FIG. 1 is a schematic diagram of an optional circuit structure of a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 4 As shown, in this embodiment, the signal output module 14 includes: a source follower transistor 141 and a selection transistor 142;

[0103] The source follower transistor 141 has a gate terminal connected to the signal processing module 13, a source terminal connected to the selection transistor 142, and a drain terminal receiving a power signal VDD; and is used to detect and follow the charge change of the floating diffusion area 131 to determine the first output signal or the second output signal.

[0104] The drain terminal of the selection transistor 142 is connected to the source terminal of the source follower transistor 141, the source terminal is connected to the signal processing module 13, and the gate terminal receives the external control signal Φ sel , and according to the external control signal Φ sel The control determines whether to output the first output signal or the second output signal.

[0105] In this embodiment, the gate terminal of the source follower transistor 141 is connected to the signal processing module 13, and follows the potential change of the floating diffusion area 131 to obtain a potential signal. This process does not affect the photoelectric conversion of the photodiode 111. Under the premise that the transmission tube 12 is disconnected, the source follower transistor 141 reads the potential change of the floating diffusion area 131, and the photodiode 111 continues to perform photoelectric conversion to collect charges. The selection transistor 142 is based on the external control signal Φ sel The control selects whether to output the target signal, and the external control signal Φ selIt can be an external clock signal or an external pulse signal, etc.; the external control signal Φ sel The timing is set according to the specific scenario. Optionally, an external control signal Φ can be sent regularly based on an external clock circuit. sel The pixel selection transistor is controlled to output a first output signal or a second output signal.

[0106] Figure 5 FIG. 1 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure. Figure 5 As shown, the signal processing circuit provided by this embodiment includes: a pixel array 510 composed of m rows*n columns of sensor pixel units 511, and n column processors 520; wherein, each column of m sensor pixel units 511 in the pixel array 510 corresponds to a column processor; each column processor 520 corresponds to each sensor pixel unit 511 in the m sensor pixel units 511 in a column; m and n are integers greater than or equal to 1 respectively.

[0107] Optionally, the signal acquisition module 11 in each sensor pixel unit 511 corresponds to a column processor 520 .

[0108] The m sensor pixel units 511 in each column of the pixel array 510 are connected to a corresponding column processor 520 .

[0109] The pixel array 510 is used to quantize the pixel signals of each row of sensor pixel units 511 row by row according to the control of an external control signal, output n first output signals or second output signals and send them to n column processors respectively.

[0110] In this embodiment, the signal acquisition module 11 in each sensor pixel unit 511 outputs signals in sequence.

[0111] The column processor 520 is used to determine the encoding signal corresponding to the sensor pixel unit 510 according to the received first output signal and second output signal, and obtain the first feedback signal and the second feedback signal based on the encoding signal, and control the operation of the sensor pixel unit through the first feedback signal and the second feedback signal.

[0112] In this embodiment, by setting a first switch transistor and a second switch transistor inside the sensor pixel unit (hereinafter referred to as the pixel unit) 511, the pixel unit can realize reset control according to the first feedback signal and the second feedback signal fed back by the column processor 520, thereby realizing adjustable exposure time, and adaptively increasing the exposure time of the sensor pixel unit in the dark light area, improving the signal-to-noise ratio, and improving the quality of the collected image. In addition, the output of the pixel unit is controlled by the first feedback signal and the second feedback signal fed back by the column processor 520, reducing the external signal input and improving the reset efficiency of the pixel unit; and reducing the number of components in the pixel unit, reducing the size of the pixel unit, and improving the resolution of the image collected by the sensor using the pixel unit.

[0113] Figure 6a FIG. 1 is a circuit structure diagram of a column processor in a signal processing circuit provided by an exemplary embodiment of the present disclosure. Figure 6a As shown, the column processor 520 includes: a comparator 521 , a first feedback circuit 522 , and a second feedback circuit 523 .

[0114] The negative input terminal of the comparator 521 is connected to the output terminal of the sensor pixel unit 511 for receiving the first output signal or the second output signal, the positive input terminal receives the reference signal Vth, and the output terminal outputs the coded signal as the output terminal of the signal processing circuit; and the output terminal is respectively connected to the input terminals of the first feedback circuit 522 and the second feedback circuit 523.

[0115] The input end of the first feedback circuit 522 is connected to the output end of the comparator 521, and the output end is connected to the sensor pixel unit 511, outputting a first feedback signal to the sensor pixel unit 511.

[0116] The input end of the second feedback circuit 523 is connected to the output end of the comparator 521, and the output end is connected to the sensor pixel unit 511, outputting the second feedback signal to the sensor pixel unit 511.

[0117] In this embodiment, the logic circuit determines the first feedback signal corresponding to the output based on the coded signal output by the comparator. and the second feedback signal The exposure time in the sensor pixel unit is controlled by the column processor 520 .

[0118] Figure 6b FIG. 1 is a circuit structure diagram of a column processor in a signal processing circuit provided by another exemplary embodiment of the present disclosure. Figure 6b As shown, in this embodiment, the first feedback circuit 522 includes a first AND logic circuit 5221 and a first OR logic circuit 5222;

[0119] One input terminal of the first AND logic circuit 5221 is used as the input terminal of the first feedback circuit 522 and is connected to the output terminal of the comparator 521; the other input terminal receives the first AND signal Φ and1 ; The output end is connected to an input end of the first OR logic circuit 5222.

[0120] One input terminal of the first OR logic circuit 5222 is connected to the output terminal of the first AND logic circuit 5221, and the other input terminal receives the first OR signal Φ OR1 The output end is connected to the sensor pixel unit 511, and outputs a first feedback signal to the sensor pixel unit 511

[0121] Optionally, the first AND logic circuit 5221 can implement AND logic processing on the output signal. Based on the processing logic of the AND logic, it can be known that only when both inputs are at a high level, a high level is output, otherwise both output a low level, that is, only when the comparison result output by the comparator is equal to the first AND signal Φ and1 When both are high level, the first AND logic circuit 5221 outputs a high level. and1 The output of the first AND logic circuit 5221 can be adjusted to achieve the first feedback signal based on the signal output by the pixel unit. The first OR logic circuit 5222 can implement OR logic processing on the input signal. Based on the OR logic processing logic, it can be known that when there is a high level in the two input signals, a high level is output, and only when both input signals are low levels, a low level is output. OR1 The first feedback signal that can directly control the output When the photodiode needs to be reset, the second or signal Φ OR1 Assign a high level signal to output a high level first feedback signal

[0122] Similar to the structure of the first feedback circuit, the second feedback circuit 523 includes a second AND logic circuit 5231 and a second OR logic circuit 5232;

[0123] One input terminal of the second AND logic circuit 5231 is used as the input terminal of the second feedback circuit 523 and is connected to the output terminal of the comparator 521; the other input terminal receives the second AND signal Φ and2 ; The output end is connected to an input end of the second OR logic circuit 5232.

[0124] One input terminal of the second OR logic circuit 5232 is connected to the output terminal of the second AND logic circuit 5231, and the other input terminal receives the second OR signal ΦOR2 The output end is connected to the sensor pixel unit 511, and outputs a second feedback signal to the sensor pixel unit 511

[0125] Optionally, the second AND logic circuit 5231 can implement AND logic processing on the output signal. Based on the processing logic of the AND logic, it can be known that only when both inputs are at a high level, a high level is output, otherwise a low level is output. That is, only when the comparison result output by the comparator is equal to the second AND signal Φ and2 When both are high level, the second AND logic circuit 5231 outputs high level. and2 The output of the second AND logic circuit 5231 can be adjusted to achieve the second feedback signal based on the signal output by the pixel unit. The second OR logic circuit 5232 can implement OR logic processing on the input signal. Based on the OR logic processing logic, it can be known that when there is a high level in the two input signals, the output is a high level, and only when both input signals are low levels, the output is a low level. Therefore, through the second OR signal Φ OR2 The second feedback signal Φ can directly control the output rsty When the photodiode needs to be reset, the second or signal Φ OR2 By giving a high level signal, a high level second feedback signal can be output

[0126] Figure 7a FIG. 1 is a circuit structure diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure. Figure 7a As shown, the signal processing circuit provided in this embodiment may further include: n digital readout circuits 530 , each digital readout circuit 530 corresponding to a column processor 520 .

[0127] The input end of the digital readout circuit 530 is connected to the output end of the comparator in the corresponding column processor, and is used to read out the coded signal output by the comparator at every preset time interval to obtain a digital sequence.

[0128] Optionally, the digital sequence output by the digital readout circuit 530 is a sequence consisting of 0 and 1, wherein 1 and 0 represent digital output signals of the pixel unit exposure control stage, 1 represents a reset operation, and 0 represents no reset operation.

[0129] like Figure 7a In the embodiment shown, the signal processing circuit provided in this embodiment further includes: n double sampling readout circuits 540, each double sampling readout circuit 540 corresponding to m sensor pixel units 511 in a column;

[0130] The input end of the dual sampling readout circuit 540 is connected to the output end of the sensor pixel unit 511. When the sensor pixel unit 511 is in signal readout, the first output signal and the second output signal at adjacent moments are continuously read out, and the exposure charge amount is determined based on the first output signal and the second output signal and output.

[0131] Optionally, the exposure charge amount may be determined based on a difference between a first output signal output at a time point before the second output signal is output and the second output signal.

[0132] Alternatively, if Figure 7a The embodiment shown in the figure may also include providing an external transmission signal Φ for each row of pixel units. TX , the first switch signal Second switch signal and external control signal Φ SEL The row control unit 550, optionally, an external transmission signal Φ TX , the first switch signal Second switch signal and external control signal Φ SEL The row control unit 550 sends a first switch signal with a preset timing to each row of pixel units in turn through a preset logic. Second switch signal and external control signal Φ SEL The row control unit 550 sends an external control signal Φ to a row of pixel units at a first preset time interval. SEL The row control unit 550 sends an external transmission signal Φ to a row of pixel units at a second preset time interval. TX , controls the transmission tube in the pixel unit to conduct, thereby controlling the output timing of the second output signal. and the second switch signal To realize the exposure control of the photodiode and the floating diffusion area in the pixel unit, optionally, the first switch signal and the second switch signal The clock signals may be of the same period. In this embodiment, the exposure and reset control of the pixel units of the corresponding row are realized through the signal output by the row control unit 550 . Figure 7b It is a schematic diagram of the connection between a column processor and other circuits in a signal processing circuit provided by an exemplary embodiment of the present disclosure.

[0133] Figure 8a FIG. 1 is a schematic diagram of the timing of multiple signals received by a pixel unit in a signal processing circuit provided by an exemplary embodiment of the present disclosure. Figure 8aAs shown, the working time of the pixel unit is divided into two intervals, the first interval is the exposure control interval, and the second interval is the signal readout interval. The interval between the two intervals is determined by the external transmission signal Φ TX The input cycle is controlled. In the first interval, the exposure signal is controlled, and when the voltage on the floating diffusion area drops below the threshold voltage (i.e. Figure 8a If the voltage signal reaches the threshold voltage, the photodiode and the floating diffusion area in the pixel unit are reset. If the voltage signal does not reach the threshold voltage, no operation is performed on the photodiode and the floating diffusion area (for example, Figure 8a At the moment T2, although the first switch signal and the second switch signal is high level, but since the first feedback signal and the second feedback signal are low level, the photodiode and the floating diffusion area are not reset). In the second interval, the accumulated charge in the photodiode is read out by double sampling (determined based on the signal difference at time T5 and time T6), and after reading the charge, the photodiode and the floating diffusion area are reset (corresponding to time T6).

[0134] In the exposure control interval, the row control unit is responsible for applying Φ to each pixel unit. SEL , Φ FRx , Φ PRx , Φ TX The signals sent by the row control unit do not change with Vout and are output in sequence for each row. The column readout and control unit applies Φ SEL The voltage signal (Vout) read out when the signal is applied determines the Φ FRy , Φ PRy The digital output module is responsible for outputting the comparison result between the Vout signal and the threshold voltage signal.

[0135] In the signal readout interval, each control voltage signal (including: external transmission signal Φ TX , the first switch signal Second switch signal and external control signal Φ SEL ) are input according to the set timing and do not change with the output signal. The signal on the photodiode is output through the double sampling readout circuit 540.

[0136] Alternatively, in an alternative embodiment, the double sampling readout circuit 540 is controlled by an external clock signal Φ READ control, and the first AND signal Φ and1 , the first or signal Φ OR1 , the second and signal Φ and2 and the second or signal Φ OR2In conjunction with the photodiode, the signal is read out at a fixed frequency. Figure 8a As shown, the reset signal V in the floating diffusion area is read out during the T4 period. RST In the T5 period, the signal V after the accumulated photoelectric charge of the floating diffusion receiving photodiode is read out is reduced. sig Optionally, during the T4 period, the second or signal Φ OR2 Set to high level, the second signal Φ and2 can be high or low (at this time due to the second or signal Φ OR2 is high level, so that the second OR logic circuit 5232 must output a high level, and the first feedback signal is high level, realizing the reset of the floating diffusion area. Therefore, the second AND signal Φ and2 In any case), the first and signal Φ and1 and the first or signal Φ OR1 Set it to low level (make the first feedback signal low level, control the photodiode not to perform reset), wait for the floating diffusion area to reset, and then read out the signal on the floating diffusion area, that is, get the signal V RST During the T5 period, the second and2 and the second or signal Φ OR2 Set to low level, first with signal Φ and1 and the first or signal Φ OR1 Set to low level, that is, the photodiode and floating diffusion area are not reset at this time, and the external transmission signal Φ TX Set it to high level (to turn on the transmission tube), wait for the charge on the photodiode to be transferred to the floating diffusion area, and then read out the signal V sig In the T6 period, by converting the first or signal Φ OR1 and the second or signal Φ OR2 Set to high (at this time, no matter whether the second output signal is high or low, after being processed by the first OR logic circuit and the second OR logic circuit, the first feedback signal and the second feedback signal are both high level) to reset the photodiode and the floating diffusion area. Optionally, in the above example, the exposure charge amount determined by the double sampling readout circuit 540 can be determined based on the difference between the first output signal output during the T4 period and the second output signal output during the T5 period, that is, the exposure charge amount = V RST -V sig .

[0137] Figure 8b 1 is a timing diagram of imaging partition control of m rows of pixel units in a signal processing circuit provided by an exemplary embodiment of the present disclosure. Figure 8bAs shown, each pixel unit 511 includes two intervals of exposure control and signal readout during image acquisition, and an exposure control interval is included between each two signal readout intervals, wherein the exposure control interval is responsible for reading out the floating diffusion area signal and determining whether to reset the photodiode signal, and determines the exposure time on the photodiode when it comes to the signal readout stage. The row controller performs signal readout on each row of pixel units row by row, and usually after performing signal readout on a row of pixel units, the photodiode and the floating diffusion area are reset, and then the exposure control interval is performed.

[0138] in accordance with Figure 8b As shown, for a specific point X in the imaging array, the corresponding digital and analog outputs are as follows Figure 8c As shown, Figure 8c 1 is a schematic diagram of digital and analog outputs in a signal processing circuit provided by an exemplary embodiment of the present disclosure. Among them, 1 and 0 represent digital output signals in the exposure control stage, 1 represents a reset operation, 0 represents no reset operation, and N represents an analog output signal. The moment t0 represents the initial moment, when the transfer of the signal of the photodiode (PD) in the pixel unit and the reset action of the floating diffusion area (FD) are completed, so that the signals in the PD and FD are cleared. The reset time interval between adjacent samplings in the exposure control stage is Δt2. Assuming that the number of samplings in the exposure control stage is N rst , the time interval between the reset time closest to the signal readout in the exposure control stage is Δt1. In one frame, the longest exposure time is N rst *Δt2+Δt1, the shortest exposure time is Δt1. s1 , which has the longest exposure time, and the signal intensity represented is V s1 / (Δt1+Nrst*Δt2) (i.e., the light intensity is weaker), for V s4 , whose exposure time is the shortest, and the signal intensity represented is V s4 / (Δt1), the exposure time difference is (Δt1+N rst *Δt2) / Δt1 times. Therefore, compared with the traditional method of using the same exposure time for all pixel units in one frame, this embodiment improves the expressible light intensity house, for example, Figure 8c In the embodiment shown, the range of light intensity that can be expressed is increased by (Δt1+N rst *Δt2) / Δt1 times.

[0139] For a single pixel unit, the signal finally outputted in one frame includes a digital signal (e.g., a digital voltage signal) outputted by the digital readout circuit 530 and an analog signal (e.g., an analog voltage signal) outputted by the double sampling readout circuit 540. Optionally, assuming that the number of bits after quantization of the analog voltage signal is N anaThe digital readout circuit 530 converts the voltage signal output by the pixel unit into a digital signal through AD. The number of sampling times in the exposure control area (which can be set according to the application scenario and is a preset value) is N. rst , so the number of bits of the digital signal is N rst In some optional examples, within one frame time, the raw data output by a single pixel unit is as follows: Fig. 9 As shown, Fig. 9 This is a diagram showing the format of raw data outputted by any pixel in a signal processing circuit provided by an exemplary embodiment of the present disclosure. Assume that the last 1 in the digital signal is at the i-th position (0≤i≤N rst -1), the leftmost is the Nth rst -1 bit, the rightmost bit is 0, then the exposure time is Δt1+i×Δt2 (refer to Figure 8c , the interval between every two outputs in the digital signal is Δt2. Since the last 1 is at the i-th position, the interval between this 1 and the analog signal is Δt1, so the exposure time can be obtained). Based on the above exposure time calculation formula, it can be known that a corresponding digital encoding circuit can be added after the digital readout circuit to realize N rst The digital exposure control signal is compressed to log2(N rst ) bits, the compressed value represents the number of bits where the last 1 is located. Through the processing of the digital coding circuit, the output bandwidth of the digital signal is reduced. For example, a 1024-bit output signal is compressed to 10 bits, which greatly reduces the output bandwidth.

[0140] Based on the above theory, optionally, in some optional embodiments, the signal processing circuit may further include: n digital encoding circuits, each digital encoding circuit corresponding to a digital readout circuit;

[0141] The input end of the digital encoding circuit is connected to the output end of the corresponding digital readout circuit, and receives the digital sequence output by the digital readout circuit to perform signal compression processing to obtain a coded value.

[0142] The electronic device provided by the present disclosure may be incorporated into any of the following: pulse cameras, high-speed cameras, audio / video players, navigation devices, fixed-position terminals, entertainment units, smart phones, communication devices, devices in motor vehicles, cameras, sports or wearable cameras, detection equipment, flight equipment, medical equipment, security equipment, etc.

[0143] The electronic device provided by the present disclosure can be applied to any of the following: pulse cameras, high-speed cameras, audio / video players, navigation equipment, fixed-position terminals, entertainment units, smart phones, communication equipment, equipment in motor vehicles, cameras, sports or wearable cameras, detection equipment, flight equipment, medical equipment, security equipment, etc.

[0144] Below, reference Fig.10 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0145] Fig.10 A block diagram of an electronic device according to an embodiment of the present disclosure is illustrated.

[0146] like Fig.10 As shown, the electronic device includes one or more processors and memory.

[0147] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0148] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the sensor pixel unit and / or other desired functions of the various embodiments of the present disclosure described above.

[0149] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0150] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0151] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0152] Of course, to simplify, Fig.10 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0153] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0154] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limiting. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0155] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0156] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0157] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0158] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0159] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A sensor pixel unit, characterized in that: include: Signal acquisition module, transmission tube, signal processing module and signal output module; The signal acquisition module is connected to the signal processing module through the transmission tube; The source terminal of the transmission tube is connected to the signal acquisition module, the drain terminal is connected to the signal processing module, and the gate terminal receives an external transmission signal; One end of the signal processing module is connected to the transmission tube, and the other end is connected to the signal output module; The signal output module is connected to the signal processing module.

2. The pixel unit according to claim 1, characterized in that: The signal acquisition module includes: a photodiode, a first reset tube and a first switch transistor; The anode terminal of the photodiode is grounded, and the cathode terminal is connected to the source terminal of the first reset tube and the source terminal of the transmission tube; The drain terminal of the first reset tube receives a power supply signal, the gate terminal receives a first feedback signal, and the source terminal is connected to the cathode terminal of the photodiode and the source terminal of the transmission tube; The source terminal of the first switch transistor is connected to the gate terminal of the first reset transistor, the drain terminal is connected to the first feedback signal, and the gate terminal receives the first switch signal.

3. The pixel unit according to claim 2, characterized in that: The signal processing module includes: a floating diffusion region, a second reset transistor and a second switch transistor; One end of the floating diffusion region is grounded, and the other end is connected to the source end of the second reset tube as a connection end of the signal processing module; the connection end is connected to the drain end of the transmission tube and the signal output module; The source terminal of the second reset transistor is connected to the floating diffusion area, the drain terminal receives a power signal, and the gate terminal is connected to the drain terminal of the second switch transistor; The drain terminal of the second switch transistor is connected to the gate terminal of the second reset transistor, the gate terminal receives the second switch signal, and the source terminal receives the second feedback signal.

4. The pixel unit according to any one of claims 1 to 3, characterized in that: The signal output module includes: a source follower transistor and a selection transistor; The gate terminal of the source follower transistor is connected to the signal processing module, the source terminal is connected to the selection transistor, and the drain terminal receives a power supply signal; The drain terminal of the selection transistor is connected to the source terminal of the source follower transistor, the source terminal is connected to the signal processing module, and the gate terminal receives an external control signal.

5. A signal processing circuit, characterized in that: include: A pixel array consisting of m rows and n columns of sensor pixel units according to any one of claims 1 to 4, and n column processors; wherein each of the column processors corresponds to m sensor pixel units in a column; m and n are integers greater than or equal to 1 respectively; The m sensor pixel units in each column of the pixel array are connected to the corresponding column processor.

6. The signal processing circuit according to claim 5, characterized in that: The column processor includes: a comparator, a first feedback circuit and a second feedback circuit; The negative input terminal of the comparator is connected to the output terminal of the sensor pixel unit, the positive input terminal receives a reference signal, the output terminal serves as the output terminal of the signal processing circuit, and the output terminal is connected to the input terminal of the first feedback circuit and the input terminal of the second feedback circuit; The input end of the first feedback circuit is connected to the output end of the comparator, and the output end is connected to the sensor pixel unit; The input end of the second feedback circuit is connected to the output end of the comparator, and the output end is connected to the sensor pixel unit.

7. The signal processing circuit according to claim 6, characterized in that: The first feedback circuit includes a first AND logic circuit and a first OR logic circuit; One input end of the first AND logic circuit is used as the input end of the first feedback circuit and is connected to the output end of the comparator; the other input end receives the first AND signal; and the output end is connected to one input end of the first OR logic circuit; One input terminal of the first OR logic circuit is connected to the output terminal of the first AND logic circuit, the other input terminal receives a first OR signal; and the output terminal is connected to the sensor pixel unit.

8. The signal processing circuit according to claim 6 or 7, characterized in that: The second feedback circuit includes a second AND logic circuit and a second OR logic circuit; One input end of the second AND logic circuit is used as the input end of the second feedback circuit and is connected to the output end of the comparator; the other input end receives the second AND signal; and the output end is connected to one input end of the second OR logic circuit; One input terminal of the second OR logic circuit is connected to the output terminal of the second AND logic circuit, the other input terminal receives a second OR signal; and the output terminal is connected to the sensor pixel unit.

9. The signal processing circuit according to claim 6 or 7, characterized in that: Also includes: n digital readout circuits, each of the digital readout circuits corresponding to one of the column processors; An input terminal of the digital readout circuit is connected to an output terminal of a corresponding comparator in the column processor.

10. The signal processing circuit according to claim 9, characterized in that: Also includes: n digital encoding circuits, each of which corresponds to one digital readout circuit; The input end of the digital encoding circuit is connected to the corresponding output end of the digital readout circuit.

11. The signal processing circuit according to claim 6 or 7, characterized in that: Also includes: n double sampling readout circuits, each of the double sampling readout circuits corresponding to m sensor pixel units in a column; An input terminal of the dual sampling readout circuit is connected to an output terminal of the sensor pixel unit.

12. An electronic device, characterized in that: The invention comprises: a processor, and a memory connected to the processor for communication, and also comprises the sensor pixel unit described in any one of claims 1 to 4 or the signal processing circuit described in any one of claims 5 to 11.

13. The electronic device according to claim 12, characterized in that: The electronic device is included in any of the following: pulse camera, high-speed camera, audio / video player, navigation equipment, fixed position terminal, entertainment unit, smart phone, communication equipment, equipment in motor vehicle, camera, sports or wearable camera, detection equipment, flight equipment, medical equipment, security equipment.

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