CAN receiver circuit

Abstract

The utility model provides a CAN receiver circuit. The CAN receiver circuit comprises an input optimization circuit, a current conversion circuit and a current comparison circuit. The voltage difference value of the first output signal and the second output signal is limited to be within a set range through the input optimization circuit, so that the duty ratio offset caused by different response speeds of the CAN receiver to different CAN differential modes is improved.

Description

Technical Field

[0001] The present application relates to the field of bus technology, and in particular to a CAN receiver circuit. Background Art

[0002] There are many communication methods in various electronic systems at present, among which CAN communication is one of the most widely used communication methods.

[0003] In the CAN chip, the CAN receiver is used to determine whether the received signal is dominant or recessive. First, the CAN SBC receives the signal from CANH and CANL, then performs voltage division, current conversion, and comparison in the CAN receiver, and finally outputs the logic judgment result. The logic judgment result consists of a dominant signal (CANH-CANL is greater than the dominant threshold) and a recessive signal (CANH-CANL is less than the recessive threshold). The dominant signal and the recessive signal correspond to different CANH-CANL values, and CANH-CANL is recorded as the CAN differential mode.

[0004] Usually the range of CAN differential mode is [-3V, 8V], and the CAN receiver responds to different CAN differential modes at different speeds, resulting in a duty cycle offset. Among them, the reference current and input resistance jointly determine the thresholds of dominant and recessive. When the CAN differential mode is closer to the dominant or recessive threshold, the generated current is closer to the reference current, the smaller the current difference, the slower the establishment speed, and the farther the CAN differential mode is from the threshold, the faster the speed. In addition, when the CAN differential mode is less than 0V, the feedback loop in the circuit will be closed, and the closed state is a recessive state. When the input switches to the dominant state at the next moment, it needs to be established from the closed state, resulting in a slow establishment. Utility Model Content

[0005] The purpose of the embodiments of the present application is to provide a CAN receiver circuit, which is used to solve the problems of slow settling speed and duty cycle deviation when the input of the existing CAN receiver switches between a dominant state and a recessive state.

[0006] A CAN receiver circuit provided in an embodiment of the present application includes: an input optimization circuit, a current conversion circuit and a current comparison circuit;

[0007] The input optimization circuit is used to process a first input signal at a first input terminal and output a first output signal at a first output terminal; process a second input signal at a second input terminal and output a second output signal at a second output terminal; and control a voltage difference between the first output signal and the second output signal to be within a set range;

[0008] The current conversion circuit is used for converting the voltage difference between the first output signal and the second output signal into a current to be compared;

[0009] The current comparison circuit is used to compare the current to be compared with the reference current to obtain a comparison result.

[0010] In the above technical solution, the CAN receiver circuit includes an input optimization circuit, a current conversion circuit and a current comparison circuit. The input optimization circuit limits the voltage difference between the first output signal and the second output signal within a set range to improve the duty cycle deviation caused by the different response speeds of the CAN receiver to different CAN differential modes.

[0011] In some optional embodiments, the current comparison circuit is used to: output an explicit signal when the current to be compared is greater than a first threshold; output a recessive signal when the current to be compared is less than a second threshold; wherein the first threshold is greater than the second threshold, and the second threshold is greater than 0.

[0012] In the above technical solution, when the current to be compared is greater than the first threshold, the CAN differential mode is greater than the dominant threshold, that is, the voltage difference between the first input signal and the second input signal is greater than the dominant threshold, and the CAN receiver circuit outputs a dominant signal. When the current to be compared is less than the second threshold, the CAN differential mode is less than the recessive threshold, that is, the voltage difference between the first input signal and the second input signal is less than the recessive threshold, and the CAN receiver circuit outputs a recessive signal. For example, the range of the CAN differential mode is [-3V, 8V], the dominant threshold is 0.8V, and the recessive threshold is 0.6V.

[0013] In some optional implementations, the input optimization circuit includes: a comparator, a first NMOS transistor, a second PMOS transistor, and an inverter;

[0014] The positive input terminal of the comparator is connected to the first input terminal, the negative input terminal of the comparator is connected to the second input terminal, the output terminal of the comparator is connected to the gate of the first NMOS tube, and the output terminal of the comparator is connected to the gate of the second PMOS tube through an inverter;

[0015] The positive input terminal of the comparator is connected to the source of the first NMOS tube, and the negative input terminal of the comparator is connected to the drain of the first NMOS tube; the source of the first NMOS tube is connected to the source of the second PMOS tube, and the drain of the first NMOS tube is connected to the drain of the second PMOS tube;

[0016] The source of the first NMOS tube is connected to the first output terminal, and the drain of the first NMOS tube is connected to the second output terminal.

[0017] In the above technical solution, when the CAN differential mode is less than 0V, the voltage of the first input signal input to the positive input terminal of the comparator is less than the voltage of the second input signal input to the negative input terminal thereof, and the comparator outputs a low-level signal to the gate of the first NMOS tube, the first NMOS tube is turned on, the low-level signal is passed through the inverter to obtain a high-level signal, the high-level signal is transmitted to the gate of the second PMOS tube, the second PMOS tube is turned on, so that the first output signal and the second output signal are equal. Therefore, when the CAN differential mode is less than 0V, the two input terminal signals of the current conversion circuit are in an intermediate balanced state, and when the input is switched to a dominant state at the next moment, it only needs to be established from the intermediate balanced state, thereby improving the establishment speed.

[0018] In some optional implementations, the input optimization circuit further includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

[0019] The first input terminal is connected to the positive input terminal of the comparator through the first resistor, the positive input terminal of the comparator is connected to the source of the first NMOS tube through the second resistor, and the source of the first NMOS tube is connected to the power supply through the third resistor;

[0020] The second input terminal is connected to the negative input terminal of the comparator through the fourth resistor, the negative input terminal of the comparator is connected to the drain of the first NMOS tube through the fifth resistor, and the drain of the first NMOS tube is grounded through the sixth resistor.

[0021] In the above technical solution, CAN bus is widely used in vehicle-mounted applications. Considering the voltage resistance problem of vehicle-mounted applications, this embodiment places the positive and negative input terminals of the comparator behind resistor dividers, and uses the ratio of the voltage divider resistors to reduce the voltage to within the voltage resistance range of the MOS inside the comparator.

[0022] In some optional embodiments, the comparator includes a hysteresis comparator; a hysteresis threshold of the hysteresis comparator is greater than the implicit threshold and less than the explicit threshold.

[0023] In the above technical solution, the comparator of this embodiment adopts a hysteresis comparator, and the hysteresis threshold of the hysteresis comparator is set between the maximum recessive threshold and the minimum dominant threshold. When the CAN differential mode is near the recessive threshold, the first NMOS tube and the second PMOS tube are turned on until the CAN differential mode is greater than the hysteresis threshold, and the two input terminal signals of the current conversion circuit are out of balance, thereby increasing the voltage difference between the CAN differential mode and the recessive threshold to generate a larger current difference and improve the response speed. In addition, the use of a hysteresis comparator can also prevent the problem of jitter in the comparator output when the voltages of the first input signal and the second input signal are similar.

[0024] In some optional implementations, the input optimization circuit includes: a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

[0025] The first input terminal is connected to the second end of the first diode through the first resistor, the second end of the first diode is connected to the first end of the second diode, the first end of the second diode is connected to the first end of the third resistor through the second resistor, the first end of the third resistor is connected to the first output terminal, and the second end of the third resistor is connected to the power supply;

[0026] The second input terminal is connected to the first end of the first diode through the fourth resistor, the first end of the first diode is connected to the second end of the second diode, the second end of the second diode is connected to the first end of the sixth resistor through the fifth resistor, the first end of the sixth resistor is connected to the second output terminal, and the second end of the sixth resistor is grounded.

[0027] In the above technical solution, a voltage limiting method of opposing diodes is adopted in the input optimization circuit to limit the voltage difference between the first output signal and the second output signal of the input current conversion circuit to a smaller range.

[0028] In some optional implementations, the current conversion circuit includes: a seventh resistor, an eighth resistor, an operational amplifier, a feedback circuit, and a current mirror circuit;

[0029] The first output terminal is connected to the positive input terminal of the operational amplifier through the eighth resistor, and the second output terminal is connected to the negative input terminal of the operational amplifier through the seventh resistor; the positive input terminal of the operational amplifier is connected to the first terminal of the current mirror circuit, the negative input terminal of the operational amplifier is connected to the second terminal of the current mirror circuit, the output terminal of the operational amplifier is connected to the feedback circuit, and the third terminal of the current mirror circuit is connected to the current comparison circuit;

[0030] The current mirror circuit is used to output the current to be compared to the current comparison circuit; the feedback circuit is used to control the current mirror circuit to connect to the power supply when the voltage difference between the first output signal and the second output signal is greater than 0; and to control the current mirror circuit to disconnect from the power supply when the voltage difference between the first output signal and the second output signal is less than 0.

[0031] In the above technical solution, the voltage of the first output signal is converted into current through the eighth resistor, and the voltage of the second output signal is converted into current through the seventh resistor. Due to the virtual short characteristic of the operational amplifier, the currents at the positive and negative input terminals of the input operational amplifier are forced to be equal, and the current to be compared is output to the current comparison circuit for comparison through the current mirror circuit.

[0032] In some optional implementations, the current mirror circuit includes a third MOS transistor, a sixth MOS transistor, and a seventh MOS transistor;

[0033] The gate of the third MOS tube is connected to the gate of the seventh MOS tube, the gate of the third MOS tube is connected to the drain of the third MOS tube, the drain of the third MOS tube is connected to the positive input terminal of the operational amplifier; the source of the seventh MOS tube is connected to the source of the sixth MOS tube, the drain of the seventh MOS tube is connected to the drain of the sixth MOS tube, and the gate of the sixth MOS tube is connected to the negative input terminal of the operational amplifier.

[0034] In some optional implementations, the feedback circuit includes a fourth MOS transistor and a fifth MOS transistor;

[0035] The source of the fourth MOS tube is connected to the power supply, the source of the fifth MOS tube is connected to the power supply, the gate of the fourth MOS tube and the gate of the fifth MOS tube are connected to the output end of the operational amplifier; the drain of the fourth MOS tube is connected to the source of the third MOS tube, and the drain of the fifth MOS tube is connected to the source of the sixth MOS tube.

[0036] In the above technical solution, when the voltage difference between the first output signal and the second output signal is less than 0V, the fourth MOS tube and the fifth MOS tube are turned off, and the entire feedback loop is turned off. When the input is switched to the dominant state at the next moment, it is necessary to start from the closed state, resulting in a slow establishment. In some embodiments of the present application, when the CAN differential mode is less than 0V, the voltage difference between the first output signal and the second output signal is limited to 0V to increase the establishment speed.

[0037] In some optional implementations, the current comparison circuit includes a reference current source; the drain of the sixth MOS transistor is connected to the input end of the reference current source. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic diagram of a CAN receiver circuit provided in an embodiment of the present application;

[0040] Figure 2 A circuit diagram of a CAN receiver provided in the first embodiment of the present application;

[0041] Figure 3 A circuit diagram of a CAN receiver provided in accordance with the second embodiment of the present application;

[0042] Figure 4 A circuit diagram of a CAN receiver provided in the third embodiment of the present application;

[0043] Figure 5 This is a structural diagram of the current conversion circuit and the current comparison circuit provided in the embodiments of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0045] Please refer to Figure 1 , Figure 1 A schematic diagram of a CAN receiver circuit provided in an embodiment of the present application includes: an input optimization circuit, a current conversion circuit and a current comparison circuit;

[0046] Among them, the input optimization circuit is used to process the first input signal at the first input terminal and output the first output signal at the first output terminal; process the second input signal at the second input terminal and output the second output signal at the second output terminal; and control the voltage difference between the first output signal and the second output signal to be within a set range; the current conversion circuit is used to convert the voltage difference between the first output signal and the second output signal into a current to be compared; the current comparison circuit is used to compare the current to be compared with the reference current to obtain a comparison result.

[0047] In an embodiment of the present application, the CAN receiver circuit includes an input optimization circuit, a current conversion circuit, and a current comparison circuit. The input optimization circuit limits the voltage difference between the first output signal and the second output signal within a set range to improve the duty cycle offset caused by the different response speeds of the CAN receiver to different CAN differential modes.

[0048] In some optional embodiments, the current comparison circuit is used to: output an explicit signal when the current to be compared is greater than a first threshold; output a recessive signal when the current to be compared is less than a second threshold; wherein the first threshold is greater than the second threshold, and the second threshold is greater than 0.

[0049] In the embodiment of the present application, when the current to be compared is greater than the first threshold, the CAN differential mode is greater than the dominant threshold, that is, the voltage difference between the first input signal and the second input signal is greater than the dominant threshold, and the CAN receiver circuit outputs a dominant signal. When the current to be compared is less than the second threshold, the CAN differential mode is less than the recessive threshold, that is, the voltage difference between the first input signal and the second input signal is less than the recessive threshold, and the CAN receiver circuit outputs a recessive signal. For example, the range of the CAN differential mode is [-3V, 8V], the dominant threshold is 0.8V, and the recessive threshold is 0.6V.

[0050] In some optional implementations, the input optimization circuit includes: a comparator CMP, a first NMOS transistor M1, a second PMOS transistor M2, and an inverter INV;

[0051] The positive input terminal of the comparator CMP is connected to the first input terminal, the negative input terminal of the comparator CMP is connected to the second input terminal, the output terminal of the comparator CMP is connected to the gate of the first NMOS tube M1, and the output terminal of the comparator CMP is connected to the gate of the second PMOS tube M2 through the inverter INV;

[0052] The positive input terminal of the comparator CMP is connected to the source of the first NMOS tube M1, and the negative input terminal of the comparator CMP is connected to the drain of the first NMOS tube M1; the source of the first NMOS tube M1 is connected to the source of the second PMOS tube M2, and the drain of the first NMOS tube M1 is connected to the drain of the second PMOS tube M2;

[0053] The source of the first NMOS transistor M1 is connected to the first output terminal, and the drain of the first NMOS transistor M1 is connected to the second output terminal.

[0054] In the embodiment of the present application, when the CAN differential mode is less than 0V, the voltage of the first input signal input to the positive input terminal of the comparator CMP is less than the voltage of the second input signal input to the negative input terminal thereof, and the comparator CMP outputs a low-level signal to the gate of the first NMOS tube M1, the first NMOS tube M1 is turned on, the low-level signal passes through the inverter INV to obtain a high-level signal, the high-level signal is transmitted to the gate of the second PMOS tube M2, the second PMOS tube M2 is turned on, so that the first output signal and the second output signal are equal. Therefore, when the CAN differential mode is less than 0V, the two input terminal signals of the current conversion circuit are in an intermediate balanced state, and when the input is switched to a dominant state at the next moment, it only needs to be established from the intermediate balanced state, thereby improving the establishment speed.

[0055] Please refer to Figure 2 , Figure 2 A circuit structure diagram of a CAN receiver provided in the first embodiment of the present application; the input optimization circuit of the present embodiment further includes a second resistor R2, a third resistor R3, a fifth resistor R5 and a sixth resistor R6; wherein, one end of the second resistor R2 is connected to the positive input end of the comparator CMP, and the other end is connected to the node Vx; one end of the fifth resistor R5 is connected to the negative input end of the comparator CMP, and the other end is connected to the node Vy; the node Vx is connected to the power supply through the third resistor R3, and the node Vy is grounded through the sixth resistor R6; the second resistor R2 and the third resistor R3 form a voltage-dividing resistor structure, and the fifth resistor R5 and the sixth resistor R6 form a voltage-dividing resistor structure.

[0056] In this embodiment, in view of the situation that the feedback loop will be closed when the CAN differential mode is less than 0V, the input range is limited for optimization. When CANL>CANH, the first NMOS tube M1 and the second PMOS tube M2 are turned on, and the nodes Vx and Vy are short-circuited. The subsequent circuit is in the state of CANH=CANL, Vx=Vy, and when the input is switched to the dominant state, the circuit is established from the middle balanced state, thereby improving the establishment speed.

[0057] Please refer to Figure 3 , Figure 3 A circuit structure diagram of a CAN receiver provided in the second embodiment of the present application; the input optimization circuit of the present embodiment further includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0058] Among them, the first input end is connected to the positive input end of the comparator CMP through the first resistor R1, the positive input end of the comparator CMP is connected to the source of the first NMOS tube M1 through the second resistor R2, and the source of the first NMOS tube M1 is connected to the power supply through the third resistor R3; the second input end is connected to the negative input end of the comparator CMP through the fourth resistor R4, the negative input end of the comparator CMP is connected to the drain of the first NMOS tube M1 through the fifth resistor R5, and the drain of the first NMOS tube M1 is grounded through the sixth resistor R6.

[0059] In the embodiment of the present application, the CAN bus is widely used in vehicle-mounted applications. Taking into account the voltage resistance problem of vehicle-mounted applications, in this embodiment, the positive and negative input terminals of the comparator CMP are placed after a resistor divider, and the voltage is reduced to the voltage resistance range of the internal MOS of the comparator CMP using the ratio of the voltage divider resistor. Here, the voltages of CANH and CANL after voltage division become CANH×R2 / (R1+R2) and CANL×R2 / (R1+R2).

[0060] In some optional implementations, the comparator CMP includes a hysteresis comparator CMP; a hysteresis threshold of the hysteresis comparator CMP is greater than the implicit threshold and less than the explicit threshold.

[0061] In the embodiment of the present application, the comparator CMP of the present embodiment adopts a hysteresis comparator CMP, and the hysteresis threshold of the hysteresis comparator CMP is set between the maximum recessive threshold and the minimum dominant threshold. When the CAN differential mode is near the recessive threshold, the first NMOS tube M1 and the second PMOS tube M2 are turned on until the CAN differential mode is greater than the hysteresis threshold, and the two input terminal signals of the current conversion circuit are out of balance, thereby increasing the voltage difference between the CAN differential mode and the recessive threshold, so as to generate a larger current difference and improve the response speed. In addition, the use of the hysteresis comparator CMP can also prevent the problem of jitter in the output of the comparator CMP when the voltages of the first input signal and the second input signal are similar.

[0062] Please refer to Figure 4 , Figure 4 A circuit structure diagram of a CAN receiver provided in the third embodiment of the present application. The input optimization circuit of the present embodiment includes: a first diode, a second diode, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0063] Among them, the first input end is connected to the second end of the first diode through the first resistor R1, the second end of the first diode is connected to the first end of the second diode, the first end of the second diode is connected to the first end of the third resistor R3 through the second resistor R2, the first end of the third resistor R3 is connected to the first output end, and the second end of the third resistor R3 is connected to the power supply; the second input end is connected to the first end of the first diode through the fourth resistor R4, the first end of the first diode is connected to the second end of the second diode, the second end of the second diode is connected to the first end of the sixth resistor R6 through the fifth resistor R5, the first end of the sixth resistor R6 is connected to the second output end, and the second end of the sixth resistor R6 is grounded.

[0064] In an embodiment of the present application, a voltage limiting method of opposing diodes is adopted in the input optimization circuit. The first diode and the second diode are diodes with a voltage difference of 0.7V, which limits the voltage difference between the first output signal and the second output signal of the input current conversion circuit to a smaller range, which is within the range of ±0.7×R2 / (R1+R2) in this embodiment.

[0065] Please refer to Figure 5 , Figure 5 This is a structural diagram of the current conversion circuit and the current comparison circuit provided in the embodiments of the present application.

[0066] Wherein, the current conversion circuit includes: a seventh resistor R7, an eighth resistor R8, an operational amplifier OP, a feedback circuit and a current mirror circuit; the first output end is connected to the positive input end of the operational amplifier OP through the eighth resistor R8, and the second output end is connected to the negative input end of the operational amplifier OP through the seventh resistor R7; the positive input end of the operational amplifier OP is connected to the first end of the current mirror circuit, the negative input end of the operational amplifier OP is connected to the second end of the current mirror circuit, the output end of the operational amplifier OP is connected to the feedback circuit, and the third end of the current mirror circuit is connected to the current comparison circuit; the current mirror circuit is used to output the current to be compared to the current comparison circuit; the feedback circuit is used to control the current mirror circuit to connect to the power supply when the voltage difference between the first output signal and the second output signal is greater than 0; when the voltage difference between the first output signal and the second output signal is less than 0, the current mirror circuit is controlled to disconnect from the power supply.

[0067] In the embodiment of the present application, the voltage of the first output signal is converted into current through the eighth resistor R8, and the voltage of the second output signal is converted into current through the seventh resistor R7. Due to the virtual short characteristic of the operational amplifier OP, the currents at the positive and negative input terminals of the input operational amplifier OP are forced to be equal, and the current to be compared is output to the current comparison circuit for comparison through the current mirror circuit.

[0068] In some optional embodiments, the current mirror circuit includes a third MOS tube M3, a sixth MOS tube M6 and a seventh MOS tube M7; the gate of the third MOS tube M3 is connected to the gate of the seventh MOS tube M7, the gate of the third MOS tube M3 is connected to the drain of the third MOS tube M3, and the drain of the third MOS tube M3 is connected to the positive input terminal of the operational amplifier OP; the source of the seventh MOS tube M7 is connected to the source of the sixth MOS tube M6, the drain of the seventh MOS tube M7 is connected to the drain of the sixth MOS tube M6, and the gate of the sixth MOS tube M6 is connected to the negative input terminal of the operational amplifier OP.

[0069] In some optional embodiments, the feedback circuit includes a fourth MOS tube M4 and a fifth MOS tube M5; the source of the fourth MOS tube M4 is connected to the power supply, the source of the fifth MOS tube M5 is connected to the power supply, the gate of the fourth MOS tube M4 and the gate of the fifth MOS tube M5 are connected to the output end of the operational amplifier OP; the drain of the fourth MOS tube M4 is connected to the source of the third MOS tube M3, and the drain of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6.

[0070] In the embodiment of the present application, when the voltage difference between the first output signal and the second output signal is less than 0V, the fourth MOS tube M4 and the fifth MOS tube M5 are turned off, and the entire feedback loop is turned off. When the input is switched to the dominant state at the next moment, it is necessary to start from the closed state, resulting in slow establishment. In some embodiments of the present application, when the CAN differential mode is less than 0V, the voltage difference between the first output signal and the second output signal is limited to 0V to increase the establishment speed.

[0071] In some optional implementations, the current comparison circuit includes a reference current source Iref; and the drain of the sixth MOS transistor M6 is connected to the input end of the reference current source Iref.

[0072] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0073] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0074] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0075] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0076] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A CAN receiver circuit, characterized in that: include: Input optimization circuit, current conversion circuit and current comparison circuit; The input optimization circuit is used to process a first input signal at a first input terminal and output a first output signal at a first output terminal; process a second input signal at a second input terminal and output a second output signal at a second output terminal; and control a voltage difference between the first output signal and the second output signal to be within a set range; The current conversion circuit is used to convert the voltage difference between the first output signal and the second output signal into a current to be compared; The current comparison circuit is used to compare the current to be compared with the reference current to obtain a comparison result.

2. The CAN receiver circuit according to claim 1, characterized in that The current comparison circuit is used to: output a dominant signal when the current to be compared is greater than a first threshold; output a recessive signal when the current to be compared is less than a second threshold; wherein the first threshold is greater than the second threshold, and the second threshold is greater than 0.

3. The CAN receiver circuit according to claim 2, characterized in that The input optimization circuit comprises: a comparator, a first NMOS tube, a second PMOS tube and an inverter; The positive input terminal of the comparator is connected to the first input terminal, the negative input terminal of the comparator is connected to the second input terminal, the output terminal of the comparator is connected to the gate of the first NMOS tube, and the output terminal of the comparator is connected to the gate of the second PMOS tube through the inverter; The positive input terminal of the comparator is connected to the source of the first NMOS tube, and the negative input terminal of the comparator is connected to the drain of the first NMOS tube; the source of the first NMOS tube is connected to the source of the second PMOS tube, and the drain of the first NMOS tube is connected to the drain of the second PMOS tube; The source of the first NMOS tube is connected to the first output end, and the drain of the first NMOS tube is connected to the second output end.

4. The CAN receiver circuit according to claim 3, characterized in that: The input optimization circuit further includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; The first input terminal is connected to the positive input terminal of the comparator through the first resistor, the positive input terminal of the comparator is connected to the source of the first NMOS transistor through the second resistor, and the source of the first NMOS transistor is connected to the power supply through the third resistor; The second input terminal is connected to the negative input terminal of the comparator through the fourth resistor, the negative input terminal of the comparator is connected to the drain of the first NMOS tube through the fifth resistor, and the drain of the first NMOS tube is grounded through the sixth resistor.

5. The CAN receiver circuit according to claim 4, characterized in that: The comparator comprises a hysteresis comparator; a hysteresis threshold of the hysteresis comparator is greater than a recessive threshold and less than a dominant threshold.

6. The CAN receiver circuit according to claim 1, characterized in that: The input optimization circuit includes: a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; The first input terminal is connected to the second end of the first diode through the first resistor, the second end of the first diode is connected to the first end of the second diode, the first end of the second diode is connected to the first end of the third resistor through the second resistor, the first end of the third resistor is connected to the first output terminal, and the second end of the third resistor is connected to a power supply; The second input terminal is connected to the first end of the first diode through the fourth resistor, the first end of the first diode is connected to the second end of the second diode, the second end of the second diode is connected to the first end of the sixth resistor through the fifth resistor, the first end of the sixth resistor is connected to the second output terminal, and the second end of the sixth resistor is grounded.

7. The CAN receiver circuit according to claim 1, characterized in that: The current conversion circuit comprises: a seventh resistor, an eighth resistor, an operational amplifier, a feedback circuit and a current mirror circuit; The first output terminal is connected to the positive input terminal of the operational amplifier through the eighth resistor, and the second output terminal is connected to the negative input terminal of the operational amplifier through the seventh resistor; the positive input terminal of the operational amplifier is connected to the first terminal of the current mirror circuit, the negative input terminal of the operational amplifier is connected to the second terminal of the current mirror circuit, the output terminal of the operational amplifier is connected to the feedback circuit, and the third terminal of the current mirror circuit is connected to the current comparison circuit; The current mirror circuit is used to output the current to be compared to the current comparison circuit; the feedback circuit is used to control the current mirror circuit to connect to the power supply when the voltage difference between the first output signal and the second output signal is greater than 0; and to control the current mirror circuit to disconnect from the power supply when the voltage difference between the first output signal and the second output signal is less than 0.

8. The CAN receiver circuit according to claim 7, characterized in that: The current mirror circuit includes a third MOS tube, a sixth MOS tube and a seventh MOS tube; The gate of the third MOS tube is connected to the gate of the seventh MOS tube, the gate of the third MOS tube is connected to the drain of the third MOS tube, and the drain of the third MOS tube is connected to the positive input terminal of the operational amplifier; the source of the seventh MOS tube is connected to the source of the sixth MOS tube, the drain of the seventh MOS tube is connected to the drain of the sixth MOS tube, and the gate of the sixth MOS tube is connected to the negative input terminal of the operational amplifier.

9. The CAN receiver circuit according to claim 8, characterized in that: The feedback circuit includes a fourth MOS tube and a fifth MOS tube; The source of the fourth MOS tube is connected to the power supply, the source of the fifth MOS tube is connected to the power supply, the gate of the fourth MOS tube and the gate of the fifth MOS tube are connected to the output end of the operational amplifier; the drain of the fourth MOS tube is connected to the source of the third MOS tube, and the drain of the fifth MOS tube is connected to the source of the sixth MOS tube.

10. The CAN receiver circuit according to claim 9, characterized in that: The current comparison circuit includes a reference current source; the drain of the sixth MOS tube is connected to the input end of the reference current source.

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