Semiconductor device

Abstract

A semiconductor device includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell operatively arranged in a first one of a plurality of columns, and operatively arranged in a first one, a second one, a third one, and a fourth one of a plurality of rows, respectively. The first column operatively corresponds to a first pair of bit lines and a second pair of bit lines. The first to fourth rows respectively correspond to a first character line, a second character line, a third character line and a fourth character line. A first pair of bit lines operatively couples the first memory cell and the second memory cell. A second pair of bit lines operatively couples the third memory cell and the fourth memory cell.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, the increase in integration density comes from the continuous reduction in minimum feature size, which allows more components to be integrated into a given area. Utility Model Content

[0003] The present disclosure provides a semiconductor device. The semiconductor device includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, which are operatively arranged in a first column of a plurality of columns, and are operatively arranged in a first row, a second row, a third row, and a fourth row of a plurality of rows, respectively. The first column operatively corresponds to a first pair of bit lines and a second pair of bit lines, and the first to fourth rows correspond to a first word line, a second word line, a third word line, and a fourth word line, respectively. The first pair of bit lines operatively couples the first memory cell and the second memory cell, and the second pair of bit lines operatively couples the third memory cell and the fourth memory cell. The first pair of bit lines physically extends along a first lateral direction through a first portion of a substrate on which the first memory cell and the second memory cell are formed and terminates at a second portion of the substrate on which the third memory cell and the fourth memory cell are formed, and the second pair of bit lines physically extends along the first lateral direction through the first portion and the second portion.

[0004] The present disclosure provides a semiconductor device, including a first memory array, a second memory array, a first pair of bit lines, and a second pair of bit lines. The first memory array includes a plurality of first memory cells formed on a first portion of a substrate. The second memory array includes a plurality of second memory cells formed on a second portion of the substrate, wherein the second portion is physically separated from the first portion along a first lateral direction. The first pair of bit lines physically extends through the first portion and terminates at the second portion. The second pair of bit lines physically extends through the first portion and the second portion.

[0005] The present disclosure provides a semiconductor device, including a first memory cell, a second memory cell, a third memory cell, a fourth memory cell, a first word line, a second word line, a third word line, a fourth word line, a first pair of bit lines, and a second pair of bit lines. The first memory cell and the second memory cell are arranged on a first portion of a substrate. The third memory cell and the fourth memory cell are arranged on a second portion of the substrate. The first portion is separated from the second portion along a first lateral direction. Each of the first to fourth memory cells includes a plurality of transistors formed based on a four-contact polysilicon pitch architecture. The first word line and the second word line are connected to the first memory cell and the second memory cell, respectively. The third word line and the fourth word line are connected to the third memory cell and the fourth memory cell, respectively. The first pair of bit lines connects the first memory cell and the second memory cell. The second pair of bit lines connects the third memory cell and the fourth memory cell. The first pair of bit lines physically extends through the first portion along the first lateral direction and terminates at the second portion. The second pair of bit lines physically extends through the first portion and the second portion along the first lateral direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be more fully understood by reading the detailed description of the following embodiments and referring to the accompanying drawings. It should be emphasized that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a block diagram of a memory array according to some embodiments of the present disclosure;

[0008] Figure 2 is a block diagram of a semiconductor device according to some embodiments of the present disclosure;

[0009] Figure 3 is an example of a circuit schematic diagram of a 6T memory cell according to some embodiments of the present disclosure;

[0010] Figure 4 is a schematic block diagram of a cross-section of an example of a semiconductor device according to some embodiments of the present disclosure;

[0011] Figure 5 is an example of a layout diagram of a memory array configured with a 4CPP architecture according to some embodiments of the present disclosure;

[0012] Figure 6 According to some embodiments of the present disclosure, Figure 5 A memory array, a schematic diagram of a memory array configured with a 4CPP architecture;

[0013] Figure 7is an example of a layout diagram of a memory array configured with a 4CPP architecture according to some embodiments of the present disclosure;

[0014] Figure 8 is an example of a layout diagram of a memory array configured with a 4CPP architecture according to some embodiments of the present disclosure;

[0015] Fig. 9 is an example of a method of making a memory array according to some embodiments.

[0016]

Explanation of symbols

[0017] 10: Memory Array

[0018] 100: memory unit

[0019] WL: Character Line

[0020] BL: Bit Line

[0021] BLB: Complementary Bit Line

[0022] 200:Semiconductor devices

[0023] 202: First memory unit

[0024] 204: Second memory unit

[0025] 206: Third memory unit

[0026] 208: Fourth memory unit

[0027] 210: Block

[0028] 230: Block

[0029] 212: First character line

[0030] 214: Second character line

[0031] 216: Third character line

[0032] 218: Fourth character line

[0033] 222: The first pair of bit lines

[0034] 224: Second pair of bit lines

[0035] WL[0]: word line

[0036] WL[1]: character line

[0037] WL[2]: character line

[0038] WL[3]: character line

[0039] 300: Memory unit

[0040] 301: first reference voltage

[0041] 303: second reference voltage

[0042] 303: Grounding

[0043] 305: Character Line

[0044] 307: Bit line

[0045] 309: Complementary bit line

[0046] 310: Node

[0047] 312: Node

[0048] 314: Node

[0049] 316: Node

[0050] T 1 :transistor

[0051] T 2 :transistor

[0052] T 3 :transistor

[0053] T 4 :transistor

[0054] T 5 :transistor

[0055] T 6 :transistor

[0056] 400:Semiconductor Structure

[0057] 401:Substrate

[0058] 402: Fins

[0059] 403: Quarantine

[0060] 404: Polysilicon structure

[0061] 405: Conductive landing pad

[0062] 410: Transistor

[0063] BEOL: Back-end of the line

[0064] FEOL: Front-End-of-Line

[0065] M1 layer: metallization layer

[0066] M2 layer: metallization layer

[0067] M1_BL: Bit Line

[0068] M2_WL: Character Line

[0069] Via1: through hole

[0070] Via2: Through hole

[0071] 500:Memory array

[0072] 502: Sub-block

[0073] 504: Sub-block

[0074] 506: Sub-block

[0075] 508: Sub-block

[0076] 502: memory unit

[0077] 504: memory unit

[0078] 506: memory unit

[0079] 508: memory unit

[0080] 510: Block

[0081] 520: Block

[0082] 522: The first pair of bit lines

[0083] 524: Second pair of bit lines

[0084] 532: First source / drain interconnect structure

[0085] 534: Second source / drain interconnect structure

[0086] 540: Bit line jumper

[0087] 552: Bottom group

[0088] 554: Top Group

[0089] BL_N[0]: Near-end bit line

[0090] BLB_N[0]: Near-end complementary bit line

[0091] BL_F[0]: Remote bit line

[0092] BLB_F[0]: Remote complementary bit line

[0093] Row[0]: row

[0094] Row[1]: row

[0095] Row[2]: row

[0096] Row[3]: row

[0097] 700:Memory array

[0098] 702: memory unit

[0099] 704: Memory unit

[0100] 706: memory unit

[0101] 708: Memory unit

[0102] 722: First pair of bit lines

[0103] 724: Second pair of bit lines

[0104] 722: Near-end bit line

[0105] 724: Remote bit line

[0106] 734: Source / drain interconnect structure

[0107] 774: Top Group

[0108] 772: Bottom group

[0109] 800:Memory array

[0110] 802: Memory unit

[0111] 804: Memory unit

[0112] 806: memory unit

[0113] 808: Memory unit

[0114] 822: The first pair of bit lines

[0115] 824: Second pair of bit lines

[0116] 822: Near-end bit line

[0117] 824: Remote bit line

[0118] 834: Source / drain interconnect structure

[0119] 884: Top Group

[0120] 882: Bottom group

[0121] 900: Method

[0122] 902: Operation

[0123] 904: Operation

[0124] 906: Operation

[0125] 908: Operation

[0126] 910: Operation DETAILED DESCRIPTION

[0127] The following disclosure provides many different embodiments or examples for realizing the different features of the disclosure. In order to simplify the disclosure, specific examples of components and configurations are described below. Of course, these are just examples and are not meant to be restrictive. For example, the formation of the first feature on the second feature in the following description may include an embodiment in which the first and second features are directly in contact, and may also include an embodiment in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the disclosure may repeat component numbers and / or symbols in various examples. This repetition is for simplicity and clarity, and does not limit the relationship between the various embodiments and / or configurations discussed.

[0128] In addition, for ease of description, spatially relative terms may be used herein, such as "below," "beneath," "below," "above," "above," "top," "bottom," etc., to describe the relationship of one (or some) element or feature to another (or some) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0129] A common integrated circuit memory is a static random access memory (SRAM) device. A typical SRAM memory device has an array of memory cells or "bit-cells". In some examples, each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (usually ground) so that one of the two storage nodes can be occupied by the information to be stored, while the complementary information is stored in the other storage node. Each bit in the SRAM cell is stored on four transistors, forming two cross-coupled inverters. The other two transistors are connected to the memory cell word line, which controls access to the memory cell during read and write operations by selectively connecting the bit cell to its bit line.

[0130] Typically, an SRAM device has an array of memory cells including transistors formed using a fin field effect transistor (FinFET) architecture. For example, a polysilicon / metal structure may be connected to a semiconductor fin that extends above an isolation material. The polysilicon / metal structure acts as the gate of the FinFET transistor, and the voltage applied to the gate determines the flow of electrons between source / drain (S / D) contacts connected to the fin on opposite sides of the gate. The threshold voltage of a FinFET transistor is the minimum voltage when the transistor is "on" and there is significant current flow between the S / D contacts. The number of gates used to form an SRAM cell that contact the fin along its length can be considered the "pitch" of the SRAM cell along one dimension, commonly referred to as the "contacted poly pitch (CPP)". This pitch at least partially determines the density of the SRAM device.

[0131] For example, a double contact polysilicon pitch (2CPP) SRAM cell includes two pass gate transistors, two p-type metal oxide semiconductor (PMOS) transistors, and two n-type metal oxide semiconductor (NMOS) transistors, which are formed together by multiple active regions (such as fins), which have two gates (such as polysilicon or metal structures) connected to the active regions along their lengths, and at least some of the gates have S / D contacts connected to the active regions. When manufacturing a typical 2CPP SRAM architecture, it is necessary to cut a portion of the fins in each cell to form a six-transistor static random access memory (6T SRAM) cell. In addition, memory cells arranged along adjacent rows typically share the same source / drain contact structure, which disadvantageously limits the ability to independently control (e.g., access) one or more specific rows and may cause coupling problems. For example, in a 2CPP SRAM architecture, adjacent cells typically rely on a shared source / drain contact structure to receive a power supply voltage, such as a cell power supply voltage (VDD) or a core power supply voltage (CVDD). In some cases, if you want to change the power supply voltage of some rows, using a 2CPP SRAM architecture will face great challenges. For some 4CPP SRAM architectures, the bit line layout of the interconnect layer (e.g., M2 layer) may encounter coupling problems, thereby reducing the read speed. Therefore, existing SRAM devices are not satisfactory in many aspects.

[0132] The present disclosure provides various embodiments of a memory device (e.g., an SRAM array) configured in a four-contact polysilicon pitch (4CPP) architecture, which is intended to solve the technical problems pointed out above without compromising design limitations. In some embodiments, a memory device as disclosed herein includes a plurality of (e.g., 4) double interleaved word lines and a plurality of fly shared bit lines arranged across a corresponding number (e.g., 4) of memory cells in a 4CPP architecture. The term "double interleaved word lines" may refer to at least four word lines connected to four elements (e.g., memory cells) located at different positions, which are offset from each other along a first lateral direction (a direction parallel to the longitudinal direction of the word lines) and a second lateral direction (a direction orthogonal to the longitudinal direction of the word lines). For example, four different rows of memory cells (of a first column) may be laterally adjacent along the longitudinal direction of the word lines, and four different rows of memory cells (of a second column) may be laterally adjacent along the same longitudinal direction. The term "flying common bit lines" may refer to at least two pairs of bit lines having segmented connections with corresponding elements (e.g., memory cells) located at different positions (e.g., top group and bottom group), respectively. Therefore, the length of the corresponding bit lines and complementary bit lines of the disclosed memory device can be significantly reduced to about 4CPP (e.g., 2 times shorter than the existing SRAM array). Therefore, the load of the bit lines and complementary bit lines of the disclosed memory device can be advantageously reduced. This reduction in the load on the bit lines and complementary bit lines allows the disclosed memory device to be enlarged (e.g., in size) without affecting its performance. By simultaneously utilizing the flying common bit lines and interleaved word lines separated by groups in 4CPP cells, the present disclosure provides a memory device design that avoids bit line coupling and reduces bit line load.

[0133] Figure 1 is a block diagram of a memory array 10 according to some exemplary embodiments. Figure 1 A memory array 10 having a plurality of memory cells 100 or bit cells is shown. One or more peripheral circuits (not shown) may be located in one or more peripheral regions or within the memory array 10. The memory cells 100 and the external circuits may be coupled via word lines WL and / or complementary bit lines BL and BLB, and data may be read from and written to the memory cells 100 via the complementary bit lines BL and BLB. Different voltage combinations applied to the word lines and bit lines may define a read, erase, or write (program) operation to the memory cells.

[0134] Figure 2 A semiconductor device 200 (eg, a memory array (eg, Figure 11 is a schematic diagram of a layout of a memory array 10) in FIG. The semiconductor device 200 may include a first memory cell 202, a second memory cell 204, a third memory cell 206, a fourth memory cell 208, a plurality of word lines (e.g., WL[0], WL[1], WL[2], and WL[3]), a first pair of bit lines 222, and a second pair of bit lines 224. The first to fourth memory cells are formed based on a four-contact polysilicon transistor architecture (4CPP).

[0135] The first memory cell 202, the second memory cell 204, the third memory cell 206, and the fourth memory cell 208 are operatively arranged along a first of a plurality of columns. The first memory cell 202, the second memory cell 204, the third memory cell 206, and the fourth memory cell 208 are operatively arranged in a first of a plurality of rows, a second of a plurality of rows, a third of a plurality of rows, and a fourth of a plurality of rows. The first column operatively corresponds to a first pair of bit lines 222 and a second pair of bit lines 224. The first to fourth rows correspond to a first word line 212, a second word line 214, a third word line 216, and a fourth word line 218, respectively.

[0136] The layout diagram of the semiconductor device 200 includes a plurality of blocks adjacent to each other along a lateral direction (e.g., an X direction), and each block may correspond to memory cells spanning different rows along a common column (e.g., along a pair of bit lines), according to various embodiments. Figure 2 Block 210 corresponds to memory cells arranged along a first pair of bit lines 222 and a second pair of bit lines 224 across the first to fourth rows (e.g., WL[0], WL[1], WL[2], and WL[3]). The memory cells may be located at the intersection of corresponding pairs of columns and rows. A pair of first bit lines (BL) and first complementary bit lines (BLB) and a pair of second bit lines (BL) and second complementary bit lines (BLB) are arranged along each column and a word line (WL) is arranged along each row.

[0137] The first memory cell 202 is physically arranged next to the second memory cell 204 along a second lateral direction (e.g., X). The third memory cell 206 is physically arranged next to the fourth memory cell 208 along the second lateral direction (e.g., X), and the second lateral direction (e.g., X) is perpendicular to the first lateral direction (e.g., Y). In some embodiments, the first memory cell 202 and the third memory cell 206 are aligned but physically separated along the first lateral direction (e.g., Y), and the second memory cell 204 and the fourth memory cell 208 are aligned but physically separated along the first lateral direction (e.g., Y).

[0138] The first pair of bit lines 222 is operatively coupled to the first memory cell 202 and the second memory cell 204. The second pair of bit lines 224 is operatively coupled to the third memory cell 206 and the fourth memory cell 208. The first pair of bit lines 222 and the second pair of bit lines 224 are formed on the same one of a plurality of metallization layers disposed on a substrate. Although the word lines (e.g., WL[0] to WL[3]) and the bit lines are Figure 2 In the layout schematic diagram of the semiconductor device 200 of FIG. 1 , the interconnect structures of the access lines are shown as extending in the X direction and the Y direction, respectively, but it should be understood that the corresponding physical interconnect structures as such access lines can extend in another direction while remaining within the scope of the present disclosure. In addition, although the paired bit lines can form interconnect structures extending in the Y direction in the bottommost metallization layer (sometimes referred to as "M0 track"), the word lines WL[0] to WL[3] can form interconnect structures extending in the X direction in the next upper metallization layer (sometimes referred to as "M1 track"), respectively, but the word lines WL[0] to WL[3] can be formed in one or more even-numbered upper metallization layers. For example, the word lines WL[0] to WL[3] can form interconnect structures extending in the X direction in the even-numbered upper metallization layer (e.g., as M3 track or M5 track). In another example, a first subset of word lines (eg, word lines WL[0] and WL[2]) may each form an M3 track, while a second subset of word lines (eg, word lines WL[1] and WL[3]) may each form an M5 track.

[0139] In some embodiments, the bit lines can extend across two groups or sub-arrays of memory cells, e.g., a top group and a bottom group. A first pair of bit lines 222 physically extends along a first lateral direction (e.g., Y) through a first portion (e.g., bottom group) of the substrate on which the first memory cell 202 and the second memory cell 204 are formed and terminates at a second portion (e.g., top group) of the substrate on which the third memory cell 206 and the fourth memory cell 208 are formed. The second pair of bit lines 224 also physically extends along the first lateral direction (e.g., Y) through both the first portion (e.g., bottom group) and the second portion (e.g., top group). In some embodiments, the first memory cell 202 and the second memory cell 204 belong to the first memory group (e.g., bottom group), while the third memory cell 206 and the fourth memory cell 208 belong to the second memory group (e.g., top group).

[0140] According to various embodiments of the present disclosure, using the disclosed arrangement, each bit line and complementary bit line can have a length of about 4 CPP. Such a significantly shortened length (e.g., compared to the 8 CPP length of existing memories) allows the disclosed memory device to be more flexibly scaled up in size without sacrificing the load on the bit lines (and complementary bit lines). For example, to form an 8×8 memory array, the length of the bit lines and complementary bit lines of such a memory array can only be increased to about 8 CPP, instead of 16 CPP in existing memories. Shorter bit lines generally have lower resistance, which can advantageously reduce the voltage drop along the bit lines, thereby increasing the operating speed of the memory device.

[0141] Figure 3 FIG. 6 is a circuit diagram of a memory cell 6T according to some embodiments. Figure 3 , depicts a circuit diagram of a memory cell 300 (a memory bit or a bit). According to some embodiments of the present disclosure, the memory cell 300 is configured as a static random access memory (SRAM) cell, which includes a plurality of transistors. For example, Figure 3 , the memory cell 300 includes a six-transistor (6T)-SRAM. Each transistor can be formed in a nanostructured transistor configuration, which will be discussed in further detail below. In some other embodiments, the memory cell 300 can be implemented as any of a variety of other SRAM cells, such as a two-transistor-two-resistor (2T-2R) SRAM cell, a four-transistor (4T)-SRAM cell, an eight-transistor (8T)-SRAM cell, a ten-transistor (10T)-SRAM cell, etc. In addition, although the discussion of the current disclosure is directed to SRAM cells, it is understood that other embodiments of the current disclosure can also be used for any memory cell, such as a dynamic random access (DRAM) memory cell.

[0142] like Figure 3 As shown, the memory cell 300 includes 6 transistors: T 1 , T 2 , T 3 , T 4 , T 5 and T 6 . Transistor T 1 and T 2 Formed as a first inverter, transistor T 3 and T 4The first and second inverters are formed as a second inverter, wherein the first and second inverters are cross-coupled with each other. Specifically, the first and second inverters are respectively coupled between the first reference voltage 301 and the second reference voltage 303. In some embodiments, the first reference voltage 301 is a power supply voltage (usually referred to as “V DD ”) voltage level. The second reference voltage 303 is usually called “ground”. The first inverter (composed of transistor T 1 and T 2 Composition) and transistor T 5 The second inverter (consisting of transistor T 3 and T 4 Composition) and transistor T 6 In addition to being coupled to the first and second inverters, transistor T 6 and T 5 They are respectively coupled to word line 305, and are respectively coupled to bit line 307 and complementary bit line 309 (sometimes referred to as bit line bar or BLB).

[0143] In some embodiments, the transistor T 1 and T 3 The memory cell 300 is respectively referred to as a pull-up transistor (hereinafter referred to as a “pull-up transistor T 1 ” and “pull-up transistor T 3 ”) Transistor T 2 and T 4 The pull-down transistor (hereinafter referred to as “pull-up transistor T 2 ” and “pull-down transistor T 4 ”) and transistor T 5 and T 6 The memory cell 300 includes an access transistor (hereinafter referred to as “access transistor T 5 ” and “Access transistor T 6 ”). In some embodiments, the transistor T 2 , T 4 , T 5 and T 6 Each includes an NMOS transistor, and the transistor T 1 and T 3 Each includes a PMOS transistor. Although Figure 3 The embodiment shows that the transistor T 1 To T 6It is an NMOS transistor or a PMOS transistor, but any of various transistors suitable for memory devices or devices can be implemented as a transistor T 1 To T 6 At least one of, for example, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), etc.

[0144] Access transistor T 5 and T 6 Each has a gate coupled to word line 305. Transistor T 5 and T 6 The gate of transistor T is configured to receive a pulsating signal via word line 305 to allow or prevent access to memory cell 300, as will be discussed in more detail below. 2 and T 5 At node 310, a transistor T 2 The drain of transistor T 5 The sources of the transistors T 1 The drain of transistor T 4 and T 6 At node 314, transistor T 4 The drain of transistor T 6 The sources of the transistors T 3 drain and node 316.

[0145] When a memory cell (e.g., memory cell 300) stores a data bit, a first node of the bit cell is configured to be in a first logic state (logic 1 or logic 0), and a second node of the bit cell is configured to be in a second logic state (logic 0 or logic 1). The first and second logic states are complementary. In some embodiments, the first logic state at the first node can represent the logic state of the data bit stored in the memory cell. For example, in Figure 3 In the illustrated embodiment, when the memory cell 300 stores a data bit at a logic 1 state, the node 310 is configured at a logic 1 state and the node 314 is configured at a logic 0 state.

[0146] To read the logic state of the data bit stored in memory cell 300, bit line 307 and complementary bit line 309 are precharged to V DD (e.g., a logical high level, for example, using a capacitor to hold a charge). Then, the word line 305 is validated or activated to a logical high level by the validation signal, thereby turning on the access transistor T5 and T 6 Specifically, in the access transistor T 5 and T 6 The gates of the access transistors T receive the rising edge of the valid signal, thereby turning on the access transistors T 5 and T 6 Once the access transistor T 5 and T 6 When the access transistor T is turned on, the pre-charged bit line 307 or the complementary bit line 309 may begin to discharge, depending on the logic state of the data bit. For example, when the memory cell 300 stores a logic 0, the node 314 (e.g., Q bar) may present a voltage corresponding to a logic 1, and the node 310 (e.g., Q bar) may present a complementary voltage corresponding to a logic 0. 5 and T 6 is turned on, starting from the pre-charged complementary bit line 309 through the access transistor T 5 and the pull-down transistor T 2 When the voltage level on the complementary bit line 309 is pulled down by this discharge path, the pull-down transistor T 4 Therefore, the bit line 307 and the complementary bit line 309 may each present a voltage level to generate a sufficiently large voltage difference between the bit line 307 and the complementary bit line 309. Therefore, the sense amplifier coupled to the bit line 307 and the complementary bit line 309 can use the polarity of the voltage difference to determine whether the logic state of the data bit is a logic 1 or a logic 0.

[0147] To write the logic state of the data bit stored in the memory cell 300, the data to be written is applied to the bit line 307 and / or the complementary bit line 309. For example, the complementary bit line 309 is connected / shorted to 0V, such as ground 303, with a low impedance connection. Then, the word line 305 is asserted or activated to a logic high level by an assertion signal, thereby turning on the access transistor T 5 and T 6 Once the access transistor T 5 and T 6 is turned on, node 310 may begin to discharge based on the logic state of complementary bit line 309. 5 and T 6 Before being turned on, the complementary bit line 309 may present a voltage corresponding to a logic 0, and the node 310 may present a voltage corresponding to a complementary logic 1. 5 and T 6 is turned on, starting from node 310 through access transistor T 5A discharge path to ground 303 is created. Once the voltage level on node 310 is pulled down to the pull-down transistor T 4 Below the threshold voltage Vth, the transistor T 4 may be closed, transistor T 3 may turn on, causing node 314 to be pulled up to V DD 301. Once node 314 is less than V DD The threshold voltage Vth of transistor 301 is 1 may be closed, transistor T 2 may be turned off, causing node 310 to be pulled down to ground 303. Then, when word line 305 is deasserted, the logic state applied to bit line 307 and / or complementary bit line 309 has been stored in memory cell 300.

[0148] To further illustrate these structures in Figure 2 relative (e.g., vertical) arrangement in Figure 4 A semiconductor structure 400 (eg, Figure 2 The embodiment shown includes: a front-end-of-line (FEOL) layer including a semiconductor structure and a back-end-of-line (BEOL) layer including an interconnect metal layer structure.

[0149] In some embodiments shown, the FEOL layer shows a transfer gate FinFET transistor 410. The FinFET transistor 410 includes a semiconductor substrate 401, a fin 402, an isolation region 403, a polysilicon structure 404, such as polysilicon, a conductive contact S and a contact D connected to the fin 402, and a contact G connected to the polysilicon structure 404. In some embodiments shown, the conduction path of the current is the fin 402 (which may also be referred to as a diffusion region or an oxide diffusion region). The polysilicon structure 404 acts as a gate, allowing current to flow from the contact S (e.g., source) to the contact D (e.g., drain) in the fin 402. For example, for a voltage potential between the contact S and the contact D, depending on the voltage applied to the polysilicon structure 404, current can flow from the contact S to the contact D in the fin 402. If a voltage less than the threshold voltage is applied to the polysilicon, a considerable current cannot flow from the contact S to the contact D, and the transistor 410 is "off". If a voltage greater than or equal to the threshold voltage is applied to the polysilicon, a significant current flows from contact S to contact D through the fin 402, and the transistor 410 is "on". In some embodiments, contact S, contact D, and contact G form connections between multiple fins 402 and polysilicon structure 404 of the FEOL layer, thereby connecting the source, drain, and gate of one or more transistors. In some embodiments, the source, drain, and gate of transistor 410 are connected to the interconnect metal layer structure of the BEOL layer. For example, typically the gate of transistor 410 is connected to a word line, which is one of the metal bars of one of the interconnect metal layer structures in the BEOL layer, and the S / D contacts of the transfer gate transistor 410 can also be connected to complementary bit lines BL and BLB, which are other metal bars of one or more metal layers in the BEOL layer. In some embodiments, the BEOL layer is used to connect the transistor 410 to peripheral circuits, such as for read / write operations. In some embodiments shown, contact D and contact G are connected to the metal bars of the BEOL layer using vias. For example, via Via1 forms a connection between contact D and a metal bar (e.g., bit line M1_BL) in the first metallization layer (M1 layer) above the FEOL layer. In some embodiments shown, a separate via Via1 connects the G contact to a conductive landing pad 405 of the M1 layer, and via Via2 connects the conductive landing pad 405 to a metal bar of the M2 layer, such as a word line M2_WL. In some implementations, the conductive landing pad 405 of the M1 layer can be formed by a metal bar that is cut or disconnected on its metal layer plane.

[0150] Figure 5 is a memory array 500 configured in a 4CPP architecture according to some embodiments of the present disclosure (e.g., Figure 2 An example of a semiconductor device 200 in FIG. Figure 6 Some embodiments according to the present disclosure are shown, corresponding to Figure 5 Schematic diagram of a memory array configured in a 4CPP architecture, including a first block 510 of FIG. 5 . The memory array 500 may include a first block 510, a second block 520, a first sub-block 502 (e.g., a first memory cell), a second sub-block 504 (e.g., a second memory cell), a third sub-block 506 (e.g., a third memory cell), a fourth sub-block 508 (e.g., a fourth memory cell), a plurality of word lines (e.g., WL[0], WL[1], WL[2], and WL[3]), a first pair of bit lines 522, a second pair of bit lines 524, a pair of first source / drain interconnect structures 532, a pair of second source / drain interconnect structures 534, and a bit line jumper 540 (or a bit line cut). Figure 5 The memory array 500 and Figure 2 The semiconductor device 200 of the memory array 500 is substantially similar except for the bit line jumpers 540 and the specific row sequence to further avoid bit line coupling. Therefore, the following description will focus on the differences of the memory array 500.

[0151] According to various embodiments, each block 510 or 520 includes four sub-blocks, and each sub-block may correspond to a memory cell. Taking block 510 as a representative example, block 510 has four sub-blocks 502, 504, 506, and 508. Sub-block 502 corresponds to a memory cell at the intersection of word line WL[0] (row [0]) and a proximal bit line of a first pair of bit lines 522 (referred to herein as “BL_N[0]”). Sub-block 504 corresponds to a memory cell at the intersection of word line WL[1] (row [1]) and a proximal complementary bit line 522 of the first pair of bit lines (hereinafter referred to as “BLB_N[0]”). Sub-block 506 corresponds to a memory cell at the intersection of word line WL[2] (row [2]) and a distal bit line of a second pair of bit lines 522 (hereinafter referred to as “BL_F[0]”). The sub-block 508 corresponds to the memory cells at the intersection of the word line WL[3] (row[3]) and the far complementary bit line of the second pair of bit lines 522 (hereinafter referred to as “BLB_F[0]”).

[0152] In various embodiments, Figure 5 Each of the blocks 510 to 520 in the embodiment is configured in a 4CPP architecture. In other words, each block has four polysilicon / metal (gate) structures passing through them. In some embodiments, each sub-block may also have four polysilicon / metal (gate) structures passing through them. These four gates correspond to word lines WL[0], WL[1], WL[2], and WL[3], respectively.

[0153] Multiple word lines can be dual-staggered word lines. The term "dual-staggered word lines" can refer to at least four word lines and four elements (e.g., memory cells) located at different positions, respectively, and these elements are offset from each other along a first lateral direction (a direction parallel to the longitudinal direction of the word line) and a second lateral direction (a direction orthogonal to the longitudinal direction of the word line). Therefore, memory cells in different rows (corresponding to different word lines) in the same column (corresponding to the same bit line) can be separated from each other or arranged in other ways based on such staggered word lines WL[0] to WL[3], while memory cells in different columns (corresponding to different bit lines) can be adjacent to each other using staggered word lines WL[0] to WL[3]. Figure 5 As shown. For example, the first memory cell 502 and the third memory cell 506 may be operably (e.g., electrically) coupled to word lines WL[0] and WL[2] (referred to herein as “Row[n]”). The second memory cell 504 and the fourth memory cell 508 may be operably (e.g., electrically) coupled to word lines WL[1] and WL[3] (referred to herein as “Row[n+1]”). In some embodiments, block 520 may have a dual staggered word line arrangement like block 510. The sequence of rows of the memory array 500 may be Row[n], Row[n+1], Row[n], Row[n+1] to effectively avoid bit line coupling.

[0154] In addition, at least two sub-blocks of each block are adjacent to each other along a lateral direction (e.g., X direction) and can share a pair of common bit lines and complementary bit lines. There can be a pair of proximal bit lines 522 and a pair of distal bit lines 524 in the memory array 500. In some embodiments, memory cells in different rows in the same column (corresponding to different word lines) can share a pair of common bit lines and complementary bit lines. For example, two sub-blocks 502 and 504 of block 510 (memory cells along the first pair of bit lines 522 and passing through word line WL[0] to word line WL[1]) are connected through a pair of first source / drain interconnect structures 532 ( 1st The two sub-blocks 506 and 508 of block 510 (memory cells along the second pair of bit lines 524 and through word lines WL[2] to WL[3]) are connected through a pair of second source / drain interconnect structures 534 (2 nd MDs) share the remote bit line BL_F[0] and the remote complementary bit line BLB_F[0].

[0155] In some embodiments, the first pair of bit lines 522 and the second pair of bit lines 524 can be formed in the same metallization layer (e.g., M0, M2, or M4 layer). In different embodiments, a common bit line structure can be configured in the memory array 500. The term "flying common bit line" can refer to at least two pairs of bit lines having segmented connections with corresponding elements (e.g., memory cells) located at different positions (e.g., top group and bottom group). For example, the first pair of bit lines 522 physically extends along a first lateral direction (e.g., Y) through a first portion of the substrate where the first memory cell 502 and the second memory cell 504 are formed and terminates at a bit line jumper 540 (e.g., an intermediate transition region). The second pair of bit lines 524 also physically extends along the first lateral direction (e.g., Y) through the first portion, the bit line jumper 540, and a second portion of the substrate where the third memory cell 506 and the fourth memory cell 508 are formed. In some embodiments, the bit line jumper 540 can be a 2CPP or 4CPP transition for bit line cutting. The first memory cell 502 can be physically separated from the third memory cell 506 along a first lateral direction (e.g., Y). The second memory cell 504 can be physically separated from the fourth memory cell 508 along the first lateral direction (e.g., Y).

[0156] The bit lines may be spread across two groups or subgroups of memory cells, e.g., a top group 554 and a bottom group 552. The first memory cell 502 and the second memory cell 504 may belong to the first memory group (e.g., the bottom group), while the third memory cell 506 and the fourth memory cell 508 may belong to the second memory group (e.g., the top group). The flying shared bit lines separated by groups in the 4CPP cell have an interleaved word line design that can improve speed and power (e.g., resistor-capacitor (RC) optimization). For example, the front-end capacitance can be maintained at 0.5 times that of the 2CPP conventional cell. Due to the shorter length of the bit lines and the larger space, the back-end capacitance and the front-end capacitance can be reduced. Since the shared bit line and word line sequence avoids accessing the same column, there is no coupling problem. The read speed is more aggressive due to the smaller bit line capacitance and the absence of bit line coupling problems. By utilizing both flying common bit lines and interleaved word lines separated by groups in 4CPP cells, the present disclosure provides a memory device design that avoids bit line coupling and reduces bit line loading.

[0157] Figure 7 is an example of a layout diagram of a memory array 700 configured in a 4CPP architecture according to some embodiments of the present disclosure. Figure 7 The memory array 700 is substantially similar to Figure 5The memory array 500 of FIG. 5 further reduces the bit line capacitance by arranging the remote bit lines 724 and the source / drain interconnect structure. Therefore, the following description will focus on the differences of the memory array 700.

[0158] In some embodiments, a pair of proximal bit lines 722 may be formed in a first of a plurality of metallization layers disposed on a substrate. A pair of distal bit lines 724 may include two portions formed in different metallization layers. For example, a first portion of a pair of distal bit lines 724 may be formed in a first metallization layer (e.g., M2 layer) of a plurality of metallization layers. A second portion of a pair of distal bit lines 724 may be formed in a second metallization layer (e.g., M1 layer) of a plurality of metallization layers. The first portion of each pair of distal bit lines 724 may extend along a first lateral direction (e.g., Y). The second portion of each pair of distal bit lines 724 may extend along a second lateral direction (e.g., X). The order in which a pair of distal bit lines 724 are formed in the plurality of metallization layers may be: M2→M1→M2. The source / drain interconnect structure 734 may be shorter on the top group to reduce the bit line capacitance. The bit line jumper 540 can be a 2CPP or 4CPP transition to optimize the bit line resistance capacitance (R / C).

[0159] Figure 8 is an example of a layout diagram of a memory array 800 configured with a 4CPP architecture according to some embodiments of the present disclosure. Figure 8 The memory array 800 is substantially similar to Figure 5 In addition to arranging remote bit lines 824 and source / drain interconnect structures to further reduce bit line capacitance, the memory array 500 of FIG. 800 will be described below with focus on the differences of the memory array 800 .

[0160] In some embodiments, a pair of proximal bit lines 822 may be formed in a first of a plurality of metallization layers disposed on a substrate. A pair of distal bit lines 824 may include three portions formed in different metallization layers. For example, a first portion of a pair of distal bit lines 824 may be formed in a first metallization layer (e.g., M4 layer) of a plurality of metallization layers. A second portion of a pair of distal bit lines 824 may be formed in a second metallization layer (e.g., M3 layer) of a plurality of metallization layers. A third portion of a pair of distal bit lines 824 may be formed in a third metallization layer (e.g., M2 layer) of a plurality of metallization layers. The formation order of a pair of distal bit lines 824 in a plurality of metallization layers may be: M4→M3→M2. The source / drain interconnect structure 834 may be shorter on the top group to reduce the bit line capacitance. A pair of proximal bit lines 822 may be formed in a third metallization layer (e.g., M2 layer) of a plurality of metallization layers. The M2 layer may have a larger space to reduce the bit line capacitance. The bit line jumper 540 can be a 2CPP or 4CPP transition to optimize the bit line resistance capacitance (R / C). The first memory cell 802 can be aligned with the third memory cell 806 along a first lateral direction (e.g., Y) but physically separated. The second memory cell 804 can be aligned with the fourth memory cell 808 along a first lateral direction (e.g., Y) but physically separated.

[0161] Fig. 9 is an example of a method of fabricating a memory array according to some embodiments. In summary, method 900 can include fabricating a memory array to avoid bit line coupling and reduce bit line loading.

[0162] The method 900 begins with operation 902, where a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell may be provided. For example, the memory cells may be based on the semiconductor device 200 ( Figure 2 )、Memory array 500( Figure 5 )、Memory array 700( Figure 7 ), or memory array 800 ( Figure 8). A first memory cell (corresponding to, for example, 202, 502, 702, or 802) and a second memory cell (corresponding to, for example, 204, 504, 704, or 804) may be arranged in a first portion of the substrate. A third memory cell (corresponding to, for example, 206, 506, 706, or 806) and a fourth memory cell (corresponding to, for example, 208, 508, 708, or 808) may be arranged in a second portion of the substrate. The first portion may be separated from the second portion along a first lateral direction (e.g., Y direction). Each of the first to fourth memory cells may include a plurality of transistors formed in a four-contact polysilicon transistor (4CPP) architecture. The first memory cell (corresponding to, for example, 202, 502, 702, or 802) and the second memory cell (corresponding to, for example, 204, 504, 704, or 804) may be arranged adjacent to each other along a second lateral direction (e.g., X direction) perpendicular to the first lateral direction (e.g., Y direction). The third memory unit (corresponding to, for example, 204, 504, 704 or 804) and the fourth memory unit (corresponding to, for example, 208, 508, 708 or 808) may be physically arranged adjacent to each other along the second lateral direction (eg, X direction).

[0163] Method 900 continues with operation 904, where the first word line and the second word line can be connected to the first memory cell and the second memory cell, respectively. In some embodiments, the first word line (corresponding to Figure 2 , Figure 5 , Figure 7 or Figure 8 The word line WL[0] in FIG. 1 may be connected to a first memory cell (corresponding to, for example, 202, 502, 702, or 802), and the second word line (corresponding to Figure 2 , Figure 5 , Figure 7 or Figure 8 The word line WL[1] in can be connected to a second memory unit (corresponding to, for example, 204, 504, 704 or 804).

[0164] Method 900 continues with operation 906, where a third word line and a fourth word line may be connected to the third memory cell and the fourth memory cell, respectively. Figure 2 , Figure 5 , Figure 7 or Figure 8 The word line WL[2] in can be connected to a third memory unit (corresponding to, for example, 206, 506, 706 or 806), and Figure 2 , Figure 5 , Figure 7 or Figure 8The fourth word line in (corresponding to word line WL[3]) can be connected to a fourth memory cell (corresponding to, for example, 208, 508, 708 or 808).

[0165] The method 900 continues with operation 908, where a first pair of bit lines can be connected to the first memory cell and the second memory cell. For example, the first pair of bit lines (corresponding to 222, 522, 722, or 822) can be connected to the first memory cell (corresponding to, for example, 202, 502, 702, or 802) and the second memory cell (corresponding to, for example, 204, 504, 704, or 804). In some embodiments, the first pair of bit lines (corresponding to 222, 522, 722, or 822) can physically extend through the first portion along a first lateral direction (e.g., the Y direction) and can terminate at the second portion.

[0166] The method 900 continues with operation 910, where a second pair of bit lines can be connected to the third memory cell and the fourth memory cell. For example, the second pair of bit lines (corresponding to 224, 524, 724, or 824) can be connected to the third memory cell (corresponding to, for example, 206, 506, 706, or 806) and the fourth memory cell (corresponding to, for example, 208, 508, 708, or 808). The second pair of bit lines (corresponding to 224, 524, 724, or 824) can physically extend through the first portion and the second portion along a first lateral direction (e.g., the Y direction). Compared to the conventional 2CPP wide cell, the common bit lines on the 4CPP SRAM tall cell adopt an interleaved word line design to improve read speed and coupling issues.

[0167] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0168] The present disclosure provides a semiconductor device. The semiconductor device includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, which are operatively arranged in a first column of a plurality of columns, and are operatively arranged in a first row, a second row, a third row, and a fourth row of a plurality of rows, respectively. The first column operatively corresponds to a first pair of bit lines and a second pair of bit lines, and the first to fourth rows correspond to a first word line, a second word line, a third word line, and a fourth word line, respectively. The first pair of bit lines operatively couples the first memory cell and the second memory cell, and the second pair of bit lines operatively couples the third memory cell and the fourth memory cell. The first pair of bit lines physically extends along a first lateral direction through a first portion of a substrate on which the first memory cell and the second memory cell are formed and terminates at a second portion of the substrate on which the third memory cell and the fourth memory cell are formed, and the second pair of bit lines physically extends along the first lateral direction through the first portion and the second portion.

[0169] In some embodiments, the first to fourth memory cells are respectively formed based on a quad-contact polysilicon pitch transistor architecture.

[0170] In some embodiments, the first memory cell is adjacent to the second memory cell along a second lateral direction, and the third memory cell is adjacent to the fourth memory cell along the second lateral direction, and the second lateral direction is perpendicular to the first lateral direction.

[0171] In some embodiments, the first memory unit and the third memory unit are aligned along a first lateral direction but are physically separated, and the second memory unit and the fourth memory unit are aligned along the first lateral direction but are physically separated.

[0172] In some embodiments, the first memory unit and the second memory unit belong to a first memory group, and the third memory unit and the fourth memory unit belong to a second memory group.

[0173] In some embodiments, the first pair of bit lines and the second pair of bit lines are formed in a same one of a plurality of metallization layers disposed on a substrate.

[0174] In some embodiments, the first pair of bit lines is formed in a first of a plurality of metallization layers disposed on a substrate, and each of the second pair of bit lines has a first portion and a second portion, wherein the first portion is formed in the first of the metallization layers and the second portion is formed in the second of the metallization layers.

[0175] In some implementations, a first portion of each of the second pair of bit lines extends in a first lateral direction and a second portion of each of the second pair of bit lines extends in a second lateral direction.

[0176] In some embodiments, the first pair of bit lines is formed in a first of a plurality of metallization layers disposed on a substrate, and each of the second pair of bit lines has a first portion, a second portion, and a third portion, wherein the first portion is formed in a first of the metallization layers, the second portion is formed in a second of the metallization layers, and the third portion is formed in a third of the metallization layers.

[0177] In some embodiments, the first portion and the third portion of each of the second pair of bit lines extend in a first lateral direction, and the second portion of each of the second pair of bit lines extends in a second lateral direction.

[0178] The present disclosure provides a semiconductor device, including a first memory array, a second memory array, a first pair of bit lines, and a second pair of bit lines. The first memory array includes a plurality of first memory cells formed on a first portion of a substrate. The second memory array includes a plurality of second memory cells formed on a second portion of the substrate, wherein the second portion is physically separated from the first portion along a first lateral direction. The first pair of bit lines physically extends through the first portion and terminates at the second portion. The second pair of bit lines physically extends through the first portion and the second portion.

[0179] In some embodiments, the first pair of bit lines is operatively coupled only to the first memory cell, and the second pair of bit lines is operatively coupled only to the second memory cell.

[0180] In some embodiments, the first memory cells are physically side-by-side along a second lateral direction, the second lateral direction is perpendicular to the first lateral direction, and the second memory cells are physically side-by-side along the second lateral direction.

[0181] In some embodiments, adjacent first memory cells are operatively coupled to different word lines, respectively, and adjacent second memory cells are operatively coupled to different word lines, respectively.

[0182] In some embodiments, the first pair of bit lines and the second pair of bit lines are formed in a same one of a plurality of metallization layers disposed on a substrate.

[0183] In some embodiments, the first pair of bit lines is formed in a first one of the metallization layers disposed on the substrate, and each of the second pair of bit lines has a first portion and a second portion, wherein the first portion is formed in the first one of the metallization layers and the second portion is formed in the second one of the metallization layers.

[0184] In some embodiments, the first pair of bit lines is formed in a first one of the metallization layers disposed on the substrate, and each of the second pair of bit lines has a first portion, a second portion, and a third portion, wherein the first portion is formed in the first one, the second portion is formed in the second one of the metallization layers, and the third portion is formed in the third one of the metallization layers.

[0185] In some embodiments, the first memory cell and the second memory cell are respectively formed based on a quad-contact polysilicon pitch transistor architecture.

[0186] The present disclosure provides a method for forming a semiconductor device, the method comprising the following steps: arranging a first memory cell and a second memory cell on a first portion of a substrate, arranging a third memory cell and a fourth memory cell on a second portion of the substrate, the first portion being separated from the second portion along a first lateral direction, wherein each of the first to fourth memory cells comprises a plurality of transistors formed based on a four-contact polysilicon pitch architecture. Connecting a first word line and a second word line to the first memory cell and the second memory cell, respectively. Connecting a third word line and a fourth word line to the third memory cell and the fourth memory cell, respectively. Connecting a first pair of bit lines to the first memory cell and the second memory cell. Connecting a second pair of bit lines to the third memory cell and the fourth memory cell. The first pair of bit lines physically extends through the first portion along the first lateral direction and terminates at the second portion, and the second pair of bit lines physically extends through the first portion and the second portion along the first lateral direction.

[0187] In some embodiments, the first memory unit and the second memory unit are physically adjacent to each other along a second lateral direction, the second lateral direction is perpendicular to the first lateral direction, and the third memory unit and the fourth memory unit are physically adjacent to each other along the second lateral direction.

[0188] The present disclosure provides a semiconductor device, including a first memory cell, a second memory cell, a third memory cell, a fourth memory cell, a first word line, a second word line, a third word line, a fourth word line, a first pair of bit lines, and a second pair of bit lines. The first memory cell and the second memory cell are arranged on a first portion of a substrate. The third memory cell and the fourth memory cell are arranged on a second portion of the substrate. The first portion is separated from the second portion along a first lateral direction. Each of the first to fourth memory cells includes a plurality of transistors formed based on a four-contact polysilicon pitch architecture. The first word line and the second word line are connected to the first memory cell and the second memory cell, respectively. The third word line and the fourth word line are connected to the third memory cell and the fourth memory cell, respectively. The first pair of bit lines connects the first memory cell and the second memory cell. The second pair of bit lines connects the third memory cell and the fourth memory cell. The first pair of bit lines physically extends through the first portion along the first lateral direction and terminates at the second portion. The second pair of bit lines physically extends through the first portion and the second portion along the first lateral direction.

[0189] In some embodiments, the first memory unit and the second memory unit are physically adjacent to each other along a second lateral direction, the second lateral direction is perpendicular to the first lateral direction, and the third memory unit and the fourth memory unit are physically adjacent to each other along the second lateral direction.

[0190] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of this disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that: include: A first memory unit, a second memory unit, a third memory unit and a fourth memory unit are operatively arranged in a first row of the plurality of columns, and are operatively arranged in a first row, a second row, a third row and a fourth row of the plurality of rows, respectively; Wherein, the first row operatively corresponds to a first pair of bit lines and a second pair of bit lines, and the first row to the fourth row correspond to a first word line, a second word line, a third word line and a fourth word line respectively; wherein the first pair of bit lines operatively couples the first memory unit and the second memory unit, and the second pair of bit lines operatively couples the third memory unit and the fourth memory unit; and The first pair of bit lines physically extends along a first lateral direction through the first portion of a substrate on which the first memory unit and the second memory unit are formed and terminates at the second portion of the substrate on which the third memory unit and the fourth memory unit are formed, and the second pair of bit lines physically extends along the first lateral direction through the first portion and the second portion.

2. The semiconductor device according to claim 1, wherein The first memory cell to the fourth memory cell are respectively formed based on a four-contact polysilicon pitch transistor structure.

3. The semiconductor device according to claim 1, wherein The first memory unit is adjacent to the second memory unit along a second transverse direction, the third memory unit is adjacent to the fourth memory unit along the second transverse direction, and the second transverse direction is perpendicular to the first transverse direction.

4. The semiconductor device according to claim 3, wherein: The first memory unit and the third memory unit are aligned along the first transverse direction but physically separated, and the second memory unit and the fourth memory unit are aligned along the first transverse direction and physically separated.

5. A semiconductor device, characterized in that: include: a first memory array including a plurality of first memory cells formed on a first portion of a substrate; a second memory array comprising a plurality of second memory cells formed on a second portion of the substrate, wherein the second portion is physically separated from the first portion along a first lateral direction; a first pair of bit lines physically extending through the first portion and terminating at the second portion; as well as A second pair of bit lines physically extends through the first portion and the second portion.

6. The semiconductor device according to claim 5, wherein: The first pair of bit lines is only operatively coupled to the first plurality of memory cells, and the second pair of bit lines is only operatively coupled to the second plurality of memory cells.

7. The semiconductor device according to claim 5, wherein: wherein the first pair of bit lines is formed in a first of a plurality of metallization layers disposed on the substrate, and each of the second pair of bit lines has: a first portion formed in the first one, and A second portion is formed in a second one of the plurality of metallization layers.

8. The semiconductor device according to claim 5, wherein: wherein the first pair of bit lines is formed in a first of a plurality of metallization layers disposed on the substrate, and each of the second pair of bit lines has: a first portion formed in the first one, a second portion formed in a second one of the plurality of metallization layers, and A third portion is formed in a third one of the plurality of metallization layers.

9. A semiconductor device, characterized in that: include: A first memory unit and a second memory unit are arranged on a first portion of a substrate; a third memory cell and a fourth memory cell arranged on a second portion of the substrate, the first portion and the second portion being separated along a first lateral direction, wherein each of the first to fourth memory cells comprises a plurality of transistors formed based on a four-contact polysilicon pitch architecture; A first word line and a second word line, connecting the first memory unit and the second memory unit respectively; a third word line and a fourth word line, respectively connecting the third memory unit and the fourth memory unit; a first pair of bit lines connecting the first memory unit and the second memory unit; and a second pair of bit lines connecting the third memory unit and the fourth memory unit; The first pair of bit lines physically extends through the first portion along the first lateral direction and terminates at the second portion, and the second pair of bit lines physically extends through the first portion and the second portion along the first lateral direction.

10. The semiconductor device according to claim 9, wherein: The first memory unit and the second memory unit are physically adjacent to each other along a second lateral direction, the second lateral direction is perpendicular to the first lateral direction, and the third memory unit and the fourth memory unit are physically adjacent to each other along the second lateral direction.

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