ESD protection circuit

Abstract

According to the ESD protection circuit provided by the utility model, the state switching circuit is arranged at the input end, and whether a core circuit is in a power-on state or not is judged by detecting the output voltage of the power management circuit in the chip, namely whether voltage exists at the second signal end VDD or not. The ESD detection circuit is controlled through the output voltage of the state switching circuit, so that the ESD detection circuit does not work after a chip is powered on, and the false triggering problem of the ESD control circuit is eliminated from the source; when the core circuit is in a non-power-on state, the detection circuit detects the second signal end, if a transient change second signal, namely an ESD signal, is detected, a control signal is output and transmitted to the first control circuit through the voltage following circuit, and an input signal of the first control circuit changes along with an input signal of the voltage following circuit. The first control circuit is started to form an ESD discharge path with the voltage follower circuit, a channel of a key device of the core circuit is controlled to be closed, and meanwhile, a first signal end is closed to protect the core circuit, so that the anti-ESD capability of the core circuit is enhanced.

Description

Technical Field

[0001] The utility model relates to the field of integrated circuit protection, in particular to an ESD protection circuit. Background Art

[0002] Static electricity is everywhere in our daily life, from small sparks on winter sweaters to lightning. There are many anti-static measures in daily life, such as installing grounding chains on large trucks and wearing anti-static clothing. In chips, it is also necessary to provide the chip with a good anti-static ability to ensure that the chip has excellent resistance to static electricity in various situations such as transfer, welding, and testing, so as to improve the reliability of the chip.

[0003] For ESD protection design of chips, an ESD protection network (RC-BigFET) is usually designed on each pin of the core circuit, such as Figure 1 As shown, it takes advantage of the low trigger voltage and high response speed of RC-BigFET to make the ESD network form a low resistance path to discharge the ESD current and reduce the ESD stress of the core circuit under ESD events. However, in practical applications, due to the parasitic effects of the components of the core circuit, especially MOS devices, it is easy to couple the Gate potential through the parasitic capacitance Cgd / Cgs of MOS under ESD events, thereby opening the channel of MOS, making the impedance of the main chip much smaller than the impedance on the ESD network. At this time, the voltage on the pin is high, which may generate a large amount of current. The high power causes the chip to heat up rapidly, and there is a risk of burning. In addition, the area utilization rate of RC-BIGFET is low, which cannot meet the miniaturization trend of integrated circuits. Utility Model Content

[0004] In order to overcome the deficiencies of the prior art, the utility model provides an ESD protection circuit. Under an ESD event, the device channel of the core circuit is closed by the ESD control circuit, thereby improving the ESD resistance of the core circuit; and by setting a state switching circuit to ensure that the detection circuit is closed when the core circuit is powered on, thereby solving the problem of the core circuit crashing due to false triggering of the detection circuit when the core circuit is powered on.

[0005] In order to achieve the above object, the utility model provides an ESD protection circuit, including: a state switching circuit and an ESD control circuit;

[0006] A state switching circuit, wherein the input end is connected to the first signal end, and the output end is connected to the ESD control circuit;

[0007] The ESD control circuit has an input end connected to the second end and the state switching circuit, and an output end connected to the core circuit; the ESD control circuit includes a detection circuit, a voltage follower circuit and a first control circuit which are electrically connected in sequence.

[0008] Preferably, the states switched by the state switching circuit include: normal state and ESD protection state; in the normal state, the core circuit works normally and the ESD control circuit is turned off; in the ESD protection state, the detection circuit detects whether there is a transient change in the signal at the second signal end, determines whether an ESD event occurs, and controls whether the core circuit is turned off.

[0009] Preferably, the state switching circuit includes a first pull-up resistor and a state switching switch connected in sequence, wherein the drain of the state switching switch is connected to the first signal terminal and to the signal output terminal through the first pull-up resistor, the gate is connected to the output terminal of the voltage follower circuit, and the source is grounded.

[0010] Preferably, when in the ESD protection state, if the detection circuit detects a second signal of transient change, the second signal is transmitted from the voltage follower circuit to the input end of the first control circuit, and the first control circuit and the voltage follower circuit are conductive to discharge the second signal and control the core circuit to shut down; the first signal is the output voltage of the power supply inside the core circuit.

[0011] The utility model also provides an ESD protection circuit, comprising: a delay circuit and an ESD control circuit;

[0012] A delay circuit connected between the second signal terminal and the ESD control circuit;

[0013] The ESD control circuit is connected between the delay circuit and the core circuit. The ESD control circuit comprises a detection circuit, a voltage follower circuit and a first control circuit which are connected in sequence.

[0014] Preferably, the ESD control circuit further includes a closed circuit, which includes a first closed switch and a second closed switch, wherein the first closed switch is connected between the input terminal of the voltage follower circuit and ground, and the second closed switch is connected between the input terminal of the first control circuit and ground.

[0015] Preferably, the voltage follower circuit includes a follower switch, and the first control circuit includes a first control switch, the drain of the follower switch is connected to the second signal terminal, the gate is connected to the output terminal of the detection circuit, and the source is grounded through a follower resistor; the drain of the first control switch is connected to the control terminal of the core circuit, the gate is connected between the source of the follower switch and the follower resistor, and the source is grounded.

[0016] Preferably, if the detection circuit detects a second signal with a transient change, the second signal is transmitted from the voltage follower circuit to the input end of the first control circuit. During the delay time, the first control circuit and the voltage follower circuit are turned on to discharge the second signal, and the control core circuit is turned off; the second signal end signal is provided by an external power supply.

[0017] Preferably, the ESD protection circuit also includes a second control circuit, the core circuit includes an N-type transistor and a P-type transistor, the first control circuit controls the N-type transistor, and the second control circuit is connected between the output end of the voltage follower circuit and the control end of the P-type transistor.

[0018] Preferably, the second control circuit includes a second control switch, a third control switch and a second pull-up resistor; the gate of the second control switch is connected to the output end of the voltage follower circuit, its drain is connected to the second signal end through the second pull-up resistor, and its source is grounded; the gate of the third control switch is connected between the drain of the second control switch and the resistor, its drain is connected to the second signal end, and its source is connected to the control end of the P-type transistor.

[0019] The utility model provides an ESD protection circuit, which has the beneficial effect that the utility model sets a state switching circuit at the input end, and determines whether the core circuit is in the power-on state by detecting the output voltage Vout of the power management circuit inside the chip, that is, whether there is voltage at the second signal end VDD. The ESD detection circuit is controlled by the output voltage Voff of the state switching, so that the ESD detection circuit does not work after the chip is powered on, thereby eliminating the false triggering problem of the ESD control circuit from the source; when the state switching circuit detects that the chip is in the power-off state through Vout, the detection circuit detects the second signal end, and if a transient second signal, i.e., an ESD signal, is detected, the output control signal is transmitted to the first control circuit through the voltage follower circuit, and the input signal of the first control circuit follows the input signal change of the voltage follower circuit, and the first control circuit starts to form an ESD discharge path with the voltage follower circuit to control the channel closure of the key components of the core circuit; at the same time, the first signal end Vout is closed to protect the power output end inside the core circuit and the core circuit under the output voltage, thereby enhancing the anti-ESD capability of the core circuit.

[0020] After the utility model successfully solves the ESD event risk and false triggering problems, the chip can further optimize the first-level ESD protection design, such as selecting a RC-SCR circuit with a small area, strong current capability, and good robustness as a protection unit. This protection device can solve the false triggering and latching problems that may be caused by RC-SCR under normal working conditions. The use of RC-SCR can significantly reduce the occupied area of ​​the protection device and effectively reduce the manufacturing cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is prior art;

[0022] Figure 2 A circuit schematic diagram of Example 1 of an ESD protection circuit provided by the utility model;

[0023] Figure 3A power supply schematic diagram of Example 2 of an ESD protection circuit provided by the utility model;

[0024] Figure 4 A circuit schematic diagram of Example 3 of an ESD protection circuit provided by the utility model;

[0025] Figure 5 A circuit schematic diagram of Example 4 of an ESD protection circuit provided by the utility model; DETAILED DESCRIPTION

[0026] The following describes the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0027] Example 1

[0028] like Figure 2 As shown, the utility model provides an ESD protection circuit, which includes: a state switching circuit and an ESD control circuit. The input end of the state switching circuit is connected to the first signal end, and the output end is connected to the ESD control circuit. The input end receives the first signal to determine whether to switch the state to perform ESD protection on the core circuit, and in the ESD protection state, the ESD event temporarily protects the first signal end, and the output end controls the working state of the ESD protection circuit. The ESD control circuit is connected between the state switching circuit and the core circuit, and the ESD control circuit includes a detection circuit, a voltage following circuit and a first control circuit connected in sequence; when in the ESD protection state, if the detection circuit detects a second signal of transient change, the second signal is transmitted from the voltage following circuit to the input end of the first control circuit, and the input signal of the first control circuit follows the input signal change of the voltage following circuit. The first control circuit forms an ESD discharge path through the signal following and the voltage following circuit to control the core circuit to be closed.

[0029] In order to solve the problem of channel opening of core circuit devices caused by ESD events, an ESD control circuit is set up. When the core circuit is not powered on, when the detection circuit detects the second signal of transient change, that is, when the ESD event is detected, the second signal is output to the voltage follower circuit, which is transmitted to the first control circuit by the voltage follower circuit, and the input voltage of the first control circuit will change with the input voltage of the voltage follower circuit, and then the voltage follower circuit and the first control circuit form an ESD discharge path. The second signal, that is, the ESD signal, is discharged to the ground through the ESD discharge path, so that the control end of the core circuit is connected to GND and is not affected by the pin voltage coupling. When the core circuit is powered on, the detection circuit may respond to the non-ESD signal at the second signal end, and the ESD control circuit is triggered by mistake, causing the core circuit to suddenly shut down during operation; in order to overcome the problem of false triggering of the detection circuit, a state switching circuit is set up. The state switching circuit determines whether the core circuit is in the power-on state by detecting the first signal, and controls the ESD control circuit through the output voltage Voff of the state switching circuit, so that the ESD control circuit does not work after the chip is powered on, thereby eliminating the false triggering problem of the ESD control circuit from the source.

[0030] In this embodiment, the states switched by the state switching circuit include: normal state and ESD protection state; in the normal state, that is, when the core circuit works normally, the ESD control circuit is turned off; in the ESD protection state, the detection circuit detects whether there is a transient change in the signal at the second signal end, determines whether an ESD event occurs, and controls whether the core circuit is turned off.

[0031] It should be noted that, under normal conditions, the signal at the second signal terminal can be any signal except the second signal (ESD signal). The second signal is generated after a transient change occurs to the signal at the second signal terminal. When the second signal is generated, the ESD control circuit works.

[0032] The first signal input by the state switching module is the output voltage of the power management circuit inside the core circuit. The output voltage Vout of the power management circuit inside the chip is detected to determine whether the core circuit is in the power-on state, that is, whether there is a voltage at the second signal terminal VDD. The ESD control circuit is controlled by the output voltage Voff of the state switching, so that the ESD control circuit does not work after the chip is powered on. Among them, the state switching circuit includes a first pull-up resistor R1 and a state switching switch MN1 connected in sequence, the drain of the state switching switch MN1 is connected to the first signal terminal and the signal output terminal (output voltage Voff) through the first pull-up resistor R1, its gate is connected to the output terminal of the voltage follower circuit (V_CTL, which is also the input terminal of the first control circuit), and its source is grounded.

[0033] Specifically, when the first signal Vout input by the state switching module, that is, the output voltage of the power supply inside the core circuit is at a high level, that is, when the core circuit is working normally, the state switching switch MN1 is in a closed state, and the first pull-up resistor R1 connected to the drain pulls up the voltage of the state switching circuit, and the signal output terminal Voff of the state switching circuit is at a high level; at this time, the ESD control circuit is in a closed state, and the state of the state switching circuit is in a normal state. This method avoids the signal fluctuation during normal operation causing the detection circuit to be falsely triggered and affect the normal operation of the core circuit. When the first signal Vout input by the state switching module is at a low level, that is, the chip is in a power-off state, the detection circuit detects the state of the second signal terminal VDD. When an ESD event occurs, the voltage signal of the second signal terminal VDD is an ESD signal that changes from a low level to a high level instantaneously. At this time, the input voltage of the voltage follower circuit, that is, the output voltage of the detection circuit, is also at a high level. The voltage follower circuit is turned on and outputs the high level to the first control circuit. The input voltage of the first control circuit follows the input voltage of the voltage control circuit to be at a high level. Since the gate voltage of the state switching switch MN1 and the output voltage V_CTL of the voltage follower circuit are both at a high potential, the state switching switch MN1 is turned on and controls the first signal Vout of the first signal terminal to be at a low level, protecting the internal power supply of the core circuit and other core circuits under the internal power supply. The input terminal of the first control circuit receives a high level and turns on. The voltage follower circuit and the first control circuit form a discharge path to discharge the ESD signal and shut down the core circuit, thereby realizing ESD protection for the core circuit.

[0034] In the state switching module, the resistance of the first pull-up resistor R1 is about 1K to 10M, and its specific resistance is determined by the magnitude of the internal power supply output voltage and the size of the series state switching switch MN1 to achieve its function.

[0035] In this embodiment, the ESD control circuit also includes a closed circuit for controlling the working state of the ESD control circuit itself, which includes a first closed switch MN2 and a second closed switch MN4, the first closed switch MN2 is connected between the input end of the voltage follower circuit and the ground, and the second closed switch MN4 is connected between the input end of the first control circuit and the ground. Specifically, the gate voltage of the first closed switch MN2 and the second closed switch MN4 is at the same potential as the output end voltage Voff of the state switching module; when the ESD control circuit needs to be closed, that is, the first signal Vout is at a high level, and the output end voltage Voff of the state switching circuit is at a high level, at this time, the first closed switch MN2 and the second closed switch MN4 are turned on, the first closed switch MN2 pulls the input signal of the voltage follower circuit to the ground GND, and the second closed switch MN4 pulls the input signal of the first control circuit to the ground GND, thereby realizing the ESD control circuit and changing its working state.

[0036] In this embodiment, the voltage follower circuit includes a follower switch MN3, and the first control circuit includes a first control switch MN5. The drain of the follower switch MN3 is connected to the second signal terminal VDD, the gate thereof is connected to the output terminal of the detection circuit, and the source thereof is grounded through the follower resistor R3; the drain of the first control switch MN5 is connected to the control terminal of the core circuit MN, the gate thereof is connected between the source of the follower switch MN3 and the follower resistor R3, and the source thereof is grounded. Specifically, the detection circuit includes a detection capacitor C1 and a detection resistor R2, which form an RC high-pass filter device. The second signal terminal VDD is filtered by the detection capacitor C1 and then divided by the detection resistor R2, and enters the gate of the follower switch MN3. The follower switch MN3 is turned on after receiving a high level, and then outputs a voltage V_CTL with the same high potential through the source. In order to completely discharge the ESD signal, the first control switch MN5 is set at the output terminal of the voltage follower circuit. When an ESD event occurs, the first control switch MN5 is turned on to form an ESD discharge path to ensure that the core circuit is closed, thereby protecting the core circuit.

[0037] It should be noted that the positions of the detection capacitor C1 and the detection resistor R2 in the detection circuit can be swapped, and the specific position is determined by the connected voltage follower circuit. If the follower switch input terminal of the connected voltage follower circuit is the gate of NMOS, the detection circuit with the detection capacitor on the side of the second signal terminal VDD is selected; if the gate connected is PMOS, the detection circuit with the detection capacitor on the GND side is selected. Among them, the detection capacitor can be a MOS capacitor or other capacitors such as a metal capacitor. The appropriate capacitor type is selected according to the voltage of the second signal terminal VDD (the breakdown voltage VBD of the capacitor needs to be greater than the maximum voltage of the input terminal VDD). The reference resistance of the detection resistor is about 1K~10M, and it is adjusted according to the product of capacitance*resistance.

[0038] The follower switch NM3 in the voltage follower circuit is an N-type MOS, which is a device with a suitable withstand voltage selected according to the maximum voltage of the second signal terminal VDD. The follower resistor R3 connected to the source of the N-type MOS has a resistance value of 1K to 10M. In order to make the follower switch MN3 work normally, the specific resistance value needs to be determined according to the size of the follower switch MN3. When the size of the follower switch MN3 is large, the follower resistor R3 resistance value required is small, and when the size of the follower switch MN3 is small, the resistance value required is large. The voltage follower switch MN3 can also be changed to a PMOS connected in series with the follower resistor R3, the drain of the PMOS is connected to GND, and the source and the follower resistor R3 are connected in series at the output node of the voltage follower circuit. The voltage follower circuit can also be changed to a voltage amplifier circuit, and the function is realized by an NMOS / PMOS common source amplifier.

[0039] In the utility model, the signal at the second signal end is provided by an external power supply. When the external power supply is at a high level, the first signal is at a high level, the core circuit works normally, and the protection circuit is in a closed state; when the external power supply is at a low level, the first signal is at a low level, and the protection circuit is in an ESD protection state. In the current state, if the detection circuit detects that the second signal undergoes a transient change, the core circuit is shut down by controlling the voltage follower circuit and the first control circuit.

[0040] Specifically, when the external power supply is at a high level, that is, the signal at the second signal terminal is at a high level (that is, the second signal is at a high level), the first signal terminal is at a high level, the core circuit output voltage Vout is at a high potential, the core circuit works normally, and the protection circuit is in a closed state. When the external power supply is at a low level, that is, the signal at the second signal terminal (not the second signal) is at a low level, the first signal at the first signal terminal is at a low level, the protection circuit is in an ESD protection state, the core circuit output voltage Vout is at a low potential, and the core circuit is in an unpowered and unworked state at this time, and no ESD event occurs; if the detection circuit detects a transient change in the signal at the second signal terminal at this time, that is, an ESD event is detected, the second signal is released to shut down the core circuit.

[0041] Example 2

[0042] The working principle of this embodiment is basically the same as that of Embodiment 1, except that the state switching circuit in Embodiment 1 is replaced by a delay circuit, and the working voltage of the delay circuit is changed from being controlled by the first signal terminal to being controlled by the second signal terminal, and the working state of the ESD control circuit is controlled by detecting the external power supply.

[0043] like Figure 3 As shown, an ESD protection provided by this embodiment includes: a delay circuit and an ESD protection circuit. The delay circuit is connected between the second signal terminal and the ESD control circuit. The received second signal is delayed, and a delayed signal is output to the ESD control circuit. The ESD control circuit is connected between the delay circuit and the core circuit, and the ESD control circuit includes a detection circuit, a voltage following circuit and a first control circuit connected in sequence. If the detection circuit detects a second signal of transient change, the second signal is transmitted from the voltage following circuit to the input end of the first control circuit, and the input signal of the first control circuit follows the input signal change of the voltage following circuit. During the delay time, the first control circuit forms an ESD discharge path through the signal following and the voltage following circuit to control the core circuit to be closed.

[0044] This embodiment is designed for a chip that does not contain an internal power management circuit. There is no internal working power output voltage to determine whether the core circuit is normal. Therefore, a delay circuit is used to replace the state switching device, and the core circuit is detected by detecting the external power supply (second signal terminal) to detect whether the core circuit is working normally, thereby determining whether the ESD control circuit is started or shut down. When the voltage at the second signal terminal is at a high level, the control signal is delayed for a certain period of time through the delay circuit, and the delay time of the delay circuit is greater than the duration of the ESD signal. When performing ESD protection, the delay circuit can ensure that the ESD control circuit is not turned off during the delay time, ensuring that the ESD control circuit can completely discharge the ESD signal. During normal operation, ensure that the detection circuit is turned off after the core circuit to avoid false triggering, thereby realizing the ESD protection function for chips without internal power management circuits.

[0045] In the delay circuit, the delay time is about 150ns to 100us. The delay time must be longer than the longest duration of the ESD waveform and shorter than the chip power-on time. The specific delay time should be determined by the duration of the ESD event and the chip power-on time.

[0046] Example 3

[0047] like Figure 4 As shown, this embodiment is an extension of Embodiment 1, and a first-level control circuit, namely, a second control circuit, is added on the basis of Embodiment 1. In Embodiments 1 and 2, the core circuit includes only N-type transistors, and the first control circuit controls whether the core circuit is turned off by controlling the on and off of the N-type transistor MN, while the core circuit in Embodiment 3 includes N-type transistors and P-type transistors, and the first control circuit is used to control the on and off of the N-type transistor MN, and the second control circuit is used to control the on and off of the P-type transistor MP; when an ESD event occurs, the first control circuit and the second control circuit operate simultaneously, so that the P-type switch MP is also in a closed state when the chip is not working properly and in an ESD event, further enhancing the ESD protection capability of the core circuit.

[0048] In this embodiment, the second control circuit is connected between the output end of the voltage follower circuit and the control end of the P-type transistor MP, and the second control circuit controls the P-type transistor to be turned off according to the output signal of the voltage follower circuit. The second control circuit includes a second control switch NM6, a third control switch MP1, and a second pull-up resistor R4; the gate of the second control switch MN6 is connected to the output end of the voltage follower circuit, the drain thereof is connected to the second signal end through the second pull-up resistor R4, and the source thereof is grounded; the gate of the third control switch MP1 is connected between the drain of the second control switch MN6 and the resistor, the drain thereof is connected to the second signal end, and the source thereof is connected to the control end of the P-type transistor MP.

[0049] When the core circuit works normally, that is, when the power supply voltage is high, the working states of the state switching circuit, the detection circuit, and the voltage follower circuit are the same as those in Example 1. The core circuit works normally, and the output voltage V_CTL of the voltage follower circuit is pulled down to GND by the second closed switch MN4 transistor. Then, the input voltage of the two-stage control circuit is low, the first control switch MN5 and the second control switch MN6 are closed, and the gate voltage Ngate of the N-type switch MN of the core circuit is not controlled by the first control switch MN5, and the V_CTL_p node voltage is high, the third control switch MP1 is closed, and the gate voltage Pgate of the P-type switch MP of the core circuit is not controlled by the third control switch MP1. At the same time, when the core circuit works normally, the control of the core circuit is completely released, eliminating false triggering.

[0050] When the core circuit is not working properly, the first closed switch MN2 and the second closed switch MN4 disconnect the control of the voltage follower circuit and the control circuit (the first control circuit and the second control circuit). At this time, if an ESD event occurs, the state switching circuit, the detection circuit, and the voltage follower circuit will respond to the ESD event in the same manner as the chip in the abnormal working state described in Example 1, and at the same time, the voltage of the first control circuit, the second control circuit, and the state switching circuit will be pulled up to a high level following the voltage V_CTL of the output terminal of the voltage follower circuit. For the first control circuit and the state switching circuit, the working state of the two will be consistent with the response ESD event performance of the chip in the abnormal working state in Example 1. For the second control circuit, the high-level input terminal voltage V_CTL turns on the second control switch MN6, resulting in a current passing through the second pull-up resistor R4 connected in series with it. The current causes the V_CTL_p node voltage (the gate voltage of the third control switch) to drop, turns on the third control switch MP1, and pulls up the gate Pgate node voltage of the P-type transistor MP of the core circuit to the second signal terminal voltage VDD, thereby realizing the closure of the core circuit PMOS.

[0051] In this embodiment, through the control of the second control circuit, comprehensive ESD protection is simultaneously implemented for the core circuit N-type transistor MN, the P-type transistor MP and the output voltage Vout of the power management circuit inside the chip.

[0052] Example 4

[0053] like Figure 5As shown, this embodiment is an extension of Embodiment 2 and is the same as Embodiment 3. This embodiment adds a second control circuit on the basis of the circuit structure of Embodiment 2. Its structure is the same as the second control circuit in Embodiment 3 and its working principle is also the same; the difference is that the second control circuit and the first control circuit are turned on within the delay time specified by the delay circuit, and the P-type transistors and N-type transistors in the core circuit are turned off to ensure that the generated ESD signal can be completely discharged, thereby improving the ESD protection capability of the core circuit.

[0054] In the present invention, the first control switch MN5 and the second control switch NM6 can be replaced by PMOS tubes to complete the work. If the second control switch MN6 is a PMOS tube, the third control switch MP1 is an NMOS tube.

[0055] Obviously, the described embodiments are only some embodiments of the utility model, not all embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

Claims

1. An ESD protection circuit, characterized in that: include: State switching circuit and ESD control circuit; A state switching circuit, wherein the input end is connected to the first signal end, and the output end is connected to the ESD control circuit; The ESD control circuit has an input end connected to the second end and the state switching circuit, and an output end connected to the core circuit; the ESD control circuit includes a detection circuit, a voltage follower circuit and a first control circuit which are electrically connected in sequence.

2. The ESD protection circuit according to claim 1, characterized in that: The states switched by the state switching circuit include: normal state and ESD protection state; in the normal state, the core circuit works normally and the ESD control circuit is turned off; in the ESD protection state, the detection circuit detects whether there is a transient change in the signal at the second signal end, determines whether an ESD event occurs, and controls whether the core circuit is turned off.

3. The ESD protection circuit according to claim 2, characterized in that: The state switching circuit includes a first pull-up resistor and a state switching switch connected in sequence, the drain of the state switching switch is connected to the first signal end and the signal output end through the first pull-up resistor, the gate is connected to the output end of the voltage follower circuit, and the source is grounded.

4. The ESD protection circuit according to claim 1, characterized in that: When in the ESD protection state, if the detection circuit detects a second signal with transient changes, the second signal is transmitted from the voltage follower circuit to the input end of the first control circuit, and the first control circuit and the voltage follower circuit are conductive to discharge the second signal and control the core circuit to shut down; the first signal is the output voltage of the power supply inside the core circuit.

5. An ESD protection circuit, characterized in that: include: Delay circuit and ESD control circuit; A delay circuit connected between the second signal terminal and the ESD control circuit; The ESD control circuit is connected between the delay circuit and the core circuit. The ESD control circuit comprises a detection circuit, a voltage follower circuit and a first control circuit which are connected in sequence.

6. The ESD protection circuit according to any one of claims 1 or 5, characterized in that: The ESD control circuit further includes a closed circuit, which includes a first closed switch and a second closed switch, wherein the first closed switch is connected between an input terminal of the voltage follower circuit and ground, and the second closed switch is connected between an input terminal of the first control circuit and ground.

7. The ESD protection circuit according to any one of claims 1 or 5, characterized in that: The voltage follower circuit includes a follower switch, and the first control circuit includes a first control switch, the drain of the follower switch is connected to the second signal terminal, the gate is connected to the output terminal of the detection circuit, and the source is grounded through a follower resistor; the drain of the first control switch is connected to the control terminal of the core circuit, the gate is connected between the source of the follower switch and the follower resistor, and the source is grounded.

8. The ESD protection circuit according to claim 7, characterized in that: If the detection circuit detects a second signal with a transient change, the second signal is transmitted from the voltage follower circuit to the input end of the first control circuit. During the delay time, the first control circuit and the voltage follower circuit are turned on to discharge the second signal, and the control core circuit is turned off. The second signal end signal is provided by an external power supply.

9. The ESD protection circuit according to any one of claims 1 or 5, characterized in that: The ESD protection circuit also includes a second control circuit, the core circuit includes an N-type transistor and a P-type transistor, the first control circuit controls the N-type transistor, and the second control circuit is connected between the output end of the voltage follower circuit and the control end of the P-type transistor.

10. The ESD protection circuit according to claim 9, characterized in that: The second control circuit includes a second control switch, a third control switch and a second pull-up resistor; the gate of the second control switch is connected to the output end of the voltage follower circuit, the drain thereof is connected to the second signal end through the second pull-up resistor, and the source thereof is grounded; the gate of the third control switch is connected between the drain of the second control switch and the resistor, the drain thereof is connected to the second signal end, and the source thereof is connected to the control end of the P-type transistor.

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