Memory device

Abstract

The utility model discloses a memory device comprising a memory array, wherein the memory array comprises a plurality of one-time programmable memory units. Each of the plurality of one-time programmable memory cells includes a select transistor, a diode, and a conductor fuse. The diode and the conductor fuse are connected in series, and the select transistor is coupled to a common node between the diode and the conductor fuse.

Description

Technical Field

[0001] The present disclosure relates to memory devices, and more particularly to one-time programmable memory devices. Background Art

[0002] The development of electronic devices such as computers, portable devices, smart phones, and Internet of Things (IoT) devices has led to an increased demand for memory devices. Generally speaking, memory devices can be volatile memory devices and non-volatile memory devices. Volatile memory devices can store data when power is supplied, but may lose the stored data once the power is turned off. Unlike volatile memory devices, non-volatile memory devices can retain data even after the power is turned off, but may be slower than volatile memory devices. Utility Model Content

[0003] According to some embodiments of the present disclosure, a memory device includes a first memory cell, wherein the first memory cell includes a first selection transistor, a first diode and a first conductor fuse, the first diode and the first conductor fuse are connected in series, and the first selection transistor is coupled to a first common node between the first diode and the first conductor fuse.

[0004] According to some embodiments of the present disclosure, a memory device includes a memory array, wherein the memory array includes a plurality of one-time programmable memory cells. Each of the one-time programmable memory cells includes a selection transistor, a diode, and a conductor fuse, wherein the diode and the conductor fuse are connected in series, and the selection transistor is coupled to a common node between the diode and the conductor fuse.

[0005] According to some embodiments of the present disclosure, a memory device includes a first one-time programmable memory cell and a second one-time programmable memory cell. The first one-time programmable memory cell includes a first selection transistor, a first diode, and a first conductor fuse, wherein the first diode and the first conductor fuse are connected in series, and the first selection transistor is coupled to a first common node between the first diode and the first conductor fuse. The first one-time programmable memory cell is configured to be programmed when the first diode is forward biased. The second one-time programmable memory cell includes a second selection transistor, a second diode, and a second conductor fuse, wherein the second diode and the second conductor fuse are connected in series, and the second selection transistor is coupled to a second common node between the second diode and the second conductor fuse. The second one-time programmable memory cell is configured not to be programmed when the second diode is reverse biased. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard methods in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of a memory device is shown according to some embodiments;

[0008] Figure 2 According to some embodiments Figure 1 Example configuration of an electronic fuse memory cell of a memory device;

[0009] Figure 3 According to some embodiments, a table is shown listing the operations Figure 2 Example signals of an electronic fuse memory cell;

[0010] Figure 4 and Figure 5 According to some embodiments, forming Figure 2 The layout of the electronic fuse memory cell;

[0011] Figure 6 According to some embodiments, Figures 4 to 5 A cross-sectional view of a semiconductor device formed by a layout;

[0012] Figure 7 According to some embodiments, a schematic diagram of a memory array is shown, wherein the memory array has a plurality of Figure 2 Electronic fuse memory cells;

[0013] Figure 8 According to some embodiments, the corresponding Figure 7 A perspective view of a semiconductor device of a portion of a memory array;

[0014] Fig. 9 and Fig.10 According to some embodiments, current distribution diagrams of a first memory array and a second memory array are respectively depicted;

[0015] Fig.11 Operations are depicted according to some embodiments Figure 7 A flow chart of an example method for storing a memory array.

[0016]

Explanation of symbols

[0017] 100:Memory device

[0018] 102:Memory Array

[0019] 103:Memory unit

[0020] 104: row decoder

[0021] 106: Column Decoder

[0022] 108: Input / output circuit

[0023] 110: Control logic circuit

[0024] 200: Electronic fuse memory unit

[0025] 202: Fuse resistor

[0026] 204: Select transistor

[0027] 206:Diode

[0028] 300:Table

[0029] 400:Part 1 / Layout

[0030] 402: Pattern / n well

[0031] 404: pattern / p + trap

[0032] 406: pattern / n + trap

[0033] 408A, 408B, 408C, 408D, 408E: Pattern / gate structure

[0034] 410A,410B,410C: Pattern / MD

[0035] 414: Pattern / Bit Line

[0036] 416: Pattern / character line

[0037] 418: Pattern / shunt line

[0038] 420: Pattern / MD

[0039] 500: Part 2 / Layout

[0040] 502: Pattern / Fuse Resistor

[0041] 504: Pattern / source line

[0042] 600: Device

[0043] 601:Substrate

[0044] 602:n well

[0045] 604:p + trap

[0046] 606:n + trap

[0047] 608: Gate structure

[0048] 700:Memory array

[0049] 700A, 700B, 700C, 700D: Electronic fuse memory unit

[0050] 800: Device

[0051] 900,1000: Current distribution diagram

[0052] 1100: Method

[0053] 1102,1104,1106: Steps

[0054] A-A',A'-A”: line

[0055] BL,BL m ,BL m+1 :Bit Line

[0056] CDD,CDD m ,CDD m+1 :Shunting line

[0057] C1,C2,C3,C N :List

[0058] D: Drain terminal

[0059] M1, M2, M3, M4, M5: metallization layer

[0060] N+:n + trap

[0061] R1, R2, R3, R M :OK

[0062] S: source extreme point

[0063] SL,SL n ,SL n+1 :Source Line

[0064] WL,WL n ,WL n+1 :Character Line

[0065] X,Y: Direction

[0066] Y': Node DETAILED DESCRIPTION

[0067] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0068] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0069] A one-time-programmable (OTP) memory device is a type of non-volatile memory device that is used in integrated circuits to adjust the circuits after the integrated circuits are manufactured. For example, OTP memory devices are used to provide repair information to control the use of redundant cells to replace defective cells of a memory array. Another use is to tune analog circuits by trimming the capacitance or resistance values ​​of analog circuits, or by enabling and disabling parts of the system. The trend now is that the same product can be prepared in different manufacturing plants with a common process technology. Despite the best engineering efforts, each plant still has slightly different processes. The use of OTP memory devices allows product functionality to be optimized independently for each manufacturing plant.

[0070] As integrated circuit technology advances, integrated circuit features (e.g., transistor size and dimensions) are reduced, allowing more circuits to be implemented in an integrated circuit. When implementing an OTP memory device such as a fuse, an electronic fuse (efuse), etc. in an integrated circuit, the OTP memory device can be configured as a one-transistor-one-resistor (1T1R) structure. Such a structure may encounter various challenges. For example, in order to successfully program (burn out or break) a resistor that serves as a fuse line of an OTP memory device, a very large programming current is usually required, and therefore the corresponding transistor is usually made of a relatively large size. This may cause significant difficulties in integrating these OTP memory devices when upgrading integrated circuits. Even if some other structures that have been proposed are adopted (e.g., one-transistor-two-resistor (1T2R)), such a 1T2R structure may still be affected by large interference currents, thereby ultimately limiting the overall size of the OTP memory device. As a result, existing OTP memory devices have not yet fully met many aspects.

[0071] The present disclosure provides multiple embodiments of an OTP memory device including multiple electronic fuse memory cells, wherein each electronic fuse memory cell is implemented as a one-transistor-one-resistor-one-diode (1T1R1D) structure. In multiple embodiments, the electronic fuse memory cell implemented as the disclosed 1T1R1D structure includes a conductor fuse (as a fuse resistor) and a diode connected in series with each other, and further includes a selection transistor connected to a common node (common node) between the conductor fuse and the diode. Since the diode is connected to the conductor fuse, an additional conductive path can be provided when the corresponding electronic fuse memory cell is selected for access (e.g., programming). In some embodiments, the diode can therefore be used as a current divider. Therefore, the selection transistor does not need to bear the entire amount of programming current, so that the selection transistor can become smaller (relative to the existing 1T1R structure). Furthermore, when the electronic fuse memory cell is not selected, the corresponding diode of the electronic fuse memory cell is reverse-biased, so that the interference current flowing through the unselected electronic fuse memory cell can be significantly suppressed. Therefore, the OTP memory device can have a relatively large number of electronic fuse memory cells configured in a 1T1R1D structure, and almost zero interference current across the entire OTP memory device.

[0072] According to various embodiments, Figure 1 An exemplary block diagram of a semiconductor (eg, memory) device 100 is shown. Figure 1 In the illustrated embodiment, the memory device 100 includes a memory array 102, a row decoder 104, a column decoder 106, an input / output (I / O) circuit 108, and a control logic circuit 110. Although not clearly shown in FIG. Figure 1 , the components of the memory device 100 may be operatively coupled to each other and to the control logic circuit 110. For example, in some embodiments, the control logic circuit 110, the input / output circuit 108, the column decoder 106, and the row decoder 104 may be operatively coupled (e.g., electrically) to the memory array 102. Figure 1 In the illustrated example, components are illustrated as separate blocks for clarity, but in some other embodiments, Figure 1 Some or all of the components shown in the drawings may be integrated together. For example, the memory array 102 may include embedded input / output circuits 108.

[0073] The memory array 102 is a hardware component for storing data. In one aspect, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or storage cells) 103. The memory array 102 includes a plurality of rows R1, R2, R3 to R4. M , each row extends along a first direction (eg, X direction), and a plurality of columns C1, C2, C3 to C N , each column extends along a second direction (e.g., the Y direction). Each of the rows and columns may include one or more conductive structures as access lines (e.g., word lines (WL), bit lines (BL), source lines (SL), etc.). In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and can be operated according to the voltage or current passing through the individual conductive structures of the columns and rows.

[0074] According to multiple embodiments of the present disclosure, each memory cell 103 is implemented as a one-time programmable memory cell, such as an electronic fuse memory cell. Further, the electronic fuse memory cell includes a fuse resistor, a selection transistor and a diode, and such a combination is sometimes referred to as a configuration of a transistor-a resistor-a diode structure. The selection transistor can be coupled to a word line (for example, controlled in a gate manner). The selection transistor can be turned on / off to enable / disable access (for example, programming, reading) to the corresponding fuse resistor. For example, when an electronic fuse memory cell is selected, the selection transistor of the selected electronic fuse memory cell is turned on to generate a first programming or reading path that conducts through the fuse resistor and the selection transistor itself. Further, when the electronic fuse memory cell is selected, since the diode is connected to the fuse resistor, a second programming or reading path that conducts through the fuse resistor and the diode can also be generated. Therefore, even if a relatively small-sized selection transistor is manufactured, the programming efficiency of the memory cell 103 will not be compromised. The following is about Figure 2 The content of the present invention will describe in detail the memory cell 103 configured as an electronic fuse memory cell (also referred to as the electronic fuse memory cell 103 herein).

[0075] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., a word line) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert one or more conductive structures (e.g., a bit line, a source line) at the column address. The input / output circuit 108 is a hardware component that can access (e.g., read, program) each memory cell 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 110 is a hardware component that can control the coupling components (e.g., the memory array 102 to the input / output circuit 108).

[0076] According to some embodiments, Figure 2 An electronic fuse memory cell 200 (eg, Figure 1 An exemplary configuration of an electronic fuse memory cell 103) is provided, wherein a relatively small size electronic fuse memory cell 200 is formed with a convenient programming efficiency. Figure 2In the example of the electronic fuse memory cell 200, the electronic fuse memory cell 200 is configured as a transistor-resistor-diode structure. For example, the electronic fuse memory cell 200 includes a fuse resistor 202, a selection transistor 204, and a diode 206. The fuse resistor 202 is connected in series to the selection transistor 204, and the diode 206 is connected to a common node between the fuse resistor 202 and the selection transistor 204. However, it should be understood that the electronic fuse memory cell 200 can be used for any other fuse configuration that exhibits fuse characteristics and is also within the scope of the present disclosure.

[0077] In various embodiments of the present disclosure, the fuse resistor 202 has a first terminal connected to a source line, and a second terminal (denoted as node Y') connected to both the select transistor 204 and the diode 206. The select transistor 204 has a gate terminal connected to a word line, a first source / drain terminal connected to the node Y' (i.e., the second terminal of the fuse resistor 202), and a second source / drain terminal connected to the anode of the diode 206, and the cathode of the diode 206 is connected to a current-divider line (CDD). In other words, the fuse resistor 202 can be electrically conductive to the bit line and the current-divider line through the select transistor 204 and the diode 206, respectively.

[0078] The fuse resistor 202, the select transistor 204, and the diode 206 can be formed on the same side of the substrate, such as the front side of the semiconductor substrate. For example, the select transistor 204 and the diode 206 can be formed along the front side surface of the semiconductor substrate, which is sometimes referred to as part of the front-end-of-line (FEOL) process / network. A plurality of metallization layers are formed above the front-end process on the front side of the substrate, wherein each metallization layer includes a plurality of interconnect (e.g., metal) structures, which is sometimes referred to as part of the back-end-of-line (BEOL) process / network. The fuse resistor 202 can be formed by one or more metal structures of one of the metallization layers disposed above the select transistor 204.

[0079] Since the fuse resistor 202 is presented as a (front side) metal structure, the fuse resistor 202 can exhibit an initial resistance value (or resistivity) such as when manufactured. In order to program the electronic fuse memory cell 200 (e.g., by permanently switching the initial resistance value of the fuse resistor 202 to a relatively large resistance value), a signal (e.g., voltage) corresponding to a logic low state is applied via the bit line to turn on the select transistor 204 (if it is presented as a p-type transistor). At the same time or subsequently, a sufficiently high voltage signal (sometimes referred to as a programming voltage (Vprogram)) is applied to one of the endpoints of the fuse resistor 202 via the source line. With the select transistor 204 turned on, a first conductive (e.g., programming) path can be provided from the source line through the fuse resistor 202 and the turned-on select transistor 204 to the bit line. Further, by connecting the shunt line (i.e., the cathode of the diode 206) to ground, the diode 206 is forward-biased, thereby providing a second conductive (e.g., programming) path from the source line through the fuse resistor 202 and the diode 206 to the shunt line. As a result, the fuse resistor 202 can be changed from a first state (e.g., a short circuit) to a second state (e.g., an open circuit), causing the electronic fuse memory cell 200 to irreversibly change from a first logic state (e.g., logic 0) to a second logic state (e.g., logic 1). The logic state can be read by applying a relatively low voltage signal to the source line and turning on the select transistor 204 to provide a first conductive (e.g., read) path and a second conductive (e.g., read) path through the select transistor 204 and the diode 206, respectively.

[0080] According to some embodiments, Figure 3 A table 300 is shown summarizing example signals that may be applied to the word lines, bit lines, source lines, and shunt lines of each selected and unselected disclosed electronic fuse memory cell, respectively. The polarity of the signal corresponds to the conductivity type of the select transistor 204 (here implemented as a p-type transistor), so it should be noted that the polarity may be changed in other embodiments and is also within the scope of the present disclosure.

[0081] As shown in the figure, when the disclosed electronic fuse memory cell is selected for programming, the voltage signals applied to the word line, the bit line, the source line and the shunt line are respectively equal to "-VDD", "0", "programming voltage" and "0". Similarly, when the disclosed electronic fuse memory cell is selected for reading, the voltage signals applied to the word line, the bit line, the source line and the shunt line are respectively equal to "-VDD", "0", "reading voltage (Vread)" and "0". Therefore, the diode 206 of the selected electronic fuse memory cell is forward biased, so that part of the current can be distributed to flow through the corresponding fuse resistor 202. On the other hand, when the disclosed electronic fuse memory cell is not selected for programming, the voltage signals applied to the word line, the bit line, the source line and the shunt line are respectively equal to "VDD", "floating voltage (floating)", "floating voltage" and "floating voltage". Similarly, when the disclosed electronic fuse memory cell is not selected for reading, the voltage signals applied to the word line, the bit line, the source line, and the shunt line are equal to "VDD", "floating voltage", "floating voltage", and "floating voltage", respectively. Therefore, the diode 206 of the unselected electronic fuse memory cell is reverse biased, so that the current flowing through the corresponding fuse resistor 202 can be significantly suppressed.

[0082] According to some embodiments, Figure 4 and Figure 5 A first portion 400 and a second portion 500 of a layout for forming the disclosed electronic fuse memory cell (e.g., configured in a 1T1R1D structure) and corresponding access lines (e.g., bit line BL, word line WL, source line SL, shunt line CDD) are illustrated. Hereinafter, the first portion 400 and the second portion 500 are referred to as "layout 400" and "layout 500", respectively. Specifically, the layout 400 can be used in a front-end process (e.g., forming the select transistor 204 and the diode 206) and a portion of a back-end process (e.g., forming the word line, the bit line, and the shunt line), and the layout 500 can be used in a back-end process (e.g., forming the fuse resistor 202 and the source line).

[0083] Reference first Figure 4 , the layout 400 includes a plurality of layers for forming an n-well, a p-well, and a + Well and n + The patterns 402, 404, and 406 of the n-well are shown in FIG. + Well 404" and "n +The layout 400 further includes a plurality of patterns 408 (eg, pattern 408A, pattern 408B, pattern 408C, pattern 408D, and pattern 408E) for forming a plurality of gate structures, respectively. The pattern 408 extends along the Y direction across the n-well 402, the p-well 406, and the p-well 408. + Well 404 and n + Well 406. Hereinafter, patterns 408A to 408E are referred to as "gate structure 408A", "gate structure 408B", "gate structure 408C", "gate structure 408D" and "gate structure 408E", respectively.

[0084] n well 402 to n + Well 406 and gate structures 408A to 408E are usually formed in the front-end process. Such front-end process structures can form select transistor 204 and diode 206. For example, gate structures 408A to 408E and n-well 402, p-well 402, and n-gate structure 408A to 408E are formed in the front-end process. + Well 404 may form select transistor 204, and p + Well 404 and n + Well 406 (and the intersecting n-well 402) can form diode 206. Specifically, the portion of n-well 402 covered by each gate structure 408A to gate structure 408E can serve as a channel of a sub-transistor of select transistor 204, while the portion of p-well 402 on the opposite side of each gate structure 408A to gate structure 408E can serve as a channel of a sub-transistor of select transistor 204. + Well 404 can serve as the source and drain terminals of the corresponding sub-transistors. In some embodiments, select transistor 204 can actually be composed of multiple such sub-transistors coupled in parallel to another sub-transistor. Figure 4 As shown in , the drain terminal D and the source terminal S of the first sub-transistor are formed on the right and left sides of the gate structure 408A, respectively, the drain terminal D and the source terminal S of the second sub-transistor are formed on the left and right sides of the gate structure 408B, respectively, the drain terminal D and the source terminal S of the third sub-transistor are formed on the right and left sides of the gate structure 408C, respectively, and so on. + Well 404 can be used as the anode of diode 206, and n + Well 406 may serve as the cathode of diode 206 .

[0085] Continue to refer Figure 4, layout 400 includes pattern 410A, pattern 410B, and pattern 410C, respectively, for forming a plurality of middle-end interconnect structures. Such an interconnect structure is connected to the drain terminal of the sub-transistor (equivalent to the drain terminal of the selection transistor 204). Such a middle-end interconnect structure is sometimes referred to as the middle-end (MD). Hereinafter, pattern 410A, pattern 410B, and pattern 410C are respectively referred to as "MD410A", "MD410B", and "MD410C". These MD410A to MD410C electrically connect the drain terminal of the selection transistor 204 to the fuse resistor 202 (wherein the formation of the fuse resistor 202 can be used Figure 5 Similarly, the layout also includes a pattern (not shown) configured to form a plurality of mid-stage interconnect structures, wherein the mid-stage interconnect structures are respectively connected to the source terminals of the sub-transistors (equivalent to the source terminal of the selection transistor 204). Such a mid-stage interconnect structure enables the source terminal of the selection transistor 204 to be connected to the first back-end interconnect structure configured as a bit line.

[0086] The layout 400 includes a pattern 414 (hereinafter referred to as the bit line 414) for forming the bit line. The layout 400 further includes a pattern 416 (hereinafter referred to as the word line 416) for forming a second back-end interconnect structure configured as a word line, and a pattern 418 (hereinafter referred to as the shunt line 418) for forming a third back-end interconnect structure configured as a shunt line. Further, the word line 416 is electrically connected to the gate structure 408A to the gate structure 408E (equivalent to the gate terminal of the selection transistor 204), and the shunt line 418 is electrically connected to the n through a plurality of mid-stage interconnect structures (hereinafter referred to as MD420) formed based on the pattern 420. + Well 406 (equivalent to the cathode of diode 206).

[0087] refer to Figure 5 , the layout 500 includes a pattern 502 and a pattern 504 for forming a fourth back-end interconnect structure configured as a fuse resistor 202 and a fifth back-end interconnect structure configured as a source line, respectively. Hereinafter, the pattern 502 and the pattern 504 are respectively referred to as the fuse resistor 202 (or fuse resistor 502) and the source line 504. For reference, the patterns 410A to 410C, the pattern 414, the pattern 416, and the pattern 418 (or structures) of the layout 400 are also shown in FIG. Figure 5 In the layout 500 shown in FIG. 1 , MD410A to MD410C may be connected to the drain terminal of the select transistor 204 (ie, Figure 24. The bit line 414 may be connected to the source terminal of the select transistor 204. The word line 416 may be connected to the gate terminal of the select transistor 204. The shunt line 418 may be connected to the cathode of the diode 206. In some embodiments, the bit line 414, the word line 416, the shunt line 418, the fuse resistor 202 (or the fuse resistor 502), and the source line 504 may be formed across multiple back-end metallization layers, such as Figure 8 This is more clearly shown in the perspective view.

[0088] Figure 6 A cross-sectional view of a device 600 formed based on the layout 400 is shown. Figure 6 The cross-section is along Figure 4 The line AA" in FIG. 1 includes a first portion (line AA') extending along the X direction and a second portion (line A'-A") extending along the Y direction. Figure 6 As shown in FIG. 6 , the device 600 includes a (eg, p-type) substrate 601, an n-well 602 (corresponding to Figure 4 n well 402), multiple p + Well 604 (corresponding to Figure 4 p + Well 404), n + Well 606 (corresponding to Figure 4 n + Well 406), and gate structure 608 (corresponding to Figure 4 Therefore, the n-well 602, p-well + The well 604 and the gate structure 608 can serve as the channel, source and drain terminals, and gate terminal of the select transistor 204, respectively. + One of the wells 604 and n + The well 606 can serve as the anode and cathode of the diode 206 respectively.

[0089] According to some embodiments, Figure 7 A schematic diagram of a memory array 700 is shown, wherein the memory array 700 has a plurality of electronic fuse memory cells, such as an electronic fuse memory cell 700A, an electronic fuse memory cell 700B, an electronic fuse memory cell 700C, and an electronic fuse memory cell 700D. Each of the electronic fuse memory cells 700A to 700D can be implemented as the electronic fuse memory cell 200 (see FIG. 2 ). Figure 2 ), that is, it has a 1T1R1D structure. Figure 7 Although four electronic fuse memory cells are shown, it should be understood that the memory array 700 may include any number of electronic fuse memory cells and still be within the scope of the present disclosure.

[0090] As shown, the electronic fuse memory cells 700A to 700D are arranged in two columns (column [n] and column [n+1]) and two rows (row [m] and row [m+1]). In some embodiments, each column includes a separate word line WL and a separate source line SL, and each row includes a separate bit line BL and a separate shunt line CDD. Figure 7 For example, row [n] includes word line WL n and source line SL n , column [n] includes word line WL n+1 and source line SLn+1, row [m] includes bit line BL m and shunt line CDD m , row [m+1] includes bit line BL m+1 and shunt line CDD m+1 Each of the electronic fuse memory cells 700A to 700D is located at the intersection of a corresponding column and a corresponding row. Therefore, each of the electronic fuse memory cells 700A to 700D can actually be connected to a combination of a corresponding word line, a source line, a bit line, and a shunt line.

[0091] By implementing each of the electronic fuse memory cells 700A to 700D as a 1T1R1D structure, the interference current flowing through the unselected electronic fuse memory cells can be significantly suppressed. Figure 7 For example, by respectively n and word line WL n Applying a programming voltage (eg, about 0.94V) and -VDD (eg, about -0.9V), with the bit line BL set to 0V m and shunt line CDD m , and select the electronic fuse memory cell 700A for programming. n+1 , bit line BL m+1 and shunt line CDD m+1 The floating voltage is set, and the other electronic fuse memory cells 700B to 700D are not selected. Therefore, only the selected electronic fuse memory cell 700A can conduct a current of about 20 milliamperes (mA), while each of the unselected electronic fuse memory cells 700B to 700D can only conduct a current in the nanoampere (nA) range. This is because the diodes of each of the unselected electronic fuse memory cells 700B to 700D are reverse biased, thereby disconnecting almost all leakage paths that may be coupled to the selected electronic fuse memory cell 700A.

[0092] According to some embodiments, Figure 8 A perspective view of a device 800 corresponding to the memory array 700 is shown. As shown in the figure, the access lines (eg, the bit line BL, the shunt line CDD, the source line SL) can be respectively arranged in different metallization layers. m and bit line BL m+1 In the first metallization layer (eg, metallization layer M1), the shunt line CDD m and shunt line CDD m+1 In the second metallization layer (eg, metallization layer M2), the source line SL n and source line SL n+1 Disposed in the third metallization layer (eg, metallization layer M5). In some embodiments, the individual fuse resistors of the electronic fuse memory cells 700A to 700D may be disposed between the second metallization layer and the third metallization layer (eg, metallization layer M3).

[0093] According to some embodiments, Fig. 9 and Fig.10 The current distribution diagram 900 and the current distribution diagram 1000 of the first memory array and the second memory array are respectively depicted. Each of the first memory array and the second memory array may include a plurality of electronic fuse memory cells disclosed above (e.g., the electronic fuse memory cell 200). For example, the first memory array includes 8×8 electronic fuse memory cells, and the second memory array includes 16×16 electronic fuse memory cells. Even with such a large array size, the current peak only appears in the selected electronic fuse memory cells, while all unselected electronic fuse memory cells only show a current close to zero. In Fig. 9 In , only the selected cell located at the intersection of the fourth column and the fourth row exhibits a detectable current level (e.g., in the milliampere range). Fig.10 In the embodiment of the present invention, only the selected cell located at the intersection of the eighth column and the eighth row exhibits a detectable current level (e.g., in the milliampere range). This is because when one of the electronic fuse memory cells is selected, the corresponding diodes of other unselected electronic fuse memory cells are reverse biased. Therefore, the interference current flowing through the unselected electronic fuse memory cells can be significantly suppressed. In other words, the detectable current level can only appear in the selected electronic fuse memory cells of the memory array.

[0094] According to some embodiments, Fig.11A flow chart of a method 1100 for operating a memory device having a memory array is shown, wherein the memory array includes a plurality of electronic fuse memory cells disclosed above (e.g., electronic fuse memory cell 200). The method 1100 may be used to operate a memory array including a plurality of electronic fuse memory cells disclosed above, such as the memory array 700. It should be noted that the method 1100 is only an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 1100 may be used in any manner. Fig.11 Additional steps are provided before, during, and after method 1100, and only some of the other steps may be briefly described herein.

[0095] The method 1100 begins at step 1102 by providing a memory array including a plurality of electronic fuse memory cells. Each electronic fuse memory cell is implemented as a 1T1R1D structure, which includes a selection transistor (e.g., selection transistor 204), a fuse resistor (e.g., fuse resistor 202), and a diode (e.g., diode 206). The fuse resistor and the selection transistor are connected in series, and the diode is connected to a common node between the selection transistor and the fuse resistor. In other words, the fuse resistor and the diode are connected in series, and the selection transistor is connected to a common node between the diode and the fuse resistor.

[0096] Further, each electronic fuse memory cell is operatively coupled to a corresponding combination of source line SL, word line WL, bit line BL, and shunt line CDD. By applying appropriate signals to the corresponding source line SL, word line WL, bit line BL, and shunt line (e.g., according to Figure 3 300), one of the electronic fuse memory cells can be selected to be programmed with two conductive paths, while the interference current flowing through the remaining unselected electronic fuse memory cells can be significantly suppressed. Figure 2 Taking the electronic fuse memory cell 200 as a representative example, when the selection transistor 204 is turned on, a conductive path can be formed through the fuse resistor 202 (e.g., from the source line to the node Y'), and another conductive path can be formed through the diode 206 (e.g., further from the node Y' to the shunt line CDD).

[0097] In some embodiments, the method 1100 proceeds to step 1104 by selecting a first one of the electronic fuse cells for programming by forward biasing the diode of the first one of the electronic fuse cells. Figure 7 As an example, the memory array 700 is provided by applying programming voltages to the source lines SL n and -VDD to word line WL n , with the bit line BL m and shunt line CDD mThe voltage of the electronic fuse memory cell 700A is set to 0V, and the electronic fuse memory cell 700A is selected for programming. Therefore, the diode of the electronic fuse memory cell 700A is forward biased, and two conductive paths can be formed through the turned-on selection transistor and the forward biased diode, respectively. While step 1104 is being performed, the method 1100 also continues to step 1106, by applying a reverse bias to the diode of the second electronic fuse memory cell, so that the second electronic fuse memory cell is not selected for programming. Continue to refer to the above Figure 7 For example, by n+1 and shunt line CDD m+1 Set to floating voltage and apply VDD to word line WL n+1 , so that the electronic fuse memory unit 700B to the electronic fuse memory unit 700D are not selected for programming. Therefore, the diodes of each electronic fuse memory unit 700B to the electronic fuse memory unit 700D can be reverse biased. As a result, the interference current flowing through each unselected electronic fuse memory unit can be greatly reduced.

[0098] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a first memory cell, wherein the first memory cell includes a first selection transistor, a first diode, and a first conductor fuse. The first diode and the first conductor fuse are connected in series, and the first selection transistor is coupled to a first common node between the first diode and the first conductor fuse.

[0099] In some embodiments, the first memory cell is configured as a one-time programmable memory cell, wherein the first conductor fuse is configured to be permanently blown. In some embodiments, the memory device further includes a first word line coupled to the gate of the first selection transistor, a first source line coupled to the first end point of the first conductor fuse, a first bit line coupled to the first source / drain of the first selection transistor, and a first shunt line coupled to the first end point of the first diode. In some embodiments, the first selection transistor has a second source / drain coupled to the first common node. In some embodiments, the first conductor fuse has a second end point coupled to the first common node. In some embodiments, the first diode has a second end point coupled to the first common node. In some embodiments, when the first conductor fuse is programmed, the first selection transistor is turned on and the first diode is forward biased. In some embodiments, the first source line is configured to apply a programming voltage to the first conductor fuse through the first source line, and the first bit line and the first shunt line are coupled to a ground voltage. In some embodiments, the memory device further includes a second memory cell, wherein the second memory cell includes a second selection transistor, a second diode, and a second conductor fuse, the second diode and the second conductor fuse are connected in series, and the second selection transistor is coupled to a second common node between the second diode and the second conductor fuse. In some embodiments, the memory device further includes a second word line coupled to a gate of the second selection transistor, a second source line coupled to a first terminal of the second conductor fuse, a second bit line coupled to a first source / drain of the second selection transistor, and a second shunt line coupled to a first terminal of the second diode, wherein the second terminal of the second conductor fuse is coupled to the second common node, the second source / drain of the second selection transistor is coupled to the second common node, and the second terminal of the second diode is coupled to the second common node. In some embodiments, when the first conductor fuse is programmed, the second selection transistor is turned off and the second diode is reverse biased.

[0100] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory array, wherein the memory array includes a plurality of one-time programmable memory cells. Each of the plurality of one-time programmable memory cells includes a selection transistor, a diode, and a conductor fuse. The diode and the conductor fuse are connected in series, and the selection transistor is coupled to a common node between the diode and the conductor fuse.

[0101] In some embodiments, the conductor fuse of each of the one-time programmable memory cells is configured to be permanently blown. In some embodiments, the memory array includes a plurality of word lines, a plurality of source lines, a plurality of bit lines, and a plurality of shunt lines. In some embodiments, each of the one-time programmable memory cells operates to be coupled to a corresponding one of the word lines, a corresponding one of the source lines, a corresponding one of the bit lines, and a corresponding one of the shunt lines. In some embodiments, when a first one-time programmable memory cell in the one-time programmable memory cells is selected for programming, the diode of the first one-time programmable memory cell is forward biased. In some embodiments, when a second one-time programmable memory cell in the one-time programmable memory cells is not selected for programming, the diode of the second one-time programmable memory cell is reverse biased. In some embodiments, the current flowing through the unselected second one-time programmable memory cell is in the range of nanoamperes.

[0102] In yet another aspect of the present disclosure, a method for operating a memory device is disclosed. The method includes providing a memory array, wherein the memory array includes a plurality of one-time programmable memory cells, each of the plurality of one-time programmable memory cells including a selection transistor, a diode, and a conductor fuse. The method also includes selecting a first one-time programmable memory cell for programming by applying a forward bias to a diode of a first one-time programmable memory cell in the plurality of one-time programmable memory cells. The method also includes not selecting a second one-time programmable memory cell for programming by applying a reverse bias to a diode of a second one-time programmable memory cell in the plurality of one-time programmable memory cells.

[0103] In some embodiments, the conductive fuse of each of the one-time programmable memory cells is configured to be permanently blown.

[0104] In yet another aspect of the present disclosure, a memory device is disclosed. The memory device includes a first one-time programmable memory cell and a second one-time programmable memory cell. The first one-time programmable memory cell includes a first selection transistor, a first diode, and a first conductor fuse, wherein the first diode and the first conductor fuse are connected in series, and the first selection transistor is coupled to a first common node between the first diode and the first conductor fuse. The first one-time programmable memory cell is configured to be programmed when the first diode is forward biased. The second one-time programmable memory cell includes a second selection transistor, a second diode, and a second conductor fuse, wherein the second diode and the second conductor fuse are connected in series, and the second selection transistor is coupled to a second common node between the second diode and the second conductor fuse. The second one-time programmable memory cell is configured not to be programmed when the second diode is reverse biased.

[0105] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, about 0.5 may include 0.45 to 0.55, about 10 may include 9 to 11, and about 1000 may include 900 to 1100.

[0106] The features of some embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that: include: A first memory unit, comprising: a first selection transistor; a first diode; and a first conductor fuse; The first diode and the first conductor fuse are connected in series, and the first selection transistor is coupled to a first common node between the first diode and the first conductor fuse.

2. The memory device according to claim 1, wherein: The first memory cell is configured as a one-time programmable memory cell, and the first conductive fuse is configured to be permanently blown.

3. The memory device according to claim 1, wherein: Further including: a first word line coupled to a gate of the first selection transistor; a first source line coupled to a first end of the first conductor fuse; a first bit line coupled to a first source / drain of the first selection transistor; as well as A first shunt line is coupled to a first end of the first diode.

4. The memory device according to claim 3, wherein: The first selection transistor has a second source / drain coupled to the first common node.

5. The memory device according to claim 3, wherein: The first conductor fuse has a second terminal coupled to the first common node.

6. The memory device according to claim 3, wherein: The first diode has a second terminal coupled to the first common node.

7. The memory device according to claim 3, wherein: When the first conductor fuse is programmed, the first selection transistor is turned on and the first diode is forward biased.

8. The memory device according to claim 7, wherein: The first source line is configured to apply a programming voltage to the first conductor fuse through the first source line, and the first bit line and the first shunt line are coupled to a ground voltage.

9. A memory device, characterized in that: include: A memory array includes a plurality of one-time programmable memory cells, each of the plurality of one-time programmable memory cells comprising: a selection transistor; a diode; and a conductor fuse; The diode and the conductor fuse are connected in series, and the selection transistor is coupled to a common node between the diode and the conductor fuse.

10. A memory device, characterized in that: include: A first one-time programmable memory unit comprises: a first selection transistor; a first diode; and a first conductor fuse; wherein the first diode and the first conductor fuse are connected in series, and the first selection transistor is coupled to a first common node between the first diode and the first conductor fuse, wherein the first one-time programmable memory cell is configured to be programmed when the first diode is forward biased; and A second one-time programmable memory unit, comprising: a second selection transistor; a second diode; and a second conductor fuse; wherein the second diode and the second conductor fuse are connected in series, and the second selection transistor is coupled to a second common node between the second diode and the second conductor fuse, The second one-time programmable memory cell is configured to not be programmed when the second diode is reverse biased.

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