Power switching semiconductor device

Abstract

A power switch semiconductor device includes: a power switch semiconductor device die having three electrodes, namely a substrate electrode and two front electrodes; and a package having a substrate with an island to which the power switch semiconductor device die conductive die is attached with the backside electrode facing a top side of the package. The package has an insulating portion that encapsulates an electronically molded compound of the power switch semiconductor device die. There is at least one electrode passing through the insulating portion of the package to access the power switch semiconductor device die, and a conductive path through the hole connects the at least one electrode of the power switch semiconductor device die. Comprising the one or more electrodes of the power switch semiconductor device die to respective pin output connection ports on the bottom side of the package.

Description

Technical Field

[0001] The utility model relates to a power switch semiconductor device or module. Background Art

[0002] Discrete power switching semiconductor device products are usually packaged by attaching the conductive die of the power switching semiconductor device die substrate (back side) to the die pad (metal island) on the metal lead frame structure, which is connected to the pin-out connection port of the package corresponding to the substrate of the power switching semiconductor device die in the metal lead frame. The other two electrodes on the other (front) side of the power switching semiconductor device die are connected to the other two corresponding pin-out ports in the metal lead frame by wire, foil or clip bonding, where all three pin-out connection ports are short-circuited by the metal lead frame due to the mechanical strength requirements of the structure. After the bonding process, the molding of the electronic molding compound (EMC) is performed to form an insulating body, and then the multiple packaged units are divided into individual units, and if necessary, the metal pins of the pin-out connection ports are trimmed and shaped, and finally tested.

[0003] The difference in coefficient of thermal expansion (CTE) between the metal bonding wire and the EMC insulating package body is a major consideration for packaging process reliability. Thermal cycling will occur during the operating life of the packaged power switch semiconductor device due to the temperature rise that occurs during actual application operation, as well as cooling after power failure. Due to thermal cycling and the CTE difference between the metal and the CTE insulating body, mechanical stress will be generated between the bonding wire and the plastic package body during daily operation.

[0004] Various packaging designs of power switch semiconductor devices usually make the substrate side of the power switch semiconductor device tube core downward, so that the pin output port of the substrate electrode of the power switch semiconductor device tube core will be located on the same plane as the other two pin output connection ports. Therefore, the heat generated during the operation of the power switch semiconductor device packaged in this way needs to pass through the body of the package, or reach the periphery of the metal substrate over a long distance, and then the heat can be conducted to the environment or air. Therefore, the thermal resistance of the package increases. Figure 1 is a single MOSFET in a TOLL-type package that illustrates the concepts discussed. Figure 1 In FIG. 1 , the substrate (back side) 101 is connected to the die substrate by conductive die attach, while the other two contacts 102 and 103 are connected to the front side electrodes of the power semiconductor die by wire, foil or clip bonding.

[0005] In practical applications, the thermal resistance of the package is the limiting factor in limiting the maximum power dissipation that can be addressed by the same power switching semiconductor device die. For the same power switching semiconductor die, a packaging method that reduces the thermal resistance is always preferred because it means increasing the maximum power handling capability in practical applications.

[0006] In addition, short circuits of the pin-out connection ports of the packaged power switch semiconductor devices during packaging hinder the concurrent testing of multiple units before the multiple packaged devices are separated into individual units, and thus limit the manufacturing efficiency. It is therefore desirable to design a method to achieve the possibility of concurrent testing of multiple packaged devices before they are separated into individual packaged units.

[0007] Therefore, solving or mitigating these known problems in packaging of power switching semiconductor devices may improve device reliability, power handling capability, and efficiency of packaging operations. Utility Model Content

[0008] The first object of the present invention is to eliminate the packaging reliability problems of one or more power switching semiconductor devices caused by the use of a bonding process. The second object of the present invention is to reduce the thermal resistance of the packaging of one or more power switching semiconductor devices. The third object of the present invention is to enable the possibility of concurrent testing of multiple packaging units of one or more power switching semiconductor devices before being divided into separate packaging units. The present invention aims to alleviate or at least mitigate problems related to at least one or more of the aforementioned problems.

[0009] According to the utility model, a power switch semiconductor device is provided, which includes:

[0010] A power switch semiconductor device die having three electrodes, namely a back electrode and two front electrodes;

[0011] a package having a substrate with an island, the power switching semiconductor device die being conductively die attached to the island, wherein the back electrode faces a top side of the package, the package having an insulating portion of an electronic molding compound encapsulating the power switching semiconductor device die;

[0012] a hole extending through the insulating portion of the package to access at least one electrode of the power switch semiconductor device die;

[0013] a conductive path through the hole, the conductive path being used to connect the at least one electrode of the power switch semiconductor device die; and

[0014] Conductive connections of the one or more electrodes of the power switching semiconductor device die to corresponding pin-out connection ports on a bottom side of the package.

[0015] In a preferred embodiment, the power switching semiconductor device includes: a hole passing through the insulating portion of the package to access at least one other electrode, a conductive path through the hole for connecting the at least one other electrode, and a conductive connection from the at least one other electrode to a corresponding pin output connection port on the bottom side of the package.

[0016] Preferably, the one or more pin-out connection ports of the package have a processed surface.

[0017] In another preferred embodiment, the power switching semiconductor device includes: a plurality of the power switching semiconductor device dies packaged in the same package, wherein each power switching semiconductor device die conductive die is attached to the same package substrate, and the back electrode faces the top side of the package.

[0018] More preferably, the package has respective insulating portions encapsulating the power switch semiconductor device die, each insulating portion having the hole and the conductive path passing through the hole.

[0019] Preferably, the substrate of the package is selected from a lead frame and a bare PCB.

[0020] More preferably, the substrate of the package comprises a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB to enhance heat dissipation.

[0021] Still more preferably, the substrate of the package comprises a PCB having blind vias for heat transfer from the one or more power switching semiconductor device dies to metal on the top side of the package.

[0022] Still more preferably, the substrate of the package comprises a PCB having ceramic insulation between the one or more power switching semiconductor device dies and metal on the top side of the package to reduce junction-to-case thermal resistance.

[0023] In a further preferred embodiment, the insulating portion comprises at least one other layer of electronic molding compound encapsulating the power switching semiconductor device die and a previous layer, wherein the hole and the conductive path through the hole are associated with each layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0025] Figure 1A TOLL type package of a single power MOSFET device product is shown through a top view, a bottom view and two side views;

[0026] Figure 2 Five schematic diagrams are used to illustrate some typical power switch semiconductor devices that can be packaged into products according to the present invention;

[0027] Figure 3(a) to Figure 3(d) A first design implementation scheme of packaging a single power switch semiconductor device into a product of the present invention is shown in a bottom view and three progressive cross-sectional side views, respectively;

[0028] Figure 4 (a) to Figure 4 (c) each discloses, through a circuit diagram and a bottom view, the use of the first design embodiment of the present invention to package multiple power switch power semiconductor dies into various module products;

[0029] Figure 5 It is a circuit diagram of a three-phase bridge driver that can be packaged as a module product using the utility model; and

[0030] Figure 6(a) to Figure 6(d) The bottom view and the cross-sectional side view respectively show how the present invention can be used. Figure 5 The circuit package shown is a second design implementation of a module product. DETAILED DESCRIPTION

[0031] exist Figure 2 , some typical power switch semiconductor devices that can be packaged using the present invention are shown, namely, NPN bipolar device 201, N-type MOSFET device 202, IGBT device 203, PNP bipolar device 204, and P-type MOSFET device 205. It should be noted that the list is only used as an example and is by no means exhaustive.

[0032] The common characteristic of all such power switching semiconductor devices is that they have three electrodes, namely a substrate electrode on one side of the substrate (usually referred to as the back side) of the power switching semiconductor device die that serves as the switching terminal, and two other electrodes on the other side (usually referred to as the front side) of the power switching semiconductor device die, namely a control electrode for controlling the on / off state of the power switching semiconductor device die and another switch electrode for the power switching semiconductor device die.

[0033] Now refer to the accompanying drawings Figure 3(a) to Figure 6(d) , showing an embodiment of a method for packaging at least one power switch semiconductor device die in a single package according to the present invention and the resulting packaged power switch semiconductor device.

[0034] Figures 3(a) to 3(d)A first preferred embodiment of a method of using the present invention to package at least one, or in this particular example, a single power switch semiconductor device die 301 is shown. The packaging method flow begins with attaching the substrate (back side) 302 of the power switch semiconductor device die 301 to the inner metal surface 309 of the substrate of the package 30301 or 30302 or 30303 by means of a conductive die attach compound 304.

[0035] The substrate of the package is preferably a metal lead frame 30301 for achieving lower thermal resistance. Both thermal conduction and electrical conduction between the power switch semiconductor device die 301 and the metal surface 309 (a) of the package located on the opposite side of the power switch semiconductor device die are achieved. The substrate of the package can also be various types of bare PCB 30302 (metal-based PCB, such as aluminum or copper-based PCB, or ordinary PCB), in which one exposed metal surface 309 (a) is used as a heat conduction medium to the external environment (such as air), and the other (inner) metal surface 309 is used as a die attachment surface, and the two surfaces are interconnected by blind vias 305. As a specific example, a PCB without blind vias can also be used, and the thermal resistance is increased while achieving electrical isolation between the die attachment pad and the exposed metal surface 309 (a) of the package. PCBs using ceramic as a dielectric or a ceramic insert 306 between the die attachment pad and the exposed metal surface 309 (a) can also be used to improve thermal conductivity while also achieving electrical isolation. Then, the front electrodes of the power switch semiconductor device die 301, i.e., the control electrode 307 and the switch electrode 308, together with the inner metal surface 309 of the package substrate 30301 or 30302 or 30303, can be used for further processing according to the present invention. The bottom view and the cross-sectional side view of the package after this processing step are shown in FIG. 3( a ).

[0036] After the die attach process, the insulating portion 310 of the body of the package is formed by applying an electronic molding compound (EMC). Preferably, an injection molding process is used for this processing step. Alternative processing methods may also be applied, such as drop dispensing followed by thermal curing.

[0037] Selective drilling is then performed, preferably by laser drilling, through the insulating body of the package to reach the three electrodes 302, 307 and 308 of the power switch semiconductor device die 301. Typically, the drilled holes 311 will directly reach the two electrodes 307 and 308 at the bonding pads at the front side of the power switch semiconductor device die 301, and indirectly reach the substrate electrode 302 of the power switch semiconductor device die 301 through metal connections along the internal metal surface 309 within the substrate of the package 30301 or 30302, 30303. A bottom view and a cross-sectional side view of the package up to the above processing steps are shown in Figure 3(b).

[0038] Then, preferably, the metal interconnection between the three electrodes 302, 307 and 308 of the power switch semiconductor device die 301 and the corresponding pin-out connection ports of the package is performed by a process similar to that of bare PCB manufacturing. The processing steps involved may include, but are not limited to, a combination of chemical metal plating, photo processing and metal etching to define the electrical connection path within the package as required. FIG. 3( c) shows a bottom view and a cross-sectional side view of the package until the above processing steps. In FIG. 3( c), metal patterns 312, 313 and 314 are connected metals from the bottom side of the package to the corresponding switch electrodes 308, control electrodes 307 and substrate electrodes 302 of the switch power semiconductor device die 301 through corresponding holes 311 in FIG. 3( b) below such metal patterns 312, 313 and 314. Further processing steps will then be taken to define the pin-out connection ports on these metal connection patterns.

[0039] The pin-out connection port surface treatment is similar to the bare PCB manufacturing process, such as solder mask, gold / silver plating or solder hot air leveling. The bottom view and cross-sectional side view of the package until the above processing steps are shown in Figure 3(d). In Figure 3(d), 316, 317 and 318 are pin-out connection ports for switch electrode 308, substrate electrode 302 and control electrode 307, respectively. The solder mask 315 covers the area except the pin-out connection ports 316-318, and the dotted shapes 312, 313 and 314 in the bottom view are metal traces located under the solder mask as in Figure 3(c).

[0040] Optionally, an isolation polymer similar to the solder mask in bare PCB manufacturing can be deposited on the top side of the package to achieve exposed metal covering the heat transfer to the environment.

[0041] Based on the foregoing description, the method of packaging at least one power switch semiconductor device die in a package can be summarized as comprising at least the following steps:

[0042] (A) conductive die attaching a power switching semiconductor device die to an island of a substrate of a package with a backside or substrate electrode facing the top side of the package;

[0043] (B) encapsulating the power switch semiconductor device die with an electronic molding compound to form an insulating portion of the package;

[0044] (C) forming a hole through the insulating portion of the package to access at least one, for example, front side electrode of the power switch semiconductor device die;

[0045] (D) forming a conductive path through the hole within the package for connecting the at least one electrode of the power switching semiconductor device die; and

[0046] (E) forming conductive connections from the one or more electrodes of the power switch semiconductor device die to corresponding pin-out connection ports on the bottom side of the package.

[0047] It should be noted that step (C) may include forming a hole through the insulating portion of the package to access at least one other, for example back electrode. In this case, step (D) includes forming a conductive path through the hole within the package for connecting the at least one other electrode, and step (E) includes forming a conductive connection of the at least one other electrode to a corresponding pin-out connection port on the bottom side of the package.

[0048] The packaging method of the present subject matter may include step (F): processing the surface of the one or more pin-out connection ports of the package; and step (G): testing the power switch semiconductor device die through the one or more pin-out connection ports of the package.

[0049] As a variation of the described embodiment, after the processing steps to obtain the resulting assembly of FIG. 3( c ), the package body molding, selective drilling, and internal connection implementation may be repeated until the last layer of the pin-out connection port (i.e., the bottom side of the package) is reached, followed by solder mask and pin-out connection port surface treatment. It is contemplated that this variation and similar variations fall within the scope of the present invention.

[0050] Refer to the repeated steps, which are:

[0051] Package body molding - step (B') encapsulating the resulting assembly with an electronic molding compound to form another layer of the insulating portion of the package;

[0052] Selective drilling—step (C') forms a hole through all insulating portions of the package to access at least one other electrode of the power switching semiconductor device die; and

[0053] • Internal connection realization—step (D′) forms a conductive path through the via within the package for connecting the at least one other electrode of the power switching semiconductor device die.

[0054] Taking these repeated steps into account, the packaging method of the present subject matter includes: after step (D) and before step (E), repeating steps (B), (C) and (D) as steps (B'), (C') and (D') one or more times, respectively, depending on the number of additional layers of the insulating portion of the package desired.

[0055] Based on the foregoing description, the power switch semiconductor device packaged by the described method can be summarized as at least comprising: a power switch semiconductor device die, the power switch semiconductor device die having three electrodes, namely a substrate electrode and two front electrodes; and a package having a substrate with an island, the power switch semiconductor device die conductive die attached to the island, wherein the back electrode faces the top side of the package. The package has an insulating portion of an electronic mold compound encapsulating the power switch semiconductor device die. There is a hole through the insulating portion of the package to access at least one, such as a front electrode, of the power switch semiconductor device die, and a conductive path within the package connects the at least one electrode of the power switch semiconductor device die through the hole. Also included is a conductive connector from one or more electrodes of the power switch semiconductor device die to a corresponding pin-out connection port on the bottom side of the package.

[0056] For some circuits, a power switching semiconductor device may include a hole through an insulating portion of the package to access at least one other electrode within the package, such as a back electrode, a conductive path within the package connecting the at least one other electrode through the hole, and a conductive connection connecting the at least one other electrode to a corresponding pin output connection port on the bottom side of the package.

[0057] Since all interconnections between the electrodes 302, 307 and 308 of the power switch semiconductor device die 301 and the corresponding pin output connection ports 316, 317 and 318 of the package are integrated in the package, the wire bonding process is eliminated. Therefore, there is no bonding-related packaging reliability problem in the packaged power switch semiconductor device of the utility model.

[0058] Additionally, since the substrate side die pad thermally linked to the top side metal 309 ( a ) of the package will face upward and be exposed to the environment (air or through an attached heat sink) after soldering in the PCBA, thermal resistance will be reduced compared to existing packaging methods where the substrate electrodes face downward.

[0059] Furthermore, all three pin-out connection ports 316, 317, and 318 of each package are essentially insulated. In addition, the two pin-out connection ports connected to the front electrodes of the power switch semiconductor device die 301 of each individual packaged device are isolated from all other such pin-out connection ports of other packages manufactured in a single pass in multiple packages, where only the substrate pin-out connection ports of multiple packages are connected. For these reasons, concurrent testing of multiple package units becomes possible.

[0060] As discussed, final testing of packaged devices is preferably performed by concurrent testing of multiple packaged units in panel form before separation into individual units. Of course, the normal process of separation into individual units before final testing is still possible.

[0061] Another variation of the described embodiment is to package multiple power switching semiconductor devices with a common substrate electrode for application in a single package using the same aforementioned processing steps. In this regard, Figure 4 (a) to 4(c) show some typical examples of semiconductor circuits that can be packaged using the present invention.

[0062] exist Figure 4 In (a), a circuit diagram of three N-type MOSFET devices 401, 402 and 403 with a common drain (substrate) electrode connected to VDD and a corresponding bottom view of the package are shown as potential candidates for use with the present invention and multi-die packaging.

[0063] Using the processing steps as described in the previous embodiments, the corresponding gate electrodes and source electrodes of the N-type MOSFET device dies 401, 402 and 403, namely G1, G2, G3, S1, S2 and S3, are connected to the corresponding pin output connection ports of the package, and the substrate electrodes of the N-type MOSFET device dies 401, 402 and 403 are connected to the VDD pin output connection port of the package. Figure 4 Also shown in (a) is a corresponding bottom view of the pin-out connection port of the package, where the dashed shape represents the metal pattern under the solder mask. The three packaged power switching semiconductor device dies (N-type MOSFETs) can be used as three high-side devices in a three-phase bridge for various applications such as BLDC or induction motor drives.

[0064] exist Figure 4 In (b), a circuit diagram and a bottom view of a corresponding package for a P-type MOSFET device 404 and an N-type MOSFET device 405 are shown, wherein a common drain (substrate) electrode connected to an output pin outside the package is shown as another potential candidate for using the present invention and multi-die packaging.

[0065] The source electrode of the P-type MOSFET device 404 and the source electrode of the N-type MOSFET 405 device are respectively connected to the VDD lead-out connection port and the VSS lead-out connection port of the package. The gate electrode of the P-type MOSFET device 404 and the gate electrode of the N-type MOSFET device 405 are respectively connected to the lead-out connection ports G4 and G5 of the package. The substrate electrode of the P-type MOSFET device 404 and the substrate electrode of the N-type MOSFET device 405 are connected to the output lead-out connection port of the package. The processing steps for such packaging are as described in the previous embodiment. The corresponding bottom view of the pin output connection port of the package is also shown as a metal pattern representing the solder mask below in a dotted shape. This package circuit can be used as a half-bridge driver or motor driver for power switch conversion.

[0066] exist Figure 4 In (c), a circuit diagram of two N-type MOSFET devices 406 and 407 with a common drain (substrate) electrode and a corresponding bottom view of the package are provided as yet another potential candidate for use with the present invention and multi-die packaging.

[0067] The corresponding gate electrodes and source electrodes of N-type MOSFET devices 406 and 407, i.e., G6, G7, S6, and S7, are connected to the corresponding pin-out connection ports of the package using the processing steps described in the previous embodiment. The corresponding bottom view of the pin-out connection port of the package is also shown as a metal pattern under the solder mask represented by a dotted shape. The target application of this package module is overcharge and over-discharge protection of lithium batteries. Since no external pin-out connection to the substrate node is required, drilling holes to reach the substrate during the selective drilling process can be omitted.

[0068] In general, for a multi-die package, the method involves packaging a plurality of power switching semiconductor device dies in the same package having a common package substrate, wherein each power switching semiconductor device die undergoes at least steps (A) to (E) and optionally steps (F) and (G). In the packaged product, the substrate has a corresponding portion or island to which the power switching semiconductor device die conductive die is attached. Each power switching semiconductor device die conductive die is attached to the same substrate with its back electrode facing the top side of the package. The package has a corresponding insulating portion encapsulating the power switching semiconductor device die, each insulating portion having the hole of step (C) and the conductive path through the hole of step (D).

[0069] For more complex circuits, more interconnect layout layers will be required. The use of additional layers or more layers of sandwiched PCB package substrates can be used to solve the layout problem. Alternatively, EMC molding, selective hole drilling, and conductive path production using a process similar to that of bare PCB production as previously described can also be reused. Therefore, in the resulting power switching semiconductor device product, the insulating portion includes at least one other layer of electronic molding compound that encapsulates the power switching semiconductor device die and the previous layer, wherein the holes of step (C) and the conductive paths through the holes of step (D) are associated with each layer.

[0070] It should be noted that the described examples are given only as typical examples and are by no means exhaustive.

[0071] In the description so far, there are limitations on the common substrate connection within the package for packaging multiple switch semiconductor device dies. This may limit the adoption of the present invention because the separation of substrate electrodes is quite common in many application circuits.

[0072] A second embodiment of the present invention is disclosed herein, in which the limitation of a common substrate can be avoided. Figure 5 5 is a circuit diagram of a three-phase bridge driver having six N-type MOSFET device dies 501-506, the dies having substrate electrodes that cannot be short-circuited together. A typical application of this semiconductor circuit is a power driver for a BLDC or induction motor. This semiconductor circuit is now used as a candidate for a second embodiment of the present invention showing that the circuit is packaged as a module.

[0073] exist Figure 5 In the embodiment of the present invention, N-type MOSFET devices 501, 502 and 503 have a common drain (substrate) connection to the pin-out connection pad VDD and therefore share a common die attach island in the package substrate. However, each of the N-type MOSFET devices 504, 505 and 506 requires a separate die attach island in the package substrate that is isolated to achieve circuit connection. Therefore, a package substrate with multiple (four in this case) isolated die attach islands will be required.

[0074] For the first embodiment, it is possible to use a metal lead frame with multiple die attach islands as a package substrate, provided that multiple package modules do not need to be tested concurrently before being separated into individual modules.By using a PCB substrate, the advantages of such concurrent testing can also be exploited.

[0075] Figures 6(a) to 6(d) The method of using the utility model will be shown according to Figure 5Six N-type MOSFET device dies 501-506 of the circuit are packaged into a preferred embodiment of a package module. In these figures, although only a PCB with blind holes between the die attach island and the exposed metal surface of the package is disclosed as a package substrate, it should be understood that it is also possible to use other types of package substrates.

[0076] The packaging method flow of this second embodiment begins by attaching the substrates of the power switch semiconductor device dies 501 - 506 to respective die attach islands of the package substrate via a conductive die attach compound.

[0077] The substrate of the package is preferably selected from one of various types of bare PCBs (metal-based PCBs, such as aluminum- or copper-based PCBs, or ordinary PCBs), in which multiple exposed metal surfaces are used as a heat conduction medium to the external environment (such as air), and the other side is used as a die attachment surface, and the two sides are interconnected by blind vias.

[0078] As a specific example, a PCB without blind vias can also be used, with increased thermal resistance while achieving electrical isolation between the die attach pad and the exposed metal surface of the package. A PCB using ceramic as a dielectric or ceramic insert between the die attach island and the exposed metal surface side can also be used to increase thermal conductivity while also achieving electrical isolation.

[0079] A bottom view and a cross-sectional side view of a package produced by the subject method using a metal-based PCB with blind vias connecting a top metal island and an inner die attach island for heat dissipation to the environment are shown in FIG6( a). In FIG6( a), N-type MOSFET device dies 501, 502, and 503 are attached to an inner metal island 602 of a package substrate 601 using a conductive die attach compound 606. N-type MOSFET device dies 504, 505, and 506 are attached to respective inner metal islands 603, 604, and 605 of the package substrate 601 using a conductive die attach compound 606. Thermal and electrical conduction between the inner metal island 602 and an exposed metal surface 608 at the top of the package substrate 601 is established through a blind via 607. Thermal and electrical conduction between the inner metal island 603, 604, and 605 and exposed metal surfaces 609, 610, and 611, respectively, located at the top of the package substrate 601 are established through the blind via 607. Reference numerals 612-617 correspond to Figure 5 Reference numerals 618-623 correspond to the source electrodes of the N-type MOSFET device dies 501-506, respectively.

[0080] The substrate of the package may also be a metal lead frame to achieve lower thermal resistance. Thermal and electrical conduction between the power switching semiconductor device die and the exposed top metal surface of the package on the opposite side of the power switching semiconductor device die is achieved. After the die attach process, the insulating portion of the body of the package is formed by applying an electronic mold compound (EMC) 624. Preferably, an injection molding process is used for this processing step. Alternative processing methods such as drop dispensing followed by thermal curing may also be used.

[0081] Selective hole drilling is then preferably performed by laser drilling through the insulating body 624 of the package to reach the corresponding three electrodes of the six N-type MOSFET device dies 501-506. A bottom view and a cross-sectional side view of the package until the above-mentioned processing steps are shown in FIG. 6( b). In FIG. 6( b), there are two types of holes, namely holes 625 and holes 626. The drilled holes 625 will directly reach the two electrodes at the bonding pads on the front side of the six N-type MOSFET device dies 501-506. The drilled holes 626 will indirectly reach the substrate electrodes (back side) of the six N-type MOSFET device dies 501-506 through the internal metal islands 602-605 in FIG. 6( a) of the package substrate.

[0082] Then, metal interconnections between the electrodes of the six N-type MOSFET device dies 501 - 506 and corresponding locations of the pin-out connection ports at the periphery of the package are preferably made by a process similar to bare PCB manufacturing.

[0083] The processing steps involved may include, but are not limited to, a combination of electroless metal plating, photo processing, and metal etching to define the desired electrical connection paths. FIG6( c ) shows a bottom view and a cross-sectional side view of the package module after metal connections are made between the electrodes of the six N-type MOSFET device dies 501-506 and the corresponding locations of the pin-out connection ports at the periphery of the package.

[0084] In FIG6(c), metal pattern 639 is connected to metal island 602 of FIG6(a) through hole 626 of FIG6(b) below metal pattern 639. Since the drain (substrate) electrodes of N-type MOSFET device dies 501, 502 and 503 are all conductive dies attached to metal island 602, this means that metal pattern 639 is Figure 5 The metal patterns 627-632 are connected to the gate electrodes of the N-type MOSFET device dies 501-506 through the holes 625 in FIG. 6(b) below the metal patterns 627-632. The electrical equivalent circuit nodes of the metal patterns 627-632 are Figure 5GUU, GUV, GUW, GLU, GLV and GLW shown. The metal patterns 633-635 are connected to the source electrodes of the N-type MOSFET device dies 501-503 through the holes 625 of FIG. 6(b) below the metal patterns 633-635, and are respectively connected to the metal islands 603-605 of FIG. 6(a) through the holes 626 of FIG. 6(b) below the metal patterns 633-635. The metal patterns 633-635 are also connected to the die attachment metal islands 603-605 of FIG. 6(a) through the holes 626 of FIG. 6(b), and are therefore respectively electrically connected to the substrate electrodes (drains) of the N-type MOSFET device dies 504-506. The equivalent circuit nodes of the metal patterns 633-635 are Figure 5 U, V and W of the metal patterns 636-638. The metal patterns 636-638 are connected to the source electrodes of the N-type MOSFET device dies 504-506 through the holes 625 in FIG. 6(b) below the metal patterns 636-638. The equivalent circuit nodes of the metal patterns 636-638 are Figure 5 VSU, VSV and VSW.

[0085] The pin-out connection port surface treatment is then performed, such as solder mask, gold / silver plating or solder hot air leveling. FIG6( d) shows an overhead view and a cross-sectional side view of the package module after the pin-out connection port surface treatment. In FIG6( d), the pattern shown by the dotted line in the bottom view is the same as the metal pattern in the bottom view of FIG6( c). A solder mask treatment is applied so that the isolated solder mask 653 covers the entire bottom side of the package except the pin-out connection ports 640-652. Further surface treatment is then applied to the pin-out connection ports 640-652, such as gold / silver plating or solder hot air leveling. The equivalent circuit nodes of the pin-out connection ports 640-645 are respectively Figure 5 The equivalent circuit nodes of the pin output connection ports 646-651 are Figure 5 The equivalent circuit nodes of the pin output connection port 652 are Figure 5 of VDD.

[0086] As a variation of this embodiment, after the processing steps to produce the assembly of FIG. 6( c ), the package body molding, selective drilling, and internal connection implementation may be repeated until the last layer of the pin-out connection port is reached, and then the pin-out connection port surface treatment such as solder mask is performed. It is contemplated that this variation and similar variations fall within the scope of the present invention.

[0087] In the case of using a PCB substrate, the final test of the packaged module is preferably carried out by concurrently testing multiple packaged units in panel form and then separating the packaged units into individual power switch units. When using a metal lead frame substrate, the normal process of separating the packaged units into individual units before final testing applies.

[0088] Therefore, for a multi-die package, the packaging method of the present subject matter may include step (H): cutting the resulting package into a plurality of smaller packages to form separate power switch units, each power switch unit including one or more power switch semiconductor device dies in the power switch semiconductor device die. Generally speaking, the method involves packaging a plurality of power switch semiconductor device dies in the same package having a common package substrate, wherein each power switch semiconductor device die undergoes steps (A) to (G). The method may include step (H) after step (G): cutting the resulting package into a plurality of smaller packages, each smaller package including one or more power switch semiconductor device dies in the power switch semiconductor device die.

[0089] The foregoing description has so far only covered the packaging of one or more power switch semiconductor devices. It is contemplated that one or more power switch semiconductor devices may be packaged together with one or more other semiconductor devices using the same basic concept of the present invention and obviously falls within the scope of the present invention.

[0090] The packaging method of the utility model replaces the electrical connection between the pin-out connection port of the package and the corresponding metal connection pad of one or more power switch semiconductor device tube cores usually made by a bonding process through a process similar to PCB manufacturing. In addition, the substrate side (back side) of one or more power switch semiconductor device tube cores attached to the metal island of the packaging substrate of the package faces upward, while the pin-out connection port of the package faces downward. Through the tube core attached metal island to the environment (air) for heat conduction, this packaging design provides a direct heat dissipation path from the exposed metal surface of the package directly to the environment for reducing thermal resistance. In addition, when packaging is performed in batches with multiple packaging units, this packaging method isolates the other pin-out connection ports except the substrate of one or more power switch device tube cores from each other. Therefore, concurrent testing is possible before multiple packaged devices are divided into separate units.

Claims

1. A power switch semiconductor device, characterized in that: include: A power switch semiconductor device die having three electrodes, namely a back electrode and two front electrodes; a package having a substrate with an island, a conductive die of the power switching semiconductor device die being attached to the island, wherein the back electrode faces a top side of the package, the package having an insulating portion of an electronic molding compound encapsulating the power switching semiconductor device die; a hole extending through the insulating portion of the package to access at least one electrode of the power switch semiconductor device die; a conductive path through the hole, the conductive path being used to connect the at least one electrode of the power switch semiconductor device die; as well as An electrically conductive connection of the at least one electrode of the power switching semiconductor device die to a corresponding pin-out connection port on a bottom side of the package.

2. The power switch semiconductor device according to claim 1, characterized in that: Also includes: a hole through the insulating portion of the package to access at least one additional electrode, a conductive path through the hole for connecting the at least one additional electrode, and a conductive connection from the at least one additional electrode to a corresponding pin-out connection port on the bottom side of the package.

3. The power switch semiconductor device according to claim 1, characterized in that: One or more of the pin-out connection ports of the package have a processed surface.

4. The power switch semiconductor device according to claim 1, characterized in that: include: A plurality of the power switch semiconductor device dies are packaged in the same package, wherein the conductive die of each power switch semiconductor device die is attached to the same package substrate, and the back electrode faces the top side of the package.

5. The power switch semiconductor device according to claim 4, characterized in that: The package has respective insulating portions encapsulating the power switch semiconductor device die, each insulating portion having the hole and the conductive path through the hole.

6. The power switch semiconductor device according to claim 1, characterized in that: The substrate of the package is selected from a lead frame and a bare PCB.

7. The power switch semiconductor device according to claim 6, characterized in that: The substrate of the package includes a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB to enhance heat dissipation.

8. The power switch semiconductor device according to claim 7, characterized in that: The substrate of the package includes a PCB having blind vias for heat transfer from one or more of the power switching semiconductor device dies to metal on a top side of the package.

9. The power switch semiconductor device according to claim 7, characterized in that: The substrate of the package includes a PCB having ceramic insulation between one or more of the power switching semiconductor device dies and metal on the top side of the package to reduce junction-to-case thermal resistance.

10. The power switch semiconductor device according to any one of claims 1 to 9, characterized in that: The insulating portion includes at least one additional layer of electronic mold compound encapsulating the power switching semiconductor device die and a previous layer, wherein the aperture and the conductive path through the aperture are associated with each layer.

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