Fault protection circuit, power conversion circuit and vehicle

Abstract

The utility model discloses a fault protection circuit, a power conversion circuit and a vehicle, and belongs to the technical field of power electronics. The fault protection circuit is applied to a bridge arm circuit, the bridge arm circuit comprises an upper bridge arm and a lower bridge arm which are connected in series, and the fault protection circuit comprises a short circuit detection unit which is electrically connected with a first bridge arm and is configured to provide a short circuit signal when short circuit of the first bridge arm is detected, and the first bridge arm is the upper bridge arm or the lower bridge arm; the overcurrent detection unit is electrically connected with the first bridge arm and is configured to provide an overcurrent signal when overcurrent of the first bridge arm is detected; the driving unit is electrically connected with the bridge arm circuit, the over-current detection unit and the short circuit detection unit and is configured to drive the second bridge arm to be switched off when receiving the over-current signal and the short circuit signal, the second bridge arm is the opposite side bridge arm of the first bridge arm, and the condition of bus direct connection short circuit caused by simultaneous conduction of the upper bridge arm and the lower bridge arm is avoided.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and in particular, relates to a fault protection circuit, a power conversion circuit and a vehicle. Background Art

[0002] In the current hybrid vehicle solution, for IGBT short-circuit faults, the DESAT pin of the driver chip is mainly used to detect the voltage VCE between the collector and emitter of the IGBT. VCE exceeding the normal value indicates that the corresponding bridge arm is overcurrent. When the upper bridge arm of a phase is overcurrent, the driver chip will first control the three-phase upper bridge to block the wave, and then control the three-phase lower bridge to enter the active short-circuit state after a delay. When the lower bridge arm of a phase is overcurrent, the logic circuit will first control the three-phase lower bridge arm to block the wave, and then control the three-phase upper bridge arm to enter the active short-circuit state after a delay. However, in the relevant technology, if the upper bridge arm is overcurrent, the IGBT is further damaged and an actual short circuit is formed, the logic circuit will still control the lower bridge arm to enter the active short-circuit state. Similarly, if the lower bridge arm is overcurrent, the IGBT is further damaged and an actual short circuit is formed, the logic circuit will still control the upper bridge arm to enter the active short-circuit state, so that the upper and lower bridge arms are in the on state at the same time, which will cause a direct bus short circuit and damage the device. Utility Model Content

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a fault protection circuit, a power conversion circuit and a vehicle, wherein when the driving unit receives an overcurrent signal and a short-circuit signal from the same bridge arm, that is, when a bridge arm is overcurrent and short-circuited, the driving unit drives the opposite bridge arm to shut down, thereby avoiding a direct bus short circuit caused by the upper and lower bridge arms being turned on at the same time.

[0004] In a first aspect, the present application provides a fault protection circuit, which is applied to a bridge arm circuit, wherein the bridge arm circuit includes an upper bridge arm and a lower bridge arm connected in series, and the fault protection circuit includes:

[0005] A short circuit detection unit, electrically connected to the first bridge arm and configured to provide a short circuit signal when a short circuit is detected in the first bridge arm, the first bridge arm being an upper bridge arm or a lower bridge arm;

[0006] an overcurrent detection unit, electrically connected to the first bridge arm and configured to provide an overcurrent signal when an overcurrent is detected in the first bridge arm;

[0007] The driving unit is electrically connected to the bridge arm circuit, the overcurrent detection unit and the short-circuit detection unit respectively, and is configured to drive the second bridge arm to turn off when receiving the overcurrent signal and the short-circuit signal, and the second bridge arm is the opposite bridge arm of the first bridge arm.

[0008] According to the fault protection circuit of the present application, when an arm of the bridge arm circuit is overcurrent, the overcurrent detection unit electrically connected to the bridge arm provides an overcurrent signal; when an arm of the bridge arm circuit is short-circuited, the short-circuit detection unit provides a short-circuit signal; when the driving unit receives the overcurrent signal and the short-circuit signal of the same arm, that is, when a bridge arm is overcurrent and short-circuited, the driving unit drives the opposite arm to shut down, so as to avoid a busbar direct short circuit caused by the simultaneous conduction of the upper and lower bridge arms.

[0009] According to one embodiment of the present application, the driving unit includes:

[0010] A first AND gate, wherein a first input end of the first AND gate is electrically connected to the output end of the overcurrent detection unit, a second input end of the first AND gate is electrically connected to the output end of the short circuit detection unit, and an output end of the first AND gate is electrically connected to the driving end of the second bridge arm.

[0011] According to one embodiment of the present application, the driving unit further includes:

[0012] A second AND gate, wherein a first input terminal of the second AND gate is connected to the overcurrent signal of the second bridge arm, and a second input terminal of the second AND gate is connected to the driving signal of the second bridge arm;

[0013] An OR gate, wherein a first input terminal of the OR gate is electrically connected to an output terminal of the first AND gate, a second input terminal of the OR gate is electrically connected to an output terminal of the second AND gate, and an output terminal of the OR gate is electrically connected to a driving terminal of the second bridge arm.

[0014] According to one embodiment of the present application, the driving unit further includes:

[0015] An inverter, an input end of the inverter being electrically connected to an output end of the overcurrent detection unit;

[0016] A third AND gate, wherein a first input terminal of the third AND gate is electrically connected to the output terminal of the inverter, a second input terminal of the third AND gate is connected to the overcurrent signal of the second bridge arm, and an output terminal of the third AND gate is electrically connected to an input terminal of the first AND gate.

[0017] According to one embodiment of the present application, the driving unit further includes:

[0018] a first resistor, wherein a first end of the first resistor is electrically connected to an output end of the third AND gate;

[0019] A capacitor, wherein a first end of the capacitor is electrically connected to the second end of the first resistor, and a second end of the capacitor is electrically connected to the ground node.

[0020] According to one embodiment of the present application, the short circuit detection unit includes:

[0021] The first comparator has a positive input terminal connected to the bridge arm voltage of the first bridge arm, and a negative input terminal connected to a reference voltage, and the reference voltage is greater than the bridge arm voltage when the first bridge arm is normally turned on.

[0022] According to one embodiment of the present application, the fault protection circuit further includes:

[0023] a second resistor, a first end of the second resistor being electrically connected to the first end of the first bridge arm;

[0024] An isolation operational amplifier chip, wherein an input end of the isolation operational amplifier chip is electrically connected to the second end of the second resistor, and an output end of the isolation operational amplifier chip is electrically connected to the short-circuit detection unit;

[0025] A third resistor, wherein a first end of the third resistor is electrically connected to the second end of the second resistor and the input end of the isolation operational amplifier chip respectively, and a second end of the third resistor is electrically connected to the second end of the first bridge arm.

[0026] According to one embodiment of the present application, the bridge arm circuit is electrically connected between the positive bus and the negative bus, and the fault protection circuit further includes:

[0027] A second comparator, wherein a positive phase input terminal of the second comparator is connected to a bus voltage between a positive bus and a negative bus, a negative phase input terminal of the second comparator is connected to a bridge arm voltage of a second bridge arm, and an output terminal of the second comparator is electrically connected to the short circuit detection unit;

[0028] a fourth resistor, wherein a first end of the fourth resistor is electrically connected to the non-inverting input terminal, and a second end of the fourth resistor is electrically connected to the ground node;

[0029] A fifth resistor, wherein a first end of the fifth resistor is electrically connected to the negative phase input end of the second comparator, and a second end of the fifth resistor is electrically connected to the output end of the second comparator.

[0030] In a second aspect, the present application provides a power conversion circuit, including a three-phase inverter circuit and the aforementioned fault protection circuit, wherein a bridge arm in the three-phase inverter circuit is electrically connected to the fault protection circuit.

[0031] According to the power conversion circuit of the present application, when a bridge arm of the three-phase inverter circuit has an overcurrent, an overcurrent detection unit electrically connected to the bridge arm provides an overcurrent signal; when a bridge arm of the bridge arm circuit has a short circuit, a short circuit detection unit provides a short circuit signal; when the driving unit receives the overcurrent signal and the short circuit signal of the same bridge arm, that is, when a bridge arm has an overcurrent and a short circuit, the driving unit drives the bridge arm on the opposite side to turn off, thereby avoiding a busbar direct short circuit caused by the upper and lower bridge arms being turned on at the same time.

[0032] In a third aspect, the present application provides a vehicle comprising a battery, a motor and the aforementioned power conversion circuit, wherein the battery is electrically connected to a DC bus, the DC side of the power conversion circuit is electrically connected to the DC bus, and the AC side of the power conversion circuit is electrically connected to the motor.

[0033] An embodiment of the present application provides a vehicle, which includes a battery, a motor and the aforementioned power conversion circuit, wherein the battery is electrically connected to a DC bus, the DC side of the power conversion circuit is electrically connected to the DC bus, and the AC side of the power conversion circuit is electrically connected to the motor.

[0034] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0036] Figure 1 is a circuit diagram of a hybrid vehicle provided in an embodiment of the present application;

[0037] Figure 2 is a structural block diagram of a fault protection circuit provided in an embodiment of the present application;

[0038] Figure 3 It is one of the circuit schematic diagrams of the fault protection circuit provided in the embodiment of the present application;

[0039] Figure 4 It is one of the partial circuit diagrams of the fault protection circuit provided in the embodiment of the present application;

[0040] Figure 5 This is the second partial circuit diagram of the fault protection circuit provided in the embodiment of the present application;

[0041] Figure 6 This is the third partial circuit diagram of the fault protection circuit provided in the embodiment of the present application.

[0042] Reference numerals:

[0043] Motor 100, power conversion circuit 200, bridge arm circuit 210, first bridge arm 211, second bridge arm 212, fault protection circuit 300, short circuit detection unit 310, overcurrent detection unit 320, drive unit 330, first to second switch tubes Q1~Q2, first to third AND gates U1~U3, OR gate U4, isolation operational amplifier chip U5, first to second comparators A1~A2, first to seventh resistors R1~R7, capacitor C. DETAILED DESCRIPTION

[0044] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0045] In the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "coupled to" or "connected to" another element or an element / circuit is said to be "coupled to" or "connected to" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0046] In the description, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the numerical descriptors used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0047] In addition, descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0048] like Figure 1 As shown, a current hybrid vehicle generally includes at least one motor 100 and a three-phase inverter circuit. The DC side of the three-phase inverter circuit is electrically connected to the DC bus, and the AC side of the three-phase inverter circuit is electrically connected to the motor 100 to convert the DC power provided by the battery into AC power to supply the motor 100 to drive the vehicle. The three-phase inverter circuit includes three parallel bridge arm circuits 210. Each phase of the three-phase inverter circuit includes an upper bridge arm and a lower bridge arm. The upper bridge arm is provided with a first switch tube Q1, and the lower bridge arm is provided with a second switch tube Q2. The first switch tube Q1 and the second switch tube Q2 may be IGBTs (Insulated Gate Bipolar Transistors).

[0049] In the related art, for IGBT short-circuit faults, the voltage VCE between the collector and emitter of the IGBT is mainly detected by the DESAT pin of the driver chip. VCE exceeding the normal value indicates that the corresponding bridge arm is overcurrent. When the upper bridge arm of a phase is overcurrent, the driver chip will first control the three-phase upper bridge to block the wave, and then control the three-phase lower bridge to enter the active short-circuit state after a delay. When the lower bridge arm of a phase is overcurrent, the logic circuit will first control the three-phase lower bridge arm to block the wave, and then control the three-phase upper bridge arm to enter the active short-circuit state after a delay. However, in the related art, if the upper bridge arm is overcurrent, the IGBT is further damaged and an actual short circuit is formed, the logic circuit will still control the lower bridge arm to enter the active short-circuit state. Similarly, if the lower bridge arm is overcurrent, the IGBT is further damaged and an actual short circuit is formed, the logic circuit will still control the upper bridge arm to enter the active short-circuit state, so that the upper and lower bridge arms are in the on state at the same time, which will cause a direct bus short circuit and damage the device.

[0050] The present application proposes a fault protection circuit 300, a power conversion circuit 200 and a vehicle. The fault protection circuit 300 includes a drive unit 330. When the drive unit 330 receives an overcurrent signal and a short-circuit signal from the same bridge arm, that is, when a certain bridge arm is overcurrent and short-circuited, the drive unit 330 drives the opposite bridge arm to shut down, thereby avoiding a busbar direct short circuit caused by the upper and lower bridge arms being turned on at the same time.

[0051] like Figure 2 As shown, an embodiment of the present application proposes a fault protection circuit 300, which is applied to a bridge arm circuit 210. The bridge arm circuit 210 includes an upper bridge arm and a lower bridge arm connected in series. The fault protection circuit 300 includes: a short circuit detection unit 310, an overcurrent detection unit 320 and a driving unit 330. The short circuit detection unit 310 is electrically connected to the first bridge arm 211, and is configured to provide a short circuit signal when detecting that the first bridge arm 211 is short-circuited. The first bridge arm 211 is an upper bridge arm or a lower bridge arm; the overcurrent detection unit 320 is electrically connected to the first bridge arm 211, and is configured to provide an overcurrent signal when detecting that the first bridge arm 211 is overcurrent; the driving unit 330 is electrically connected to the bridge arm circuit 210, the overcurrent detection unit 320 and the short circuit detection unit 310 respectively, and is configured to drive the second bridge arm 212 to turn off when receiving the overcurrent signal and the short circuit signal. The second bridge arm 212 is the opposite bridge arm of the first bridge arm 211.

[0052] The bridge arm circuit 210 can be arranged between the positive bus and the negative bus, and the bridge arm circuit 210 includes an upper bridge arm, a first end of the upper bridge arm is electrically connected to the positive bus, a second end of the upper bridge arm is electrically connected to the first end of the lower bridge arm, and a first end of the lower bridge arm is electrically connected to the negative bus. When the upper bridge arm of a certain phase is the first bridge arm 211, the lower bridge arm of the same phase is the second bridge arm 212, and when the lower bridge arm of a certain phase is the first bridge arm 211, the upper bridge arm of the same phase is the second bridge arm 212. The first bridge arm 211 and the second bridge arm 212 are respectively provided with a switch tube, which can be an IGBT. The following description takes the example that the driving end of the IGBT is turned on when receiving a high-level signal and turned off when receiving a low-level signal as an example.

[0053] The first bridge arm 211 and the second bridge arm 212 are electrically connected to the corresponding fault protection circuit 300 respectively. The structure and principle of the fault protection circuit 300 are the same. The fault protection circuit 300 electrically connected to the first bridge arm 211 of a phase bridge arm circuit 210 is used as an example for explanation below.

[0054] The gate of the IGBT can be electrically connected to the driver chip. When the IGBT is normally turned on, the voltage VCE between the collector and the emitter is low. When the IGBT is overcurrent, the IGBT will enter a desaturation state, and VCE will rise rapidly. This voltage will charge the DESAT pin capacitor C of the driver chip. The overcurrent detection unit 320 can be electrically connected to the DESAT pin of the driver chip. When the DESAT pin voltage is higher than the threshold voltage, the overcurrent detection unit 320 generates an overcurrent signal, and the overcurrent signal can be a low-level signal. Among them, the threshold voltage is greater than the voltage of the DESAT pin of the driver chip when the IGBT is normally turned on. The specific value of the threshold voltage is not limited here and can be selected according to the actual application scenario. For example, the threshold voltage can be 6V.

[0055] The short-circuit detection unit 310 is electrically connected to the first bridge arm 211. When the IGBT is short-circuited, the IGBT will not enter a desaturation state, and the voltage VCE between the collector and the emitter is always close to 0V. The short-circuit detection unit 310 can determine whether the first bridge arm 211 is short-circuited by detecting the voltage between the collector and the emitter of the first bridge arm 211, and generate a short-circuit signal when the first bridge arm 211 is short-circuited. The short-circuit signal can be a low-level signal.

[0056] The input end of the driving unit 330 is electrically connected to the overcurrent detection unit 320 and the short circuit detection unit 310 respectively, and the output end of the driving unit 330 is electrically connected to the driving end of the second bridge arm 212. The driving unit 330 is mainly used to generate a driving signal to drive the conduction and shutdown of the second bridge arm 212. When the first bridge arm 211 is overcurrent and short-circuited, the driving unit 330 generates a shutdown signal to drive the second bridge arm 212 to shut down, so as to avoid the situation where the busbar is directly short-circuited due to the simultaneous conduction of the first bridge arm 211 and the second bridge arm 212.

[0057] According to the fault protection circuit 300 of the present application, when an arm of the bridge arm circuit 210 is overcurrent, the overcurrent detection unit 320 electrically connected to the bridge arm provides an overcurrent signal; when an arm of the bridge arm circuit 210 is short-circuited, the short-circuit detection unit 310 provides a short-circuit signal; when the driving unit 330 receives the overcurrent signal and the short-circuit signal of the same arm, that is, when a bridge arm is overcurrent and short-circuited, the driving unit 330 drives the opposite arm to shut down, so as to avoid a busbar direct short circuit caused by the simultaneous conduction of the upper and lower bridge arms.

[0058] like Figure 3 As shown, in some embodiments, the driving unit 330 includes a first AND gate U1. A first input terminal of the first AND gate U1 is electrically connected to the output terminal of the overcurrent detection unit 320, a second input terminal of the first AND gate U1 is electrically connected to the output terminal of the short circuit detection unit 310, and an output terminal of the first AND gate U1 is electrically connected to the driving terminal of the second bridge arm 212.

[0059] It should be noted that when the first bridge arm 211 has an instantaneous overcurrent, the overcurrent detection unit 320 generates an overcurrent signal. If the current in the first bridge arm 211 continues to be too large, causing further damage, the first bridge arm 211 is short-circuited, and the short-circuit detection unit 310 generates a short-circuit signal. The input end of the first AND gate U1 is electrically connected to the overcurrent detection unit 320 and the short-circuit detection unit 310, respectively. Only when the first bridge arm 211 is both overcurrent and short-circuited, the second bridge arm 212 is controlled to be turned off to avoid a busbar direct short circuit caused by the upper and lower bridge arms being turned on at the same time.

[0060] In some embodiments, the driving unit 330 further includes a second AND gate U2 and an OR gate U4. The first input end of the second AND gate U2 is connected to the overcurrent signal of the second bridge arm 212, and the second input end of the second AND gate U2 is connected to the driving signal GH_U of the second bridge arm 212; the first input end of the OR gate U4 is electrically connected to the output end of the first AND gate U1, the second input end of the OR gate U4 is electrically connected to the output end of the second AND gate U2, and the output end of the OR gate U4 is electrically connected to the driving end of the second bridge arm 212.

[0061] The first input end of the second AND gate U2 is connected to the overcurrent signal of the second bridge arm 212, and the overcurrent signal of the second bridge arm 212 can be a low level signal. The second input end of the second AND gate U2 is connected to the drive signal of the second bridge arm 212, and the drive signal of the second bridge arm 212 can be a PWM (Pulse Width Modulation) signal.

[0062] When the second bridge arm 212 is overcurrent, the first input terminal of the second AND gate U2 is connected to a low-level overcurrent signal. At this time, no matter whether the driving signal of the second bridge arm 212 is a high-level signal or a low-level signal, the second AND gate U2 outputs a low-level signal to drive the second bridge arm 212 to turn off. Similarly, when the first bridge arm 211 is overcurrent, the fault protection circuit 300 electrically connected to the second bridge arm 212 can drive the first bridge arm 211 to turn off.

[0063] The first input end of the OR gate U4 is electrically connected to the output end of the first AND gate U1, and the second input end of the OR gate U4 is electrically connected to the output end of the second AND gate U2. When the first bridge arm 211 is overcurrent and short-circuited or when the second bridge arm 212 is overcurrent, the output end of the OR gate U4 applies a shutdown signal to the driving end of the second bridge arm 212.

[0064] In some embodiments, the driving unit 330 further includes an inverter and a third AND gate U3. The input end of the inverter is electrically connected to the output end of the overcurrent detection unit 320; the first input end of the third AND gate U3 is electrically connected to the output end of the inverter, the second input end of the third AND gate U3 is connected to the overcurrent signal of the second bridge arm 212, and the output end of the third AND gate U3 is electrically connected to the input end of the first AND gate U1.

[0065] The first input end of the third AND gate U3 is connected to the inverted signal of the output signal of the overcurrent detection unit 320, that is, the first input end of the third AND gate U3 is connected to the inverted signal of the overcurrent signal of the first bridge arm 211, and the second input end of the third AND gate U3 is connected to the overcurrent signal of the second bridge arm 212. When the first bridge arm 211 is overcurrent and the second bridge arm 212 works normally, the third AND gate U3 outputs a high-level signal, and the output end of the third AND gate U3 is electrically connected to the first input end of the first AND gate U1. At this time, if the first bridge arm 211 is not short-circuited, the first input end and the second input end of the first AND gate U1 are both high-level signals, and the output end of the second AND gate U2 is also a high-level signal. Therefore, the output end of the OR gate U4 is a high-level signal, which drives the second bridge arm 212 to turn on, and the second bridge arm 212 enters the ASC (active short circuit) working mode.

[0066] As an example, the first bridge arm 211 is an upper bridge arm, and the second bridge arm 212 is a lower bridge arm. When the upper bridge arm is overcurrent and not short-circuited, and the lower bridge arm is normal, the first input end of the third AND gate U3 is connected to the DESAT pin signal P1_DESAT_L of the lower bridge arm driver chip, and the P1_DESAT_L signal is high when the lower bridge arm is normal. The second input end of the third AND gate U3 is connected to the DESAT pin signal P1_DESAT_H of the upper bridge arm driver chip, and when the upper bridge arm is overcurrent, the P1_DESAT_H signal is low, and the inverted signal P\1\_\D\E\S\A\T\_\H\ of P1_DESAT_H is high, and at this time, the output end of the third AND gate U3 outputs a high-level signal. When the upper bridge arm is not short-circuited, the short-circuit detection unit 310 outputs a high-level signal, so the output end of the second AND gate U2 outputs a high-level signal, that is, the first input end of the OR gate U4 is a high-level signal, so the OR gate U4 outputs a high-level signal to drive the lower bridge arm to turn on.

[0067] In some embodiments, the driving unit 330 further includes: a first resistor R1 and a capacitor C. The first end of the first resistor R1 is electrically connected to the output end of the third AND gate U3; the first end of the capacitor C is electrically connected to the second end of the first resistor R1, and the second end of the capacitor C is electrically connected to the ground node.

[0068] The first resistor R1 and the capacitor C are connected in series to form a delay circuit. When the first bridge arm 211 is overcurrent and not short-circuited, the fault protection circuit 300 electrically connected to the second bridge arm 212 drives the first bridge arm 211 to disconnect, and at the same time, the third AND gate U3 outputs a high-level signal to drive the second bridge arm 212 to turn on. After the high-level signal is delayed by the delay circuit, it can be ensured that the first bridge arm 211 is disconnected before the second bridge arm 212 is turned on, thereby avoiding the situation where the first bridge arm 211 and the second bridge arm 212 are in the on state at the same time.

[0069] In some embodiments, the short circuit detection unit 310 includes a first comparator A1. The positive input terminal of the first comparator A1 is connected to the bridge arm voltage of the first bridge arm 211, and the negative input terminal of the first comparator A1 is connected to a reference voltage, which is greater than the bridge arm voltage when the first bridge arm 211 is normally turned on.

[0070] When the IGBT is short-circuited, it will not enter the desaturation state, the voltage VCE between the collector and emitter of the IGBT is close to zero voltage, and the reference voltage is greater than the bridge arm voltage when the first bridge arm 211 is normally turned on, that is, the reference voltage is greater than zero voltage. When VCE is greater than the reference voltage, it means that the bridge arm where the IGBT is located is not short-circuited, and the first comparator A1 outputs a high-level signal. When VCE is less than the reference voltage, it means that the bridge arm where the IGBT is located is short-circuited, and the first comparator A1 outputs a low-level signal.

[0071] In some embodiments, the fault protection circuit 300 includes: a second resistor R2, an isolation amplifier chip U5, and a third resistor R3. The first end of the second resistor R2 is electrically connected to the first end of the first bridge arm 211; the input end of the isolation amplifier chip U5 is electrically connected to the second end of the second resistor R2, and the output end of the isolation amplifier chip U5 is electrically connected to the short circuit detection unit 310; the first end of the third resistor R3 is electrically connected to the second end of the second resistor R2 and the input end of the isolation amplifier chip U5, respectively, and the second end of the third resistor R3 is electrically connected to the second end of the first bridge arm 211.

[0072] The second resistor R2 and the third resistor R3 are connected in series to divide the voltage at both ends of the first bridge arm 211. The isolation amplifier chip U5 is electrically connected to both ends of the third resistor R3, and is mainly used to amplify the voltage divided by the third resistor R3. The second resistor R2, the isolation amplifier chip U5 and the third resistor R3 together form a voltage acquisition circuit to amplify the voltage of the switch tube and transmit it to the short circuit detection unit 310 for short circuit detection.

[0073] like Figure 4 As shown, in some embodiments, the bridge arm circuit 210 is electrically connected between the positive bus and the negative bus, and the fault protection circuit 300 further includes: a second comparator A2, a fourth resistor R4, and a fifth resistor R5. The positive phase input terminal of the second comparator A2 is connected to the bus voltage between the positive bus and the negative bus, the negative phase input terminal of the second comparator A2 is connected to the bridge arm voltage of the second bridge arm 212, and the output terminal of the second comparator A2 is electrically connected to the short circuit detection unit 310; the first end of the fourth resistor R4 is electrically connected to the positive phase input terminal, and the second end of the fourth resistor R4 is electrically connected to the ground node; the first end of the fifth resistor R5 is electrically connected to the negative phase input terminal of the second comparator A2, and the second end of the fifth resistor R5 is electrically connected to the output terminal of the second comparator A2.

[0074] In some embodiments, the voltage acquisition circuit in the aforementioned embodiments may be used to respectively acquire the bus voltage between the positive bus and the negative bus and the bridge arm voltage of the second bridge arm 212 .

[0075] The fault protection circuit 300 may further include a sixth resistor R6 and a seventh resistor R7, wherein the sixth resistor R6 is electrically connected to the non-inverting input terminal of the second comparator A2, and the seventh resistor R7 is electrically connected to the inverting input terminal of the second comparator A2. The second comparator A2, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 together form a subtractor circuit. The input terminal of the subtractor circuit is respectively connected to the bus voltage and the bridge arm voltage of the second bridge arm 212, and the output terminal of the subtractor circuit is the difference between the bus voltage and the bridge arm voltage of the second bridge arm 212, that is, the bridge arm voltage of the first bridge arm 211.

[0076] By using a subtractor circuit, it is only necessary to collect the bus voltage and the voltage of a certain bridge arm in the bridge arm circuit 210 to obtain the bridge arm voltage of the opposite bridge arm. In the three-phase bridge arm circuit 210, it is only necessary to collect the bus voltage and the voltage of a certain bridge arm in each phase to obtain the voltage of each bridge arm, thereby reducing the loops that need to be sampled and saving costs.

[0077] like Figure 4-6 As shown, as an example, the positive input terminal of the second comparator A2 is connected to the bus voltage VBUS_DSP between the positive bus and the negative bus, the negative input terminal of the second comparator A2 is connected to the bridge arm voltage VUL_DSP of the lower bridge arm, the output terminal of the second comparator A2 is electrically connected to the overcurrent detection unit 320, and the voltage output by the output terminal of the second comparator A2 is the bridge arm voltage VUL_DSP of the upper bridge arm.

[0078] An embodiment of the present application provides a power conversion circuit 200 , including a three-phase inverter circuit and the aforementioned fault protection circuit 300 , wherein a bridge arm in the three-phase inverter circuit is electrically connected to the fault protection circuit 300 .

[0079] The three-phase inverter circuit includes three bridge arm circuits 210 connected in parallel. The upper bridge arm and the lower bridge arm of each phase in the three-phase inverter circuit are respectively electrically connected to the fault protection circuit 300. The structure and principle of the fault protection circuit 300 can refer to the above embodiment and will not be repeated here.

[0080] According to the power conversion circuit 200 of the present application, when a bridge arm of the three-phase inverter circuit has an overcurrent, the overcurrent detection unit 320 electrically connected to the bridge arm provides an overcurrent signal. When a bridge arm of the bridge arm circuit 210 has a short circuit, the short circuit detection unit 310 provides a short circuit signal. When the driving unit 330 receives the overcurrent signal and the short circuit signal of the same bridge arm, that is, when a bridge arm has an overcurrent and a short circuit, it drives the bridge arm on the opposite side to turn off, so as to avoid a busbar direct short circuit caused by the upper and lower bridge arms being turned on at the same time.

[0081] An embodiment of the present application provides a vehicle, which includes a battery, a motor 100 and the aforementioned power conversion circuit 200, wherein the battery is electrically connected to a DC bus, the DC side of the power conversion circuit 200 is electrically connected to the DC bus, and the AC side of the power conversion circuit 200 is electrically connected to the motor 100.

[0082] The positive electrode of the battery is electrically connected to the positive bus, and the negative electrode of the battery is electrically connected to the negative bus. The power conversion circuit 200 is mainly used to convert the electric energy of the DC side battery into AC power to drive the motor 100 to work. The vehicle may include multiple motors 100, and each motor 100 is electrically connected to the corresponding power conversion circuit 200. The power conversion circuit 200 includes the aforementioned three-phase inverter circuit, and the upper bridge arm and the lower bridge arm of each phase in the three-phase inverter circuit are electrically connected to the fault protection circuit 300 respectively. The structure and principle of the fault protection circuit 300 can refer to the aforementioned embodiment and will not be repeated here.

[0083] According to the vehicle of the present application, when a bridge arm of the three-phase inverter circuit in the power conversion circuit 200 has an overcurrent, the overcurrent detection unit 320 electrically connected to the bridge arm provides an overcurrent signal; when a bridge arm of the bridge arm circuit 210 has a short circuit, the short circuit detection unit 310 provides a short circuit signal; when the driving unit 330 receives the overcurrent signal and the short circuit signal of the same bridge arm, that is, when a bridge arm has an overcurrent and a short circuit, the driving unit 330 drives the opposite bridge arm to shut down, so as to avoid a busbar direct short circuit caused by the simultaneous conduction of the upper and lower bridge arms.

[0084] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A fault protection circuit, characterized in that: Applied to a bridge arm circuit, the bridge arm circuit includes an upper bridge arm and a lower bridge arm connected in series, and the fault protection circuit includes: a short-circuit detection unit, electrically connected to the first bridge arm and configured to provide a short-circuit signal when a short circuit is detected in the first bridge arm, wherein the first bridge arm is the upper bridge arm or the lower bridge arm; an overcurrent detection unit, electrically connected to the first bridge arm and configured to provide an overcurrent signal when an overcurrent is detected in the first bridge arm; The driving unit is electrically connected to the bridge arm circuit, the overcurrent detection unit and the short-circuit detection unit respectively, and is configured to drive the second bridge arm to turn off when receiving the overcurrent signal and the short-circuit signal, and the second bridge arm is the opposite bridge arm of the first bridge arm.

2. The fault protection circuit according to claim 1, characterized in that: The driving unit comprises: A first AND gate, wherein a first input end of the first AND gate is electrically connected to the output end of the overcurrent detection unit, a second input end of the first AND gate is electrically connected to the output end of the short-circuit detection unit, and an output end of the first AND gate is electrically connected to the driving end of the second bridge arm.

3. The fault protection circuit according to claim 2, characterized in that: The driving unit further comprises: a second AND gate, wherein a first input terminal of the second AND gate is connected to the overcurrent signal of the second bridge arm, and a second input terminal of the second AND gate is connected to the driving signal of the second bridge arm; An OR gate, wherein a first input terminal of the OR gate is electrically connected to an output terminal of the first AND gate, a second input terminal of the OR gate is electrically connected to an output terminal of the second AND gate, and an output terminal of the OR gate is electrically connected to a driving terminal of the second bridge arm.

4. The fault protection circuit according to claim 2, characterized in that: The driving unit further comprises: An inverter, wherein an input end of the inverter is electrically connected to an output end of the overcurrent detection unit; A third AND gate, wherein a first input terminal of the third AND gate is electrically connected to the output terminal of the inverter, a second input terminal of the third AND gate is connected to the overcurrent signal of the second bridge arm, and an output terminal of the third AND gate is electrically connected to an input terminal of the first AND gate.

5. The fault protection circuit according to claim 4, characterized in that: The driving unit further comprises: a first resistor, wherein a first end of the first resistor is electrically connected to an output end of the third AND gate; A capacitor, a first end of the capacitor is electrically connected to the second end of the first resistor, and a second end of the capacitor is electrically connected to a ground node.

6. The fault protection circuit according to any one of claims 1 to 5, characterized in that: The short circuit detection unit comprises: A first comparator, wherein a positive input terminal of the first comparator is connected to the bridge arm voltage of the first bridge arm, and a negative input terminal of the first comparator is connected to a reference voltage, and the reference voltage is greater than the bridge arm voltage when the first bridge arm is normally turned on.

7. The fault protection circuit according to any one of claims 1 to 5, characterized in that: The fault protection circuit further comprises: a second resistor, a first end of the second resistor being electrically connected to the first end of the first bridge arm; an isolation operational amplifier chip, wherein an input end of the isolation operational amplifier chip is electrically connected to the second end of the second resistor, and an output end of the isolation operational amplifier chip is electrically connected to the short-circuit detection unit; A third resistor, wherein a first end of the third resistor is electrically connected to the second end of the second resistor and the input end of the isolation operational amplifier chip respectively, and a second end of the third resistor is electrically connected to the second end of the first bridge arm.

8. The fault protection circuit according to any one of claims 1 to 5, characterized in that: The bridge arm circuit is electrically connected between the positive bus and the negative bus, and the fault protection circuit further includes: A second comparator, wherein a positive phase input terminal of the second comparator is connected to a bus voltage between the positive bus and the negative bus, a negative phase input terminal of the second comparator is connected to a bridge arm voltage of the second bridge arm, and an output terminal of the second comparator is electrically connected to the short circuit detection unit; a fourth resistor, wherein a first end of the fourth resistor is electrically connected to the non-inverting input terminal, and a second end of the fourth resistor is electrically connected to a ground node; A fifth resistor, wherein a first end of the fifth resistor is electrically connected to the negative phase input end of the second comparator, and a second end of the fifth resistor is electrically connected to the output end of the second comparator.

9. A power conversion circuit, characterized in that: It comprises a three-phase inverter circuit and a fault protection circuit according to any one of claims 1 to 8, wherein a bridge arm in the three-phase inverter circuit is electrically connected to the fault protection circuit.

10. A vehicle, characterized in that: It comprises a battery, a motor and a power conversion circuit according to claim 9, wherein the battery is electrically connected to a DC bus, the DC side of the power conversion circuit is electrically connected to the DC bus, and the AC side of the power conversion circuit is electrically connected to the motor.

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