Integrated circuit

Abstract

An integrated circuit includes a substrate having a first active region and a second active region separated by a dielectric isolation region. A first fin is present in the first active region, the first fin including a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. A second fin is present in the second active region, the second fin including a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. The longer first portion of the first fin and the longer first portion of the second fin are in line with each other. The shorter second portion of the first fin and the shorter second portion of the second fin are parallel to each other.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit. Background Art

[0002] Integrated circuits are formed on semiconductor wafers. A lithographic patterning process uses ultraviolet light to transfer the desired mask pattern to a photoresist on the semiconductor wafer. An etching process can then be used to transfer the pattern to the layers below the photoresist. This process is repeated many times with different patterns to build up different layers on the wafer substrate and make useful devices.

[0003] However, conventional lithography processes can no longer meet the requirements of critical dimension (CD) (such as 10 nanometers (nm) or less) and pattern density in integrated circuits. Mandrel-spacer technology is often used in advanced lithography to reduce the pitch of the final pattern to half of the original mask pattern. Utility Model Content

[0004] Some embodiments of the present disclosure are directed to an integrated circuit, the integrated circuit comprising a substrate having a first active region and a second active region separated by a dielectric isolation region. A first fin is present in the first active region, the first fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. A second fin is present in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. The longer first portion of the first fin and the longer first portion of the second fin are in line with each other. The shorter second portion of the first fin and the shorter second portion of the second fin are parallel to each other.

[0005] Some embodiments of the present disclosure are directed to an integrated circuit, the integrated circuit comprising a substrate having a first active region and a second active region separated by a dielectric isolation region. A first fin is present in the first active region, the first fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. A second fin is present in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. The dielectric isolation region does not cover the shorter second portion of the first fin.

[0006] Some embodiments of the present disclosure are directed to an integrated circuit, the integrated circuit comprising a substrate having a first active region and a second active region separated by a dielectric isolation region. A first fin is present in the first active region, the first fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. A second fin is present in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. The shorter second portion of the first fin and the shorter second portion of the second fin are adjacent to the dielectric isolation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flow chart illustrating a method for forming a dielectric structure between two active regions by etching a mandrel and then etching a substrate in two separate process steps, rather than etching through the fin and substrate in one process step, according to some embodiments;

[0009] FIG. 2A to FIG. 2C Different views of the processing steps; Figure 2A For the plan view; Figure 2B is the X-axis view through line BB; Figure 2C is the Y-axis view through line CC;

[0010] FIG. 3A to FIG. 3C Different views of the processing steps; Figure 3A For the plan view; Figure 3B It is the X-axis view; Figure 3C It is the Y-axis view;

[0011] FIG. 4A to FIG. 4C Different views of the processing steps; Figure 4A For the plan view; Figure 4B It is the X-axis view; Figure 4C It is the Y-axis view;

[0012] FIG. 5A to FIG. 5C Different views of the processing steps; Figure 5A For the plan view; Figure 5B It is the X-axis view; Figure 5C It is the Y-axis view;

[0013] FIG. 6A to FIG. 6C Different views of the processing steps; Fig. 6A For the plan view; Figure 6B It is the X-axis view; Figure 6C It is the Y-axis view;

[0014] 7A to 7C Different views of the processing steps; Fig. 7A For the plan view; Figure 7B It is the X-axis view; Figure 7C It is the Y-axis view;

[0015] FIG. 8A to FIG. 8C Different views of the processing steps; Fig. 8A For the plan view; Figure 8B It is the X-axis view; Figure 8C It is the Y-axis view;

[0016] 9A to 9C Different views of the processing steps; Fig. 9A For the plan view; Fig. 9B It is the X-axis view; Fig. 9C It is the Y-axis view;

[0017] FIG. 10A to FIG. 10C Different views of the processing steps; Fig. 10A For the plan view; Fig. 10B It is the X-axis view; Fig. 10C It is the Y-axis view;

[0018] FIG. 11A to FIG. 11C Different views of the processing steps; Fig.11A For the plan view; Fig. 11B It is the X-axis view; Fig. 11C It is the Y-axis view;

[0019] FIG. 12A to FIG. 12C Different views of the processing steps; Fig. 12A For the plan view; Fig. 12B It is the X-axis view; Fig. 12C It is the Y-axis view;

[0020] FIG. 13A to FIG. 13C Different views of the processing steps; Fig.13A For the plan view; Fig. 13B It is the X-axis view; Fig. 13C It is the Y-axis view;

[0021] FIG. 14A to FIG. 14C for Figure 1 Different views of the processing steps in a first variant of the method; Fig.14A For the plan view; Fig. 14B It is the X-axis view; Fig. 14C It is the Y-axis view;

[0022] FIG. 15A to FIG. 15C Different views of the processing steps in the first variant; Fig.15A For the plan view; Fig. 15B It is the X-axis view; Fig. 15C It is the Y-axis view;

[0023] FIG. 16A to FIG. 16C for Figure 1 Different views of the processing steps in a second variant of the method; Fig.16A For the plan view; Fig. 16B It is the X-axis view; Fig. 16C It is the Y-axis view;

[0024] FIG. 17A to FIG. 17C Different views of the processing steps in the second variant; Fig.17A For the plan view; Fig. 17B It is the X-axis view; Fig. 17C It is the Y-axis view;

[0025] 18A to 18C for Figure 1 Different views of the processing steps in a third variant of the method; Fig.18A For the plan view; Fig.18B It is the X-axis view; Fig.18C It is the Y-axis view;

[0026] FIG. 19A to FIG. 19C Different views of the processing steps in the third variation; Fig.19A For the plan view; Fig.19B It is the X-axis view; Fig.19C It is the Y-axis view;

[0027] FIG. 20A to FIG. 20C Different views of the processing steps in the third variation; Fig. 20A For the plan view; Fig. 20B It is the X-axis view; Fig. 20C It is the Y-axis view;

[0028] FIG. 21A to FIG. 21C To illustrate different views of the final structure of the third variation in some embodiments; Fig.21A For the plan view; Fig. 21B It is the X-axis view; Fig. 21C It is the Y-axis view;

[0029] Fig. 22 A cross-sectional view through a substrate illustrating additional aspects of dielectric structures in some embodiments;

[0030] Fig.23A Plan view of a CPODE structure prepared in one etching step for comparison purposes;

[0031] Fig. 23B Schematic diagram of a CPODE structure prepared according to some embodiments of the methods disclosed herein.

[0032]

Explanation of symbols

[0033] 100: Method

[0034] 105,110,112,115,116,120,125,127,130,135,137,140,145,150,155,157: Steps

[0035] 200: Integrated Circuits

[0036] 202:Substrate

[0037] 203: Surface of substrate

[0038] 206: First Axis

[0039] 208: Second Axis

[0040] 210: First hard mask layer / pad oxide layer

[0041] 211: Thickness or depth of pad oxide layer

[0042] 212: Second hard mask layer / nitride layer

[0043] 213: Thickness or depth of nitride layer

[0044] 214: Third hard mask layer / covering oxide layer

[0045] 215: Thickness or depth of the covering oxide layer

[0046] 220: spindle

[0047] 222,224: Part

[0048] 226: spindle groove

[0049] 227: Width

[0050] 230: Photoresist layer

[0051] 231,232,233,234: Spacer

[0052] 235,236: Internal spacer

[0053] 237: External spacer

[0054] 241: First Fin

[0055] 242: Second fin

[0056] 243: Third Fin

[0057] 244:Fourth Fin

[0058] 245,246: Internal fins

[0059] 247: External fins

[0060] 248: Fin height

[0061] 249: Top of the fin

[0062] 252: First Active Zone

[0063] 254: Second active zone

[0064] 256: Dielectric structure / dielectric isolation region / CPODE structure

[0065] 257: Height

[0066] 259: Width of CPODE groove / Width of CPODE structure

[0067] 260: Fin Etch Mask

[0068] 262:CPODE Mask

[0069] 264: Spacer Etching Mask

[0070] 270:CPODE groove

[0071] 271: Depth

[0072] 280,282:Fin

[0073] 283: The first part of the fin

[0074] 285: The second part of the fin

[0075] 290:STI Zone

[0076] 291: STI Depth

[0077] 300: Fin

[0078] 302: Polysilicon area

[0079] 303: Width of polysilicon region DETAILED DESCRIPTION

[0080] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Components and configuration value specific examples are described below to simplify the disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0081] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another or some elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0082] The numerical values ​​in the specification and patent application range of this application should be understood to include the same numerical values ​​when reduced to the same significant figures and the numerical values ​​that differ from the stated values ​​by less than the experimental error of the conventional measurement technology of the type described in this application for determining the value. All ranges disclosed herein include the listed endpoints.

[0083] The term "about" can be used to include any numerical value that can be varied without changing the basic function of the value. When used with a range, "about" also discloses a range defined by the absolute values ​​of the two endpoints, for example, "about 2 to about 4" also discloses a range of "from 2 to 4". The term "about" can refer to ±10% of the indicated number.

[0084] The present disclosure is about structures composed of different layers. When the terms "on..." or "over..." or "over..." are used with reference to two different layers (including a substrate), they simply mean that one layer is on or above another layer. These terms do not require that the two layers are in direct contact with each other, and allow other layers to be located between the two layers. For example, all layers of a structure can be considered to be "on" a substrate, even if they are not all in direct contact with the substrate. The term "directly" can be used to indicate that two layers are in direct contact with each other without any layers between them.

[0085] The present disclosure relates to various methods for forming a continuous poly on diffusion edge (CPODE) structure. In this regard, a CPODE structure or pattern can be used as an electrical insulating or dielectric structure or feature on a wafer. This provides electrical isolation between adjacent active device regions (such as transistors). This may be useful for reducing parasitic capacitance between active device regions, thereby increasing processing speed. The CPODE structure can also be used as a vertical capacitor.

[0086] The present disclosure uses mandrel-spacer technology to form integrated circuit structures such as semiconductor devices or transistors. Such technology includes self-aligned double patterning (SADP), which halves the pitch of the exposed pattern. The method described herein reduces the depth / width ratio during etching, thereby allowing better etching process control and more stable device isolation performance.

[0087] Figure 1 1 is a flow chart illustrating a method 100 for forming a dielectric structure between two active regions in accordance with some embodiments. FIG. 2A to FIG. 13C Some steps of the method are also illustrated in FIG. These figures provide different views for better understanding. The figures with the A suffix, i.e. FIG. 2A to FIG. 13A , is a planar graph. A graph with a B suffix, i.e. FIG. 2B to FIG. 13B , for along Figure 2A The X-axis view of the line BB intercepted by . The figure with C suffix, that is Figures 2C to 13C , for along Figure 2A For ease of reference, lines BB and CC are repeated periodically throughout the figure.

[0088] First, in step 105, one or more hard mask layers are applied to the substrate. This is typically performed by depositing a suitable material. FIG. 2A to FIG. 2C , these figures show the starting state of the integrated circuit 200 before the CPODE structure is formed. The integrated circuit is built on a substrate 202. The substrate is typically a wafer made of a semiconductor material. Such material may include silicon, for example in the form of crystalline Si or polycrystalline Si. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In a specific embodiment, the wafer substrate is silicon.

[0089] Here, three hard mask layers 210, 212, 214 are shown as having been deposited on substrate 202. The first hard mask layer 210 directly contacting the substrate is a pad oxide layer. The oxide used to form the pad oxide layer may be, for example, silicon oxide, such as silicon dioxide (SiO 2 )、AlO x , HfO x 、ZrO xor other suitable materials. The pad oxide layer may be formed by thermal oxidation, PVD, CVD, ALD, oxidation, or other suitable deposition techniques. In some non-limiting examples, the pad oxide layer 210 may have a thickness or depth 211 from about 10 angstroms to about 30 angstroms, but other values ​​and ranges are also within the scope of the present disclosure.

[0090] The second hard mask layer 212 is a nitride layer deposited on the pad oxide layer 210. The nitride used to form the nitride layer may be, for example, silicon nitride or silicon oxynitride. The nitride layer may be formed by PVD, CVD, ALD, oxidation, or other suitable deposition techniques. In some specific embodiments, the nitride layer 212 may have a thickness or depth 213 from about 100 angstroms to about 1000 angstroms, but other values ​​and ranges are also within the scope of the present disclosure.

[0091] Finally, the third hard mask layer 214 is a capping oxide layer deposited on the nitride layer 212. The capping oxide layer can also be formed, for example, of silicon oxide, such as silicon dioxide (SiO 2 )、AlO x , HfO x 、ZrO x or other suitable materials. Likewise, the capping oxide layer may be formed by thermal oxidation, PVD, CVD, ALD, oxidation, or other suitable deposition techniques. In some specific embodiments, the capping oxide layer 214 may have a thickness or depth 215 from about 100 angstroms to about 1000 angstroms, but other values ​​and ranges are also within the scope of the present disclosure. The pad oxide layer 210, the nitride layer 212, and the capping oxide layer 214 together form a three-layer pattern etching system, which allows for better control of subsequent etching steps.

[0092] Next, let’s refer to Figure 1 Step 110 and FIG. 2A to FIG. 2C , one or more mandrels 220 are formed on the substrate 202. Each mandrel generally has a linear shape and extends in the direction of the first axis 206. Here, for simplicity, only one mandrel is illustrated.

[0093] The mandrels may be formed by depositing a layer of mandrel material, forming a photoresist layer over the mandrel material layer, exposing the photoresist to radiation and developing the photoresist layer to form a mandrel pattern, and then etching the mandrel material layer to form the mandrels.

[0094] The material used to form the mandrel may be, for example, a dielectric material such as silicon dioxide (SiO 2 )'s silicon oxide, a nitride such as silicon nitride or silicon oxynitride, polysilicon, a high-k dielectric material, or a low-k dielectric material.

[0095] The photoresist layer can be applied, for example, by spin coating or by spraying, roller coating, dip coating or extrusion coating. Typically, in spin coating, the substrate is placed on a rotating platform, which may include a vacuum chuck that holds the substrate in position. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to evenly diffuse the resist from the center of the substrate to the periphery of the substrate. The rotation speed of the platform is then fixed, which controls the thickness of the final photoresist layer.

[0096] The photoresist layer may then be baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90° C. to about 110° C., but other values ​​and ranges are also within the scope of the present disclosure. Baking may be performed using a hot plate or oven or similar equipment.

[0097] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light that carries the desired mask pattern. In a particular embodiment, EUV light having a wavelength of about 13.5 nm is used for patterning because this allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to the radiation while some portions of the photoresist layer are not exposed to the radiation. Such exposure results in some portions of the photoresist becoming soluble in the developer while other portions of the photoresist remain insoluble in the developer.

[0098] An additional resist bake step (post-exposure bake or PEB) may be performed after exposure to radiation. This may, for example, help release acid leaving groups (ALGs) or other molecules of interest in chemical amplification photoresists.

[0099] The photoresist layer is then developed using a developer. The developer may be an aqueous solution or an organic solution. The soluble portion of the photoresist layer is dissolved and washed away during the development step, leaving behind a photoresist pattern. An example of a common developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developers may include 2-heptanone, n-butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl 2-hydroxyisobutyrate, ethyl lactate or propylene glycol methyl ether acetate, n-amyl acetate, n-butyl propionate, n-hexyl acetate, n-butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-hexanone, propyl isobutyrate or isobutyl propionate. In general, any suitable developer may be used. Sometimes, a post-development bake or "hard bake" may be performed to stabilize the developed photoresist pattern so as to achieve optimal performance in subsequent steps.

[0100] Generally speaking, any etching step used herein may be performed using wet etching, dry etching, or plasma etching processes such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or a combination thereof, as appropriate. The etching may be anisotropic. Depending on the material, the etchant may include carbon tetrafluoride (CF 4 ), hexafluoroethane (C 2 F 6 ), octafluoropropane (C 3 F 8 ), fluoroform (CHF 3 ), difluoromethane (CH 2 F 2 ), fluoromethane (CH 3 F), trifluoromethane (CHF 3 ), carbon fluoride, nitrogen (N 2 ), hydrogen (H 2 ), oxygen (O 2 ), argon (Ar), xenon (Xe), xenon difluoride (XeF 2 ), helium (He), carbon monoxide (CO), carbon dioxide (CO 2 ), fluorine (F 2 ), chlorine (Cl 2 ), oxygen (O 2 ), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), boron trichloride (BCl 3 ), ammonia (NH 3 ), bromine (Br 2 ) or the like, or combinations thereof in various ratios. For example, hydrofluoric acid and ammonium fluoride may be used to wet etch silicon dioxide. Alternatively, CHF 3 , O 2 CF 4 and / or H 2 Silicon dioxide is dry etched using various mixtures of

[0101] Next, in Figure 1 In step 112, a first mask is applied over the mandrel(s). This can be done by applying another photoresist layer and patterning it. The result of this step is shown in FIG. 3A to FIG. 3C As can be seen here, the photoresist layer 230 is patterned so that a portion of the mandrel is exposed along a second axis 208 that is perpendicular (i.e., substantially orthogonal) to the first axis 206. This portion of the mandrel corresponds to the desired location of the dielectric structure to be formed. The remainder of the mandrel is covered by the photoresist layer.

[0102] exist Figure 1 In step 115, the exposed portion of the mandrel is etched. The etching continues until the third hard mask layer 214. In step 116, the first mask is removed. The photoresist can be removed, for example, at high temperature using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media or other strippers or by dry etching using oxygen plasma. The resulting structure is shown in FIG. 4A to FIG. 4C As can be seen here, the mandrel 220 has now been divided into two parts 222, 224, which are separated by the mandrel groove 226. Figure 4C In some embodiments, the width 227 of the mandrel trench 226 may be about 30 nanometers to about 50 nanometers, although other values ​​and ranges are also within the scope of the present disclosure.

[0103] Next, in Figure 1 In step 120, spacers are formed on the sidewalls of the mandrel 220. The spacers may be made of a dielectric material such as titanium nitride (TiN), silicon nitride (SiN), or titanium oxide. The spacers may be formed, for example, by deposition such as CVD or PVD, followed by etching to remove the horizontal material and leave only the sidewalls.

[0104] The resulting structure is shown in FIG. 5A to FIG. 5C As illustrated here, there are a total of four spacers along the first axis, two spacers 231, 233 around the mandrel portion 222, and two spacers 232, 234 around the mandrel portion 224. There are two inner spacers 235, 236 extending along the second axis adjacent to the mandrel groove 226. There are also two outer spacers 237 extending along the second axis at the distal end of the mandrel opposite the mandrel groove. Figure 5C , the width 227 of the mandrel trench is now narrower because it has been partially filled by the two inner spacers 235, 236, and in some embodiments is about 20 nm or more, but other values ​​and ranges are also within the scope of the present disclosure.

[0105] Next, in Figure 1 In step 125, the mandrel is removed. The two mandrel portions can be removed, for example, by etching. The resulting structure is shown in FIG. 6A to FIG. 6C middle.

[0106] Then, in step 130, an etch is performed to transfer the spacer pattern into the substrate 202 through the hard mask layers 210, 212, 214 and form the fins. An appropriate and suitable etchant is used to etch through the layers. It should be noted that due to the SADP process, the fin pitch is half the pitch of the original mask pattern used to form the mandrels.

[0107] In step 135, the spacers are removed. The hard mask layer is also removed. The resulting structure is shown in 7A to 7CAs illustrated here, the structure can be described as being composed of a total of four fins extending along the first axis 206. The first fin 241 and the second fin 242 are in a straight line in their length. The third fin 243 is also in a straight line in their length with the fourth fin 244. The first fin 241 and the third fin 243 are parallel to each other, and their ends are aligned with each other. The second fin 242 and the fourth fin 244 are parallel to each other, and their ends are aligned with each other. Using the mandrel groove 226 as a reference, the first fin 241 and the third fin 243 can be considered to be located in the first active region 252 on the substrate 202. Similarly, the second fin 242 and the fourth fin 244 can be considered to be located in the second active region 254 on the substrate 202.

[0108] Two inner fins 245, 246 extend along the second axis adjacent to the mandrel groove 226. These inner fins can also be described as a set or a plurality of fins extending along the second axis 208. There are also two outer fins 247 extending along the second axis spaced apart from the mandrel groove 226. The fins 241, 243, 245 are located in the first active region 252. The fins 242, 244, 246 are located in the second active region 254.

[0109] Next, in step 137, whichever is more appropriate, FIG. 8A to FIG. 8C As illustrated, a fin etch mask 260 is formed that exposes the third fin 243 and the fourth fin 244. Ideally, the fin etch mask 260 also exposes the outer fin 247. In some embodiments, a portion of the inner fins 245, 246 may also be exposed (along the X-axis or Y-axis). It should be noted that the pitch of the fins is half of the pitch possible with a separate mask pattern, so the width of the exposed area is necessarily greater than the width of the fins themselves. Etching is then performed to remove the third fin 243 and the fourth fin 244 and potentially some portions of the inner fins. It should be noted that although some portions of the substrate 202 are also exposed (see Figure 8B ), but generally speaking, the third fin 243 and the fourth fin 244 will be etched faster than the substrate 202 due to the larger exposed surface area of ​​these fins (three sides of the fins are exposed) compared to the exposed surface area of ​​the substrate.

[0110] After removing the fin etch mask, the resulting structure is shown in 9A to 9C The resulting structure can be described as including a first fin 241, a second fin 242, and inner fins 245, 246 extending along the second axis. Due to process control limitations, it is not always possible to ensure that the inner fins 245, 246 are completely etched away.

[0111] Next, refer to Figure 1 Step 140 and FIG. 10A to FIG. 10C, forming a CPODE mask 262 that exposes the substrate 202 between the fins 245, 246 extending along the second axis 208. As illustrated here, the inner fins 245, 246 are covered by the CPODE mask 262, but this is not required. The exposed area of ​​the substrate 202 corresponds to the same location as the mandrel groove 226.

[0112] Reference now Figure 1 Step 145 and FIG. 11A to FIG. 11C , etching is performed into the substrate 202 through the CPODE mask 262 to form a trench 270 in the substrate 202 .

[0113] Then, if Figure 1 Step 150 and FIG. 12A to FIG. 12C As can be seen, the trench 270 is filled with a dielectric material to form a dielectric structure or dielectric isolation region 256 between the first active region 252 and the second active region 254. The dielectric material is typically silicon oxide, but other dielectric materials such as undoped polysilicon, silicon nitride, silicon oxynitride, fluoride-doped silicate glass or other dielectric materials may also be used. Deposition may be performed using physical vapor deposition (PVD) or chemical vapor deposition (CVD) or spin coating processes known in the art. This dielectric structure 256 may also be referred to as a CPODE structure.

[0114] refer to FIG. 12A to FIG. 12C It should be noted that the trench is filled with dielectric material to at least the fin height 248. In other words, the dielectric structure 256 has a minimum total height 257 that corresponds to the sum of the trench depth 271 into the substrate and the fin height 248.

[0115] exist Figure 1 In step 155, the CPODE mask is removed. The resulting structure is shown in FIG. 13A to FIG. 13C . A dielectric structure or dielectric isolation region 256 is located between the first active region 252 and the second active region 254. Each active region 252, 254 can be described as including a fin 280, 282 consisting of a longer first portion 283 and a shorter second portion 285. The first portion 283 of each fin extends along a first axis, and the second portion 285 of each fin extends along a second axis. The longer first portions 283 of each fin 280, 282 are in line with each other. The shorter second portions 285 of each fin 280, 282 are parallel to each other along the Y axis, and their ends are aligned with each other. The shorter second portions 285 of each fin 280, 282 can also be described as being parallel to or bordering the dielectric isolation region 256.

[0116] It should be noted that, as illustrated here, the dielectric material of the dielectric structure 256 does not cover the shorter second portion 285 of the fin. However, other embodiments are contemplated in which the dielectric material covers the shorter second portion of the fin.

[0117] Figure 1 As indicated above, the third fin 243 and the fourth fin 244 are removed in the optional step 137, which occurs before the CPODE mask is formed. FIG. 8A to FIG. 8C However, if step 137 is not performed, the third fin 243 and the fourth fin 244 may be removed in an optional step 157 after the trench is filled with a dielectric material in step 150 .

[0118] If step 137 is not performed, the resulting structure after step 155 is FIG. 14A to FIG. 14C This is similar to 7A to 7C The structure shown, but with the addition of a dielectric structure 256. The four fins 241, 242, 243, 244 extend along the first axis 206. A pair of inner fins 245, 246 and an outer fin 247 extend along the second axis 208.

[0119] like Figure 1 As described in step 157 of FIG. 15A to FIG. 15C As shown, a fin etch mask 260 is formed to expose the third fin 243 and the fourth fin 244. Likewise, the fin etch mask 260 also ideally exposes the outer fin 247 and may also expose a portion of the inner fins 245 and 246. The third fin 243 and the fourth fin 244 are then etched away. After removing the fin etch mask 260, the final structure is similar to FIG. 13A to FIG. 13C Same as shown.

[0120] In another variation, instead of etching away the third and fourth fins, the spacers used to form these fins are etched away. This is indicated in optional step 127 and begins after the mandrel is removed, such as Figure 1 As discussed in step 125 of FIG. 6A to FIG. 6B exemplified.

[0121] Reference now FIG. 16A to FIG. 16C There are four spacers 231, 232, 233, 234 extending along the first axis. There are two inner spacers 235, 236 extending along the second axis adjacent to the mandrel groove 226. There are also two outer spacers 237 extending along the second axis at the distal end of the mandrel opposite the mandrel groove. Also refer to 7A to 7C, spacer 233 will eventually form third fin 243, spacer 234 will eventually form fourth fin 244, outer spacer 237 will eventually form outer fin 247, and inner spacers 235, 236 will eventually form inner fins 245, 246. A spacer etch mask 264 is formed to expose spacers 233, 234 formed on one sidewall of the mandrel. Ideally, the spacer etch mask also exposes outer spacer 237. Portions of inner spacers 235, 236 may also be exposed. The exposed spacers are then etched away. After removing the fin etch mask, the resulting structure is shown in FIG. FIG. 17A to FIG. 17C After the remaining process steps, the final structure will also be FIG. 13A to FIG. 13C Same as shown.

[0122] It should be noted that although steps 127, 137, and 157 are individually identified as Figure 1 The optional steps in the above are described below, but at least one of these steps must be performed to remove the third fin and the fourth fin.

[0123] The inner fins 245, 246 extending along the second axis may also be completely etched away. This may be done, for example, by appropriate patterning of the fin etch layer during any of the optional etching steps 127, 137 or 157.

[0124] Alternatively, when the dielectric structure is formed, the inner fins 245, 246 may be completely etched away during steps 140, 145 and 150. This variation is illustrated in 18A to 18C As seen here, the inner fins 245 , 246 along with the substrate therebetween are exposed by the CPODE mask 262 . FIG. 19A to FIG. 19C The resulting structure is illustrated after etching step 145. Note that because the inner fins are etched away, trench 270 may be deeper near its center than the area where the inner fins were previously located.

[0125] FIG. 20A to FIG. 20C The resulting structure after applying the dielectric material is illustrated. A dielectric isolation region 256 separates the first active region 252 and the second active region 254 .

[0126] FIG. 21A to FIG. 21C Here, the resulting fins 280 , 282 only extend along the first axis 206 , and no longer have any portion extending along the second axis 208 .

[0127] The CPODE structure is typically formed in one etch step where a continuous etch is performed through the fin and down into the substrate. Figure 1The method results in the location of the dielectric structure being etched in two different steps. The first etching step of the mandrel results in no fin being formed at all and is therefore equivalent to etching through the fin. The second etching step is performed while etching the substrate. As a result, the depth / width ratio of each individual etching step is significantly reduced, resulting in better process control and higher dielectric isolation. This allows the critical dimension (CD) width to be increased by up to twenty (20) nanometers (nm) in some cases. The etching process window is also expanded, as is the overlying window for small fin end-to-end spacing. Fin end-to-end losses are also reduced.

[0128] The disclosed method also allows the depth of the CPODE structure to be adjusted as needed through a combination of greater step etch rate control and ultra-more-etch (UME) depth. In addition, the depth of the overall CPODE structure can also be increased by about 10% to about 20%. This is Fig. 22 2 is illustrated in an exemplary cross-sectional view of the illustrated integrated circuit 200. The CPODE trench 270 is shown here together with a shallow trench isolation (STI) region 290. In some embodiments, the width 259 of the CPODE trench is from about 20 nm to about 30 nm, but other values ​​and ranges are also within the scope of the present disclosure. The STI region has a depth 291 measured from the surface 203 of the substrate 202 and into the substrate. The fin height 248 is also measured from the surface 203 of the substrate to the top 249 of the fin 241. In some embodiments, the fin height 248 can range from about 250 angstroms to about 600 angstroms, including from about 400 angstroms to about 500 angstroms, but other values ​​and ranges are also within the scope of the present disclosure. The CPODE depth 257 is measured from the top 249 of the fin to the bottom of the trench 270. In the disclosed method, the CPODE depth can be from about 1100 angstroms to about 1300 angstroms, but other values ​​and ranges are also within the scope of the present disclosure. This depth is approximately equal to the sum of the STI depth 291 and the fin height 248. When the CPODE structure is etched in one step, the CPODE depth is typically at least 100 angstroms less than the sum of the STI depth and the fin height. This ability to increase the depth of the CPODE structure using the disclosed method also improves the electrical isolation between the two active regions on either side of the CPODE structure.

[0129] Fig.23A and Fig. 23B The improvements in CPODE structure obtainable as a result of the methods of the present disclosure are generally illustrated. Fig.23Ais a plan view showing a CPODE structure obtained by one etching step. In conventional processes, a polysilicon region is used as a dummy gate layer. The dummy gate layer is removed, a trench is etched through the fin and substrate in one step, and a CPODE structure is produced by filling the etched trench and dummy gate region with a dielectric material. The previous figures depicted only one fin and one CPODE structure, while in this illustration, four continuous fins 300 extending from left to right are shown. Five polysilicon regions 302 extending from top to bottom are shown. Within the central polysilicon region is a CPODE structure 256. The width 259 of the CPODE structure is less than the width 303 of the polysilicon region and is approximately half the width of the polysilicon region.

[0130] Fig. 23B FIG. 2 is a plan view showing an example of the increase in width of a CPODE structure that can be obtained using the method of the present disclosure. Here, the fins 300 are illustrated as being cut in half along their length, as would occur in the method of the present disclosure. The width 259 of the CPODE structure is much larger and is almost equal to the width 303 of the polysilicon region.

[0131] The substrate with the CPODE structure can be further processed to obtain the desired integrated circuit. In addition, the processing steps of forming other structures on the substrate are omitted in the above discussion. FIG. 6A to FIG. 6C and 7A to 7C Before removing the hard mask layer, the STI region may have been formed between the fins. FIG. 13A to FIG. 13C Additional processing steps that may be performed after the CPODE structure is formed may include various doping, lithography, etching and deposition steps for forming source / drain regions, dummy gates or metal gates, interlayer dielectric (ILD) regions, etch stop layers, gate oxide layers, etc. required in transistors or other semiconductor devices.

[0132] Thus, some embodiments of the present disclosure relate to methods for forming a dielectric structure between a first active region and a second active region. A mandrel is formed on a substrate extending along a first axis. A first trench is formed in the mandrel along a second axis perpendicular to the first axis in a desired location of the dielectric structure. Spacers are formed on the sidewalls of the mandrel. The mandrel is then removed. Etching into the substrate to form at least a first fin extending along the first axis in the first active region, a second fin extending along the first axis in the second active region, and a plurality of fins extending along the second axis is then removed. The spacers are then removed. A CPODE mask is formed to expose the substrate between the fins extending along the second axis. A second trench is formed by etching into the substrate through the CPODE mask. The second trench is then filled with a dielectric material to at least the height of the fin to form a dielectric structure between the first active region and the second active region. In some embodiments, etching into the substrate also forms a third fin extending along the first axis in the first active region and a fourth fin extending along the first axis in the second active region, and the method further includes forming a fin etch mask exposing the third fin and the fourth fin, and etching to remove the third fin and the fourth fin. In some embodiments, the third fin and the fourth fin are removed before forming the CPODE mask or after filling the second trench with a dielectric material. In some embodiments, a portion of the fins extending along the second axis are also removed during etching to remove the third fin and the fourth fin. In some embodiments, the method further includes forming a spacer etch mask exposing at least one spacer formed on the sidewall of the mandrel extending along the first axis before removing the mandrel, and etching to remove the exposed at least one spacer. In some embodiments, the CPODE mask also exposes at least a portion of the fin extending along the second axis. In some embodiments, the fins extending along the second axis are not covered by the dielectric material forming the dielectric structure. In some embodiments, the dielectric structure has a depth of about 1100 angstroms to about 1300 angstroms. In some embodiments, the dielectric structure has a width of about 150 angstroms to about 400 angstroms.

[0133] The present disclosure also relates to an integrated circuit, the integrated circuit comprising a substrate having a first active region and a second active region separated by a dielectric isolation region. A first fin is present in the first active region, the first fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. A second fin is present in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. The longer first portion of the first fin and the longer first portion of the second fin are in line with each other. The shorter second portion of the first fin and the shorter second portion of the second fin are parallel to each other. In some embodiments, the shorter second portion of the first fin and the shorter second portion of the second fin border the dielectric isolation region. In some embodiments, the dielectric isolation region has a depth of about 1100 angstroms to about 1300 angstroms.

[0134] Other embodiments of the present disclosure are also related to methods for forming a first active region and a second active region. A mandrel is formed on a substrate. Etching is performed to form a first trench in the mandrel. Then etching is performed into the substrate to form a first fin and a third fin located in the first active region, a second fin and a fourth fin located in the second active region, and a plurality of shorter fins separating the first active region and the second active region. A fin etch mask is formed to expose the third fin and the fourth fin. Etching is performed to remove the third fin and the fourth fin. A CPODE mask is formed to expose the substrate between the shorter fins. Etching is performed into the substrate through the CPODE mask to form a second trench. The second trench is then filled with a dielectric material to form an isolation region between the first active region and the second active region. In some embodiments, the third fin and the fourth fin are removed before forming the CPODE mask or after filling the second trench with a dielectric material. In some embodiments, a portion of the shorter fins is also removed during etching to remove the third fin and the fourth fin. In some embodiments, the CPODE mask also exposes at least a portion of the shorter fins. In some embodiments, the shorter fins extending along the second axis are not covered by the dielectric material forming the isolation region. In some embodiments, the hard mask layer is located between the substrate and the mandrel. In some embodiments, the isolation region has a depth of about 1100 angstroms to about 1300 angstroms. In some embodiments, the isolation region has a width of about 20 nanometers to about 30 nanometers.

[0135] Some embodiments of the present disclosure relate to an integrated circuit, the integrated circuit comprising a substrate having a first active region and a second active region separated by a dielectric isolation region. A first fin is present in the first active region, the first fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. A second fin is present in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. The dielectric isolation region does not cover the shorter second portion of the first fin. In some embodiments, the dielectric isolation region does not cover the shorter second portion of the second fin. In some embodiments, an end of the shorter second portion of the first fin is aligned with an end of the shorter second portion of the second fin.

[0136] Some embodiments of the present disclosure relate to an integrated circuit, the integrated circuit comprising a substrate having a first active region and a second active region separated by a dielectric isolation region. A first fin is present in the first active region, the first fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. A second fin is present in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region. The shorter second portion of the first fin and the shorter second portion of the second fin are adjacent to the dielectric isolation region. In some embodiments, an end of the shorter second portion of the first fin is aligned with an end of the shorter second portion of the second fin. In some embodiments, the dielectric isolation region has a depth of 1100 angstroms to 1300 angstroms.

[0137] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, characterized in that: Include: a substrate having a first active region and a second active region separated by a dielectric isolation region; a first fin in the first active region, the first fin comprising a first longer portion perpendicular to the dielectric isolation region and a second shorter portion parallel to the dielectric isolation region; and A second fin located in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region; wherein the longer first portion of the first fin and the longer first portion of the second fin are in a straight line with each other; and The shorter second portion of the first fin and the shorter second portion of the second fin are parallel to each other.

2. The integrated circuit according to claim 1, wherein: The shorter second portion of the first fin and the shorter second portion of the second fin are adjacent to the dielectric isolation region.

3. The integrated circuit according to claim 1, wherein: The dielectric isolation region has a depth of 1100 angstroms to 1300 angstroms.

4. The integrated circuit according to claim 1, wherein: The dielectric isolation region has a width of 150 angstroms to 400 angstroms.

5. An integrated circuit, characterized in that: Include: a substrate having a first active region and a second active region separated by a dielectric isolation region; a first fin in the first active region, the first fin comprising a first longer portion perpendicular to the dielectric isolation region and a second shorter portion parallel to the dielectric isolation region; and A second fin is located in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region, wherein the dielectric isolation region does not cover the shorter second portion of the first fin.

6. The integrated circuit according to claim 5, characterized in that The dielectric isolation region does not cover the shorter second portion of the second fin.

7. The integrated circuit according to claim 6, characterized in that The end of the shorter second portion of the first fin is aligned with the end of the shorter second portion of the second fin.

8. An integrated circuit, characterized in that: Include: a substrate having a first active region and a second active region separated by a dielectric isolation region; a first fin in the first active region, the first fin comprising a first longer portion perpendicular to the dielectric isolation region and a second shorter portion parallel to the dielectric isolation region; and A second fin is located in the second active region, the second fin comprising a longer first portion perpendicular to the dielectric isolation region and a shorter second portion parallel to the dielectric isolation region, wherein the shorter second portion of the first fin and the shorter second portion of the second fin are bordered with the dielectric isolation region.

9. The integrated circuit according to claim 8, characterized in that The end of the shorter second portion of the first fin is aligned with the end of the shorter second portion of the second fin.

10. The integrated circuit according to claim 8, characterized in that The dielectric isolation region has a depth of 1100 angstroms to 1300 angstroms.

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