Interpolation filter and zero intermediate frequency architecture transmitter

Abstract

The utility model discloses an interpolation filter, which comprises a first time delay circuit of which the input end is connected with a first input signal and outputs a plurality of first time delay signals; the input end of the second time delay circuit is connected with a second input signal and outputs a plurality of second time delay signals; the multiplexing circuit is used for receiving the plurality of first delay signals and the plurality of second delay signals; the multiplexing circuit outputs the plurality of first delay signals or the plurality of second delay signals under the control of a selection signal; and the filter circuit is used for carrying out addition operation and multiplication operation on the plurality of first delay signals or the plurality of second delay signals and outputting a filtering result. According to the invention, the operation resources of the two filters are multiplexed (but the delay units are independent of each other), the area is greatly reduced on the premise that the channel performance is ensured, and the more the stages of the channel filters are, the more the order of each stage of filter is, the more the area is saved, and the more obvious the advantages of the structure are.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an interpolation filter and a zero intermediate frequency architecture transmitter. Background Art

[0002] In order to meet the increasing data demand of smartphone functions, the infrastructure of modern digital mobile communication must support wider bandwidth and faster data conversion. To achieve high-speed data rates, it has become a trend to integrate digital down converter (DDC) and digital up converter (DUC) channels in the converter system.

[0003] The zero-IF architecture converts the baseband directly into RF. Compared with the superheterodyne architecture, the zero-IF architecture reduces the use of IF and local oscillator RF circuits and IF filters. Therefore, the zero-IF architecture transmitter has the advantages of small size, low power consumption, and easy integration. Figure 3 As shown, in the first half of the transmission channel, that is, the end close to the baseband processor, the data sampling rate is low and the circuit operating clock frequency is low. At this time, the main consideration is how to reduce the area of ​​the interpolation filter circuit and how to maximize the performance of the transmitter while reducing the consumption of hardware resources. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present application is to provide a digital programmable gain integrated instrumentation amplifier to solve at least one problem existing in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the utility model provides an interpolation filter, the interpolation filter comprising:

[0006] A first delay circuit, whose input terminal is connected to a first input signal, performs at least one delay process on the first input signal, and outputs a plurality of first delay signals;

[0007] A second delay circuit, whose input terminal is connected to a second input signal, performs at least one delay process on the second input signal, and outputs a plurality of second delayed signals;

[0008] a multiplexing circuit, whose input end is electrically connected to the output end of the first delay circuit and the output end of the second delay circuit respectively, and receives the plurality of first delayed signals and the plurality of second delayed signals; the multiplexing circuit outputs the plurality of first delayed signals or the plurality of second delayed signals under the control of the selection signal;

[0009] The filter circuit has an input end electrically connected to an output end of the multiplexing circuit, performs addition and multiplication operations on the plurality of first delayed signals or the plurality of second delayed signals, and outputs a filtering result.

[0010] In one embodiment of the present application, the filtering circuit includes:

[0011] A first adding circuit, whose input end is electrically connected to the output end of the multiplexing circuit, adds the plurality of first delayed signals or the plurality of second delayed signals in pairs, and outputs a plurality of first addition operation results;

[0012] a multiplication circuit, whose input end is electrically connected to the output end of the first addition circuit, multiplies each of the plurality of addition operation results by a corresponding filter coefficient, and outputs a plurality of multiplication operation results;

[0013] The second adding circuit has an input end connected to the output end of the multiplying circuit, performs an addition operation on the multiple multiplication results, and outputs a second addition operation result.

[0014] In one embodiment of the present application, the first delay circuit includes multiple delay units, the second delay circuit includes multiple delay units, the multiplexing circuit includes multiple multiplexing units, and a multiplexing unit corresponds to connecting a delay unit of the first delay circuit and a delay unit of the second delay circuit; the first input signal and the second input signal are connected to the same multiplexing unit.

[0015] In one embodiment of the present application, the first delay circuit includes a first delay unit to a seventh delay unit, the second delay circuit includes an eighth delay unit to a fourteenth delay unit, the multiplexing circuit includes a first multiplexing unit to an eighth multiplexing unit, and the first multiplexing unit to the eighth multiplexing unit each include a first input terminal and a second input terminal;

[0016] The first input signal is connected to the first input terminal of the first multiplexing unit, and the second input signal is connected to the second input terminal of the first multiplexing unit;

[0017] The output end of the first delay unit is electrically connected to the first input end of the second multiplexing unit, and the output end of the eighth delay unit is electrically connected to the second input end of the second multiplexing unit;

[0018] The output end of the second delay unit is electrically connected to the first input end of the third multiplexing unit, and the output end of the ninth delay unit is electrically connected to the second input end of the third multiplexing unit;

[0019] The output end of the third delay unit is electrically connected to the first input end of the fourth multiplexing unit, and the output end of the tenth delay unit is electrically connected to the second input end of the fourth multiplexing unit;

[0020] The output end of the fourth delay unit is electrically connected to the first input end of the fifth multiplexing unit, and the output end of the eleventh delay unit is electrically connected to the second input end of the fifth multiplexing unit;

[0021] The output end of the fifth delay unit is electrically connected to the first input end of the sixth multiplexing unit, and the output end of the twelfth delay unit is electrically connected to the second input end of the sixth multiplexing unit;

[0022] The output end of the sixth delay unit is electrically connected to the first input end of the seventh multiplexing unit, and the output end of the thirteenth delay unit is electrically connected to the second input end of the seventh multiplexing unit;

[0023] The output end of the seventh delay unit is electrically connected to the first input end of the eighth multiplexing unit, and the output end of the fourteenth delay unit is electrically connected to the second input end of the eighth multiplexing unit.

[0024] In one embodiment of the present application, the first adding circuit includes a first adding unit to a fourth adding unit;

[0025] The output end of the first multiplexing unit and the output end of the eighth multiplexing unit are electrically connected to the first adding unit respectively;

[0026] The output end of the second multiplexing unit and the output end of the seventh multiplexing unit are electrically connected to the second adding unit respectively;

[0027] The output end of the third multiplexing unit and the output end of the sixth multiplexing unit are electrically connected to the third adding unit respectively;

[0028] An output end of the fourth multiplexing unit and an output end of the fifth multiplexing unit are electrically connected to the fourth adding unit respectively.

[0029] In an embodiment of the present application, the interpolation filter further includes: a ninth multiplexing unit and a tenth multiplexing unit having a third input terminal and a fourth input terminal;

[0030] The output end of the fourth delay unit is electrically connected to the third input end of the ninth multiplexing unit, and the output end of the second adding circuit is electrically connected to the fourth input end of the ninth multiplexing unit; the ninth multiplexing unit is electrically connected to the second adding circuit or the fourth delay unit under the control of the selection signal to form a signal path;

[0031] The output end of the eleventh delay unit is electrically connected to the third input end of the tenth multiplexing unit, and the output end of the second adding circuit is electrically connected to the fourth input end of the tenth multiplexing unit; the tenth multiplexing unit is electrically connected to the second adding circuit or the eleventh delay unit under the control of the selection signal to form a signal path.

[0032] In one embodiment of the present application, the interpolation filter further includes:

[0033] The third delay circuit has an input end electrically connected to the output end of the second adding circuit, and an output end electrically connected to the fourth input end of the ninth multiplexing unit.

[0034] In one embodiment of the present application, the interpolation filter further includes:

[0035] A first trigger, whose input end is electrically connected to the output end of the ninth multiplexing unit, and whose output end serves as one of the output ends of the interpolation filter;

[0036] The second trigger has an input end electrically connected to the output end of the tenth multiplexing unit, and an output end serving as another output end of the interpolation filter.

[0037] To achieve the above-mentioned purpose and other related purposes, the utility model provides a zero intermediate frequency architecture transmitter, including the above-mentioned interpolation filter.

[0038] As described above, the interpolation filter and zero intermediate frequency architecture transmitter provided by the present application have the following beneficial effects:

[0039] An interpolation filter of the present application includes: a first delay circuit, whose input end is connected to a first input signal, delays the first input signal at least once, and outputs a plurality of first delay signals; a second delay circuit, whose input end is connected to a second input signal, delays the second input signal at least once, and outputs a plurality of second delay signals; a multiplexing circuit, whose input end is electrically connected to the output end of the first delay circuit and the output end of the second delay circuit, respectively, and receives the plurality of first delay signals and the plurality of second delay signals; the multiplexing circuit outputs the plurality of first delay signals or the plurality of second delay signals under the control of a selection signal; a filtering circuit, whose input end is electrically connected to the output end of the multiplexing circuit, performs addition and multiplication operations on the plurality of first delay signals or the plurality of second delay signals, and outputs a filtering result. The present application greatly reduces the area under the premise of ensuring channel performance by multiplexing the computing resources of the two-way filter (but the delay units are independent of each other), and as the number of stages of the channel filter increases, the number of orders of each stage of the filter increases, the area saved by the present application increases, and the advantages of the structure of the present application become more obvious.

[0040] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0042] Figure 1 A circuit hardware structure diagram of an interpolation filter according to an embodiment of the present application;

[0043] Figure 2 A circuit simulation timing diagram of an interpolation filter according to an embodiment of the present application;

[0044] Figure 3 This is the structural block diagram of the zero intermediate frequency architecture transmitter. DETAILED DESCRIPTION

[0045] The following describes the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0046] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0047] Although the terms "first", "second", "A", "B", etc. may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the following technology. The term "and / or" includes a combination of multiple related items or any item in the multiple related items.

[0048] As used herein, unless the context indicates otherwise, the singular form is intended to include the plural form, and it will be understood that the term "comprising" means the presence of stated features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0049] Before describing the drawings in detail, it is intended to clarify that the division of components in this specification is divided only by the main function of each component. That is, two or more components to be described below can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main function of the component, each component to be described below can also perform some or all of the functions of other components, and some of the main functions of each component can be exclusively performed by other components.

[0050] In order to meet the increasing data demand of smartphone functions, the infrastructure of modern digital mobile communication must support wider bandwidth and faster data conversion. To achieve high-speed data rates, it has become a trend to integrate digital down converter (DDC) and digital up converter (DUC) channels in the converter system.

[0051] The zero-IF architecture converts the baseband directly into RF. Compared with the superheterodyne architecture, the zero-IF architecture reduces the use of IF and local oscillator RF circuits and IF filters. Therefore, the zero-IF architecture transmitter has the advantages of small size, low power consumption, and easy integration. Figure 3 This is a typical zero-IF transmitter block diagram:

[0052] 1. This architecture divides the signal into real and imaginary parts for transmission, effectively reducing baseband resource loss and improving spectrum utilization; 2. Since there is no intermediate frequency, the difficulty of filter design is reduced; 3. Since signal transmission is divided into orthogonal differential transmission, common mode interference is reduced.

[0053] from Figure 3 It can be seen that since the architecture divides the signal into real and imaginary parts for transmission, the corresponding digital signal processing (DSP) part of the transmitter is also divided into two channels: the in-phase (I) branch and the quadrature-phase (Q) branch. The processed signals are orthogonal to each other, that is, the phase difference of the processed signals is 90°.

[0054] In the first half of the transmission channel, that is, the end close to the baseband processor, the data sampling rate is low and the circuit operating clock frequency is low. At this time, the main consideration is how to reduce the area of ​​the interpolation filter circuit and how to maximize the performance of the transmitter while reducing the consumption of hardware resources.

[0055] In response to the above problems, the present application provides an interpolation filter, which mainly takes into account the characteristics of the zero-IF architecture transceiver that divides the signal into real and imaginary parts for transmission. By multiplexing the computing resources of the filters on two mutually orthogonal channels, the hardware structure is simplified and the consumption of hardware resources is significantly reduced while ensuring the performance of the transmitter to the greatest extent.

[0056] See also Figure 1 , Figure 1 FIG. 1 is a structural block diagram of an interpolation filter according to an embodiment of the present application. Figure 1 In the embodiment, the interpolation filter at least comprises: a first delay circuit 110, a second delay circuit 120, a multiplexing circuit 130 and a filtering circuit 140; wherein,

[0057] A first delay circuit 110, whose input terminal is connected to a first input signal, performs at least one delay process on the first input signal, and outputs a plurality of first delay signals;

[0058] A second delay circuit 120, whose input terminal is connected to a second input signal, performs at least one delay process on the second input signal, and outputs a plurality of second delayed signals;

[0059] A multiplexing circuit 130, whose input end is electrically connected to the output end of the first delay circuit and the output end of the second delay circuit respectively, receives the plurality of first delayed signals and the plurality of second delayed signals; the multiplexing circuit outputs the plurality of first delayed signals or the plurality of second delayed signals under the control of the selection signal;

[0060] The filter circuit 140 has an input end electrically connected to an output end of the multiplexing circuit, performs addition operations and multiplication operations on the multiple first delayed signals or the multiple second delayed signals, and outputs a filtering result.

[0061] The present application reuses the computing resources of the two filters (but the delay units are independent of each other), thereby greatly reducing the area while ensuring the channel performance. As the number of channel filters increases and the number of orders of each filter level increases, the present application saves more area and the advantages of the structure of the present application become more obvious.

[0062] The following is a detailed description of each module.

[0063] In one embodiment, the first delay circuit includes multiple delay units, the second delay circuit includes multiple delay units, the multiplexing circuit includes multiple multiplexing units, and a multiplexing unit corresponds to connecting a delay unit of the first delay circuit and a delay unit of the second delay circuit; the first input signal and the second input signal are connected to the same multiplexing unit.

[0064] See also Figure 1 , the first delay circuit includes a first delay unit to a seventh delay unit, the second delay circuit includes an eighth delay unit to a fourteenth delay unit, the multiplexing circuit includes a first multiplexing unit to an eighth multiplexing unit, and the first multiplexing unit to the eighth multiplexing unit each include a first input terminal and a second input terminal;

[0065] The first input signal din_I is connected to the first input terminal of the first multiplexing unit MUX1, and the second input signal din_Q is connected to the second input terminal of the first multiplexing unit MUX1;

[0066] The output end of the first delay unit Qi0 is electrically connected to the first input end of the second multiplexing unit MUX2, and the output end of the eighth delay unit Qq0 is electrically connected to the second input end of the second multiplexing unit MUX2;

[0067] The output end of the second delay unit Qi1 is electrically connected to the first input end of the third multiplexing unit MUX3, and the output end of the ninth delay unit Qq1 is electrically connected to the second input end of the third multiplexing unit MUX3;

[0068] The output end of the third delay unit Qi2 is electrically connected to the first input end of the fourth multiplexing unit MUX4, and the output end of the tenth delay unit Qq2 is electrically connected to the second input end of the fourth multiplexing unit MUX4;

[0069] The output end of the fourth delay unit Qi3 is electrically connected to the first input end of the fifth multiplexing unit MUX5, and the output end of the eleventh delay unit Qq3 is electrically connected to the second input end of the fifth multiplexing unit MUX5;

[0070] The output end of the fifth delay unit Qi4 is electrically connected to the first input end of the sixth multiplexing unit MUX6, and the output end of the twelfth delay unit Qq4 is electrically connected to the second input end of the sixth multiplexing unit MUX6;

[0071] The output end of the sixth delay unit Qi5 is electrically connected to the first input end of the seventh multiplexing unit MUX7, and the output end of the thirteenth delay unit Qq5 is electrically connected to the second input end of the seventh multiplexing unit MUX7;

[0072] The output end of the seventh delay unit Qi6 is electrically connected to the first input end of the eighth multiplexing unit MUX8, and the output end of the fourteenth delay unit Qq6 is electrically connected to the second input end of the eighth multiplexing unit.

[0073] See also Figure 1 , the filtering circuit comprises:

[0074] A first adding circuit 1401, whose input end is electrically connected to the output end of the multiplexing circuit, adds the multiple first delayed signals or the multiple second delayed signals in pairs, and outputs multiple first addition operation results;

[0075] a multiplication circuit 1402, whose input end is electrically connected to the output end of the first addition circuit, multiplies each of the plurality of addition operation results by a corresponding filter coefficient, and outputs a plurality of multiplication operation results;

[0076] The second adding circuit 1403 has an input end connected to the output end of the multiplication circuit, performs an addition operation on the multiple multiplication operation results, and outputs a second addition operation result.

[0077] Specifically, the first adding circuit includes a first adding unit to a fourth adding unit;

[0078] The output end of the first multiplexing unit MUX1 and the output end of the eighth multiplexing unit MUX8 are electrically connected to the first adding unit respectively; that is, the first adding unit performs an addition operation on the output of the first multiplexing unit MUX1 and the output of the eighth multiplexing unit MUX8;

[0079] The output end of the second multiplexing unit MUX2 and the output end of the seventh multiplexing unit MUX7 are electrically connected to the second adding unit respectively; that is, the second adding unit performs an addition operation on the output of the second multiplexing unit MUX2 and the output of the seventh multiplexing unit MUX7;

[0080] The output end of the third multiplexing unit MUX3 and the output end of the sixth multiplexing unit MUX6 are electrically connected to the third adding unit respectively; that is, the third adding unit performs addition operation on the output of the third multiplexing unit MUX3 and the output of the sixth multiplexing unit MUX6;

[0081] The output end of the fourth multiplexing unit MUX4 and the output end of the fifth multiplexing unit MUX5 are electrically connected to the fourth adding unit respectively; that is, the fourth adding unit performs addition operation on the output of the fourth multiplexing unit MUX4 and the output of the fifth multiplexing unit MUX5.

[0082] Continue reading Figure 1 , the interpolation filter further includes: a ninth multiplexing unit MUX_I and a tenth multiplexing unit MUX_Q having a third input terminal and a fourth input terminal;

[0083] The output end of the fourth delay unit Qi3 is electrically connected to the third input end of the ninth multiplexing unit MUX_I, and the output end of the second adding circuit is electrically connected to the fourth input end of the ninth multiplexing unit MUX_I; the ninth multiplexing unit MUX_I is electrically connected to the second adding circuit or the fourth delay unit under the control of the selection signal to form a signal path;

[0084] The output end of the eleventh delay unit Qq3 is electrically connected to the third input end of the tenth multiplexing unit MUX_Q, and the output end of the second adding circuit is electrically connected to the fourth input end of the tenth multiplexing unit MUX_Q; the tenth multiplexing unit MUX_Q is electrically connected to the second adding circuit or the eleventh delay unit under the control of the selection signal to form a signal path.

[0085] In one embodiment, the interpolation filter further includes:

[0086] The third delay circuit 150 has an input end electrically connected to the output end of the second adding circuit, and an output end electrically connected to the fourth input end of the ninth multiplexing unit MUX_I.

[0087] In one embodiment, the interpolation filter further includes:

[0088] A first trigger 160, whose input end is electrically connected to the output end of the ninth multiplexing unit MUX_I, and whose output end serves as one of the output ends of the interpolation filter;

[0089] The second trigger 170 has an input end electrically connected to the output end of the tenth multiplexing unit MUX_Q, and an output end thereof serving as another output end of the interpolation filter.

[0090] The present application is described in detail below using a double interpolation filter as an embodiment.

[0091] Assume that the coefficients of the filter in this embodiment are [-53, 0, 313, 0, -1155, 0, 4989, 8192, 4989, 0, -1155, 0, 313, 0, -53]. The input bit width of the filter is 14 bits, and the output bit width is also 14 bits.

[0092] The hardware circuit structure of the interpolation filter in the embodiment of the present application is as follows: Figure 1As shown, din_I and din_Q are the signals input into the filter by the I path and the Q path respectively. They pass through their respective delay circuits (i.e., the first delay circuit and the second delay circuit). The output of the delay circuit is sent to the filter circuit (the operation logic is multiplexed by the I and Q paths), and the results of the operation are synchronized and sent to dout_I and dout_Q outputs at the same time. The present application is a double interpolation filter, which inserts a 0 between every other sampling point. Therefore, the filter coefficients of this embodiment [-53, 0, 313, 0, -1155, 0, 4989, 8192, 4989, 0, -1155, 0, 313, 0, -53] correspond to the data of din_I [0, xi1, 0, xi2, 0, xi3, 0, xi4, 0, xi5, 0, xi6, 0, xi7, 0, xi8] multiplied and accumulated to obtain the interpolation filtering result dout_I of the I path; the corresponding data of din_Q [0, xq1, 0, xq2, 0, xq3, 0, xq4, 0, xq5, 0, xq6, 0, xq7, 0, xq8] are multiplied and accumulated to obtain the interpolation filtering result dout_Q of the Q path (note: the 0 is caused by double interpolation).

[0093] The specific timing arrangement of the embodiment of the present application is as follows Figure 2 As shown, after the data of din_I comes in, it is sent to the first delay unit Qi0, the second delay unit Qi1, the third delay unit Qi2, the fourth delay unit Qi3, the fifth delay unit Qi4, the sixth delay unit Qi5, and the seventh delay unit Qi6 for delay step by step, and after the data of din_Q comes in, it is sent to the eighth delay unit Qq0, the ninth delay unit Qq1, the tenth delay unit Qq2, the eleventh delay unit Qq3, the twelfth delay unit Qq4, the thirteenth delay unit Qq5, and the fourteenth delay unit Qq6 for delay step by step.

[0094] The input signals of the I and Q channels and their respective delayed results are sent to the multiplexing units MUX1 to MUX8, and the selection signal S is used to determine which channel of data is sent to the filter circuit for filtering operation within a certain period of time.

[0095] Send din_I to the entry 0 of the first multiplexing unit MUX1, and send din_Q to the entry 1 of the first multiplexing unit MUX1;

[0096] Send the first delay unit Qi0 to the entry 0 of the second multiplexing unit MUX2, and send the eighth delay unit Qq0 to the entry 1 of the second multiplexing unit MUX2;

[0097] Send the second delay unit Qi1 to the entry 0 of the third multiplexing unit MUX3, and send the ninth delay unit Qq1 to the entry 1 of the third multiplexing unit MUX3;

[0098] Send the third delay unit Qi2 to the entry 0 of the fourth multiplexing unit MUX4, and send the tenth delay unit Qq2 to the entry 1 of the fourth multiplexing unit MUX4;

[0099] Send the fourth delay unit Qi3 to the entry 0 of the fifth multiplexing unit MUX5, and send the eleventh delay unit Qq3 to the entry 1 of the fifth multiplexing unit MUX5;

[0100] Send the fifth delay unit Qi4 to the entry 0 of the sixth multiplexing unit MUX6, and send the twelfth delay unit Qq4 to the entry 1 of the sixth multiplexing unit MUX6;

[0101] Send the sixth delay unit Qi5 to the entry 0 of the seventh multiplexing unit MUX7, and send the thirteenth delay unit Qq5 to the entry 1 of the seventh multiplexing unit MUX7;

[0102] Send the seventh delay unit Qi6 to the entry 0 of the eighth multiplexing unit MUX8, and send the fourteenth delay unit Qq6 to the entry 1 of the eighth multiplexing unit MUX8;

[0103] It should be noted that the above-mentioned entry 0 refers to the first input terminal, and the entry 1 refers to the second input terminal. Of course, in another embodiment, the entry 0 may refer to the second input terminal, and the entry 1 may refer to the first input terminal. The specific port usage may be set differently according to actual needs, and no limitation is imposed on the port setting here.

[0104] When the selection signal S=0, the outputs of the first multiplexing unit MUX1 to the eighth multiplexing unit MUX8 are din_I, Qi0, Qi1, Qi2, Qi3, Qi4, Qi5, and Qi6, and the I-path signal is filtered; when the selection signal S=1, the outputs of the first multiplexing unit MUX1 to the eighth multiplexing unit MUX8 are din_Q, Qq0, Qq1, Qq2, Qq3, Qq4, Qq5, and Qq6, and the Q-path signal is filtered.

[0105] The operation result dout is sent to the entry 1 of the tenth multiplexing unit MUX_Q of the Q path, and after dout is delayed by a trigger (second delay circuit) for a clk_in2 cycle, the delayed result dout_d is sent to the entry 1 of the ninth multiplexing unit MUX_I of the I path. It should be noted that the entry 0 of the ninth multiplexing unit MUX_I is directly connected to the output of the fourth delay unit Qi3, and the entry 0 of the tenth multiplexing unit MUX_Q is directly connected to the output of the eleventh delay unit Qq3. When the selection signal S=1, the output of the ninth multiplexing unit MUX_I is dout_d, and the output of the tenth multiplexing unit MUX_Q is dout; when the selection signal S=0, the output of the ninth multiplexing unit MUX_I is Qi3, and the output of the tenth multiplexing unit MUX_Q is Qq3. After the output results of the ninth multiplexing unit MUX_I and the tenth multiplexing unit MUX_Q pass through a first-level trigger, their respective results are output to dout_I and dout_Q at the same time. The trigger signal of the first-stage trigger is the output clock of the interpolation filter, and its frequency is twice the frequency of the input data clock.

[0106] It should be noted here that, for the ninth multiplexing unit MUX_I and the tenth multiplexing unit MUX_Q, the entry 0 refers to the third input terminal, and the entry 1 refers to the fourth input terminal.

[0107] Next, attach Figure 1 The connection mode is explained as follows: the entry 0 of the ninth multiplexing unit MUX_I is directly connected to the output of the fourth delay unit Qi3, and the entry 0 of the tenth multiplexing unit MUX_Q is directly connected to the output of the eleventh delay unit Qq3.

[0108] Taking the case of I as an example, when the data [xi1, xi2, xi3, xi4, xi5, xi6, xi7, xi8, ...] passes through the double interpolation filter, it is first interpolated to [0, xi1, 0, xi2, 0, xi3, 0, xi4, 0, xi5, 0, xi6, 0, xi7, 0, xi8, ...], and then the data with 0 interpolation is filtered with the filter with coefficients of [-53, 0, 313, 0, -1155, 0, 4989, 8192, 4989, 0, -1155, 0, 313, 0, -53], and finally the result of interpolation filtering is obtained, which is the output dout_I of this application.

[0109] So the first result of I output dout_I is 0*(-53)+xi1*(0)+0*(313)+xi2*(0)+0*(-1155)+xi3*(0)+0*(4989)+xi4*(8192)+0*(4989)+xi5*(0)

[0110] +0*(-1155)+xi6*(0)+0*(313)+xi7*(0)+0*(-53)=xi4*(8192)

[0111] The second result is xi1*(-53)+0*(0)+xi2*(313)+0*(0)+xi3*(-1155)+0*(0)+xi4*(4989)+0*(8192)+xi5*(4989)+0*(0)+xi6*(-1155)+0*(0)+xi7*(313)+0*(0)+xi8*(-53)=xi1*(-53)+xi2*(313)+xi3*(-1155)+xi4*(4989)+0*(8192)+xi5*(4989)+xi6*(-1155)+xi7*(313)+xi8*(-53)

[0112] The third result is 0*(-53)+xi2*(0)+0*(313)+xi3*(0)+0*(-1155)+xi4*(0)+0*(4989)+xi5*(8192)+0*(4989)+xi6*(0)+0*(-1155)+xi7*(0)

[0113] +0*(313)+xi8*(0)+0*(-53)=xi5*(8192)

[0114] It can be seen that the third result output by the present application has the same form as the output and the first result of the present application. After writing out the formulas of more results, we can find that the output of the present application has only two forms. One is like the second result, that is, the result after din_I, Qi0, Qi1, Qi2, Qi3, Qi4, Qi5, and Qi6 are calculated and sent to the entry 1 of the ninth multiplexing unit MUX_I. The other is a certain data x*8192. Since the input and output of the filter are both 14 bits, that is, the input and output bit widths remain unchanged, the input x*8192 is truncated and the output of the filter is actually x. Therefore, the result of the fourth delay unit Qi3 is directly connected to the entry 0 of the ninth multiplexing unit MUX_I without passing through the multiplier in the middle. The same is true for the Q-path tenth multiplexing unit MUX_Q connection.

[0115] Combined with the simulation timing of this application Figure 2 You can learn more about the specific working process of this application. Figure 2 I in dout_I and dout_Q C , Q CIt means that when the selection signal S=0, the ninth multiplexing unit MUX_I and the tenth multiplexing unit MUX_Q will select the outputs of the fourth delay unit Qi3 and the eleventh delay unit Qq3 respectively.

[0116] The utility model provides a zero intermediate frequency architecture transmitter, including: Figure 1 The interpolation filter shown.

[0117] The above is a detailed description of the implementation process and working details of a specific embodiment of the present application in combination with the drawings in the specification. For a general technician in this field, there will be flexible changes in the specific implementation of the application scheme based on the design architecture proposed in this application. Therefore, this specification should not be a limitation of the present application and does not exhaust the scope of the present application.

[0118] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An interpolation filter, characterized in that: The interpolation filter comprises: A first delay circuit, whose input terminal is connected to a first input signal, performs at least one delay process on the first input signal, and outputs a plurality of first delay signals; A second delay circuit, whose input terminal is connected to a second input signal, performs at least one delay process on the second input signal, and outputs a plurality of second delayed signals; a multiplexing circuit, whose input end is electrically connected to the output end of the first delay circuit and the output end of the second delay circuit respectively, and receives the plurality of first delayed signals and the plurality of second delayed signals; the multiplexing circuit outputs the plurality of first delayed signals or the plurality of second delayed signals under the control of the selection signal; The filter circuit has an input end electrically connected to an output end of the multiplexing circuit, performs addition and multiplication operations on the plurality of first delayed signals or the plurality of second delayed signals, and outputs a filtering result.

2. The interpolation filter according to claim 1, characterized in that The filtering circuit comprises: A first adding circuit, whose input end is electrically connected to the output end of the multiplexing circuit, adds the plurality of first delayed signals or the plurality of second delayed signals in pairs, and outputs a plurality of first addition operation results; a multiplication circuit, whose input end is electrically connected to the output end of the first addition circuit, multiplies each of the plurality of addition operation results by a corresponding filter coefficient, and outputs a plurality of multiplication operation results; The second adding circuit has an input end connected to the output end of the multiplying circuit, performs an addition operation on the multiple multiplication results, and outputs a second addition operation result.

3. The interpolation filter according to claim 2, characterized in that The first delay circuit includes multiple delay units, the second delay circuit includes multiple delay units, and the multiplexing circuit includes multiple multiplexing units. A multiplexing unit corresponds to connecting a delay unit of the first delay circuit and a delay unit of the second delay circuit; the first input signal and the second input signal are connected to the same multiplexing unit.

4. The interpolation filter according to claim 3, characterized in that The first delay circuit includes a first delay unit to a seventh delay unit, the second delay circuit includes an eighth delay unit to a fourteenth delay unit, the multiplexing circuit includes a first multiplexing unit to an eighth multiplexing unit, and the first multiplexing unit to the eighth multiplexing unit each include a first input terminal and a second input terminal; The first input signal is connected to the first input terminal of the first multiplexing unit, and the second input signal is connected to the second input terminal of the first multiplexing unit; The output end of the first delay unit is electrically connected to the first input end of the second multiplexing unit, and the output end of the eighth delay unit is electrically connected to the second input end of the second multiplexing unit; The output end of the second delay unit is electrically connected to the first input end of the third multiplexing unit, and the output end of the ninth delay unit is electrically connected to the second input end of the third multiplexing unit; The output end of the third delay unit is electrically connected to the first input end of the fourth multiplexing unit, and the output end of the tenth delay unit is electrically connected to the second input end of the fourth multiplexing unit; The output end of the fourth delay unit is electrically connected to the first input end of the fifth multiplexing unit, and the output end of the eleventh delay unit is electrically connected to the second input end of the fifth multiplexing unit; The output end of the fifth delay unit is electrically connected to the first input end of the sixth multiplexing unit, and the output end of the twelfth delay unit is electrically connected to the second input end of the sixth multiplexing unit; The output end of the sixth delay unit is electrically connected to the first input end of the seventh multiplexing unit, and the output end of the thirteenth delay unit is electrically connected to the second input end of the seventh multiplexing unit; The output end of the seventh delay unit is electrically connected to the first input end of the eighth multiplexing unit, and the output end of the fourteenth delay unit is electrically connected to the second input end of the eighth multiplexing unit.

5. The interpolation filter according to claim 4, characterized in that: The first adding circuit includes first to fourth adding units; The output end of the first multiplexing unit and the output end of the eighth multiplexing unit are electrically connected to the first adding unit respectively; The output end of the second multiplexing unit and the output end of the seventh multiplexing unit are electrically connected to the second adding unit respectively; The output end of the third multiplexing unit and the output end of the sixth multiplexing unit are electrically connected to the third adding unit respectively; The output end of the fourth multiplexing unit and the output end of the fifth multiplexing unit are electrically connected to the fourth adding unit respectively.

6. The interpolation filter according to claim 4, characterized in that The interpolation filter further includes: a ninth multiplexing unit and a tenth multiplexing unit having a third input terminal and a fourth input terminal; The output end of the fourth delay unit is electrically connected to the third input end of the ninth multiplexing unit, and the output end of the second adding circuit is electrically connected to the fourth input end of the ninth multiplexing unit; the ninth multiplexing unit is electrically connected to the second adding circuit or the fourth delay unit under the control of the selection signal to form a signal path; The output end of the eleventh delay unit is electrically connected to the third input end of the tenth multiplexing unit, and the output end of the second adding circuit is electrically connected to the fourth input end of the tenth multiplexing unit; the tenth multiplexing unit is electrically connected to the second adding circuit or the eleventh delay unit under the control of the selection signal to form a signal path.

7. The interpolation filter according to claim 6, characterized in that The interpolation filter further comprises: The third delay circuit has an input end electrically connected to the output end of the second adding circuit, and an output end electrically connected to the fourth input end of the ninth multiplexing unit.

8. The interpolation filter according to claim 7, characterized in that: The interpolation filter further comprises: A first trigger, whose input end is electrically connected to the output end of the ninth multiplexing unit, and whose output end serves as one of the output ends of the interpolation filter; The second trigger has an input end electrically connected to the output end of the tenth multiplexing unit, and an output end serving as another output end of the interpolation filter.

9. A zero intermediate frequency architecture transmitter, characterized in that: It comprises the interpolation filter as claimed in any one of claims 1 to 8.

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