Airborne equipment network card

Abstract

The utility model relates to the technical field of avionics airborne equipment communication, and discloses an airborne equipment network card, which comprises a core board, a connector and signal conversion modules, the connector comprises a bus interface and a plurality of electrical interfaces, and each electrical interface is connected with the core board through a corresponding signal conversion module; the connector is in communication connection with terminal equipment through a bus interface and is in communication connection with avionics equipment through a multi-path electrical interface; the core board communicates with the terminal equipment based on a first communication protocol corresponding to the terminal equipment bus, and communicates with the avionics equipment based on a second communication protocol corresponding to the airborne equipment; and the signal conversion module is in communication connection with the core board through a media independent interface. Therefore, in the communication process of the terminal equipment and the airborne equipment, the airborne equipment network card performs data conversion on the received and transmitted data according to the ARINC664 protocol, the communication efficiency between the terminal equipment and the avionics equipment is improved, and the function of the avionics equipment is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of avionics onboard equipment communication, in particular to an onboard equipment network card. Background Art

[0002] In avionics onboard equipment, the ARINC664 protocol is widely used. At the same time, the ARINC664 bus has a large number of interfaces in the application and the communication protocol is relatively complex. When communicating between the terminal equipment and the airborne equipment, it is necessary to convert the received and sent data according to the ARINC664 protocol. However, since the airborne equipment system has many functions and the data parameter types are relatively complex, the communication efficiency between the terminal equipment and the avionics equipment and the function realization of the avionics equipment are affected. Summary of the invention

[0003] In view of this, the utility model provides an airborne device network card to solve the problems of poor communication efficiency between terminal equipment and avionics equipment and difficulty in realizing the functions of avionics equipment.

[0004] In a first aspect, the utility model provides an airborne device network card, comprising: a core board, a connector and a signal conversion module, wherein the connector comprises a bus interface and a multi-channel electrical interface, and each of the electrical interfaces is connected to the core board through a corresponding signal conversion module;

[0005] A connector, used for communication connection with a terminal device via a bus interface and communication connection with an avionics device via a multi-channel electrical interface;

[0006] A core board, used to communicate with the terminal device based on a first communication protocol corresponding to the terminal device bus, and to communicate with the avionics device based on a second communication protocol corresponding to the airborne device;

[0007] The signal conversion module is used to communicate with the core board through the media independent interface.

[0008] In an optional embodiment, the signal conversion module includes: a physical layer chip PHY, a clock chip and a network transformer, wherein the PHY is connected to the clock chip through a preset first pin, and is connected to the network transformer through a preset second pin, and is communicated with the core board through a third pin corresponding to the media independent interface, and is communicated with the connector through a fourth pin corresponding to the connector interface.

[0009] In an optional implementation, the core board includes: an FPGA chip, wherein the FPGA chip includes bus interface pins, and the bus interface pins are communicatively connected to the terminal device via two pairs of data differential channels and a pair of clock differential channels.

[0010] In an optional implementation, the airborne device network card further includes: a random access memory, wherein the random access memory is communicatively connected to the core board;

[0011] Random access memory is used to store the data sent and received by the core board.

[0012] In an optional implementation, the airborne device network card further includes: a flash memory, wherein the flash memory is communicatively connected to the core board;

[0013] The flash memory is used to store the loading files of the core board, wherein the loading files include the program files of the core board.

[0014] In an optional embodiment, the airborne device network card further includes: a serial communication interface, wherein the serial communication interface is communicatively connected to the core board via a parallel data transmission interface;

[0015] The serial communication interface is used to connect to a debugging device through a connector, wherein the debugging device is used to debug the network card of the airborne device.

[0016] In an optional implementation, the airborne device network card further includes: a power supply device, wherein the power supply device includes: a connector, a filter circuit, a first power supply chip and a second power supply chip;

[0017] A connector for inputting a DC power of a preset voltage into a filter circuit;

[0018] A filter circuit, used for filtering the direct current and inputting the direct current into the first power chip and the second power chip respectively;

[0019] A first power chip, used for converting direct current into direct current of target voltage and inputting the direct current into the first sub-functional module in the core board;

[0020] The second power chip is used to supply power to each second sub-function module in the core board according to the rated voltage of the second sub-function module, wherein the second sub-function module is the remaining sub-function module in the core board except the first sub-function module.

[0021] In an optional embodiment, the second power chip is also used to: supply power to each third functional module in the airborne device network card according to the rated voltage of the third functional module, wherein the third functional module is the remaining functional module in the airborne device network card except the core board. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a structural diagram of an onboard device network card according to an embodiment of the utility model;

[0024] Figure 2 This is a schematic diagram of the use scenario of the airborne device network card;

[0025] Figure 3 is an architectural diagram of another airborne device network card according to an embodiment of the utility model;

[0026] Figure 4 It is a schematic diagram of the chip connection of the signal conversion module;

[0027] Figure 5 It is a structural diagram of another airborne device network card according to an embodiment of the utility model;

[0028] Figure 6 It is a schematic diagram of FPGA chip memory resource allocation;

[0029] Figure 7 It is a schematic diagram of some bus interface pins in FPGA chip;

[0030] Figure 8 This is a schematic diagram of a DDR chip;

[0031] Fig. 9 This is a schematic diagram of the Flash chip;

[0032] Fig.10 This is a schematic diagram of the RS232 interface chip;

[0033] Fig.11 It is a structural diagram of another airborne device network card according to an embodiment of the utility model;

[0034] Fig.12 is a schematic diagram of a power supply unit. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0036] In conjunction with the application scenarios on which the execution of the airborne device network card depends, the application scenarios are described here.

[0037] In avionics onboard equipment, the ARINC664 protocol is widely used. At the same time, the ARINC664 bus has a large number of interfaces in the application and the communication protocol is relatively complex. When communicating between the terminal equipment and the airborne equipment, it is necessary to convert the received and sent data according to the ARINC664 protocol. However, since the airborne equipment system has many functions and the data parameter types are relatively complex, the communication efficiency between the terminal equipment and the avionics equipment and the function realization of the avionics equipment are affected.

[0038] Specifically, in the process of communication between terminal equipment and airborne equipment, there are high requirements for ARINC664 protocol consistency check of sent and received data, ICD (Interface Control Document) parsing and processing, simulation of related communication between airborne equipment, and data monitoring and recording. Therefore, in the scheme of communication between terminal equipment and airborne equipment, there is an urgent need for an airborne equipment that can be applied to a large-scale integrated verification environment to assist in solving data processing problems.

[0039] The embodiment of the utility model provides an airborne device network card, including: a core board, a connector and a signal conversion module, wherein the connector includes a bus interface and a multi-channel electrical interface, and each electrical interface is connected to the core board through a corresponding signal conversion module; the connector is used to communicate with the terminal device through the bus interface, and communicate with the avionics equipment through the multi-channel electrical interface; the core board is used to communicate with the terminal device based on a first communication protocol corresponding to the terminal device bus, and communicate with the avionics equipment based on a second communication protocol corresponding to the airborne device; the signal conversion module is used to communicate with the core board through a media independent interface. In the process of communication between the terminal device and the airborne device, the airborne device network card can be used to convert the received and sent data according to the ARINC664 protocol, thereby improving the communication efficiency between the terminal device and the avionics equipment and realizing the functions of the avionics equipment.

[0040] In this embodiment, an onboard device network card is provided. Figure 1is a diagram of the architecture of an onboard device network card according to an embodiment of the utility model, such as Figure 1 As shown, the airborne device network card includes: a connector 10, a core board 20, and a signal conversion module 30, wherein the connector 10 includes a bus interface 11 and multiple electrical interfaces 12, and each electrical interface is connected to the core board through a corresponding signal conversion module.

[0041] The connector 10 is used to communicate with the terminal device through the bus interface and communicate with the avionics device through the multi-channel electrical interface.

[0042] In the disclosed embodiment, the airborne device network card is an ARINC664 terminal network card, which can be applied to airborne devices using the ARINC664 bus protocol. The airborne device network card includes the connector, which is used to provide an external connection interface for the airborne device network card.

[0043] Here, the above-mentioned interface includes a bus interface for communicating with a terminal device, and a multi-channel electrical interface for communicating with an avionics device. The bus interface may be a PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) interface, the data transmission rate of which may reach 100 Mbps, and the multi-channel electrical interface may be a dual-redundant ARINC664 electrical interface, where dual redundancy means two ports, such as Ethernet interface A and Ethernet interface B. It should be understood that when data is sent and received through the electrical interface, one of the ports is usually used as a backup data port to improve the reliability of data transmission.

[0044] The core board 20 is used to communicate with the terminal device based on a first communication protocol corresponding to the terminal device bus, and to communicate with the avionics device based on a second communication protocol corresponding to the airborne device.

[0045] In the embodiments of the present disclosure, Figure 2 The figure shows a schematic diagram of the use scenario of the above-mentioned airborne equipment network card, wherein the terminal device may be a device for communicating with the avionics equipment, for example, a laptop computer. Usually, the first communication protocol corresponding to the terminal device bus may be a PCIE transmission protocol. In addition, the avionics equipment bus is an ARINC664 bus, and ARINC664 is used to communicate with the terminal device. Therefore, the above-mentioned second communication protocol may be an ARINC664 protocol (hereinafter referred to as AFDX protocol).

[0046] Specifically, when the avionics equipment communicates with the terminal equipment through the airborne equipment network card, high-speed data transmission can be performed with the CPU of the terminal equipment through PCIE1x. The airborne equipment network card can convert the data format of the acquired data through the core board to convert the data into the data format of the AFDX protocol, and send the data to the avionics equipment through the AFDX protocol.

[0047] Similarly, after the airborne device network card obtains the data sent by the airborne device through the above-mentioned AFDX protocol, it can convert the data format of the data through the core board to convert the data into the data format of the PCIE protocol, and send the data to the terminal device through the PCIE protocol.

[0048] The signal conversion module 30 is used to communicate with the core board through a media independent interface.

[0049] In the disclosed embodiment, the signal converter can be used for data processing and transmission between the avionics equipment and the airborne equipment network card, wherein the signal converter can include a PHY (Port Physical Layer) chip. In addition, the media independent interface can be a MII (Media Independent Interface) interface.

[0050] Here, when the above-mentioned avionics equipment communicates with the airborne equipment network card, the received data can be processed by the above-mentioned PHY chip, digital signals or analog signals can be converted, and the converted data can be transmitted. The specific data processing and transmission process will not be repeated here.

[0051] It can be known from the above description that in the embodiment of the present disclosure, the above-mentioned airborne device network card includes: a core board, a connector and a signal conversion module, wherein the connector includes a bus interface and a multi-channel electrical interface, and each electrical interface is connected to the core board through the corresponding signal conversion module; the connector is used to communicate with the terminal device through the bus interface, and communicate with the avionics equipment through the multi-channel electrical interface; the core board is used to communicate with the terminal device based on the first communication protocol corresponding to the terminal device bus, and communicate with the avionics equipment based on the second communication protocol corresponding to the airborne device; the signal conversion module is used to communicate with the core board through the media independent interface. In the process of communication between the terminal device and the airborne device, the airborne device network card can be used to convert the sent and received data according to the ARINC664 protocol, thereby improving the communication efficiency between the terminal device and the avionics equipment and realizing the functions of the avionics equipment.

[0052] In this embodiment, another onboard device network card is also provided. Figure 3This is an architecture diagram of another airborne device network card according to an embodiment of the utility model, and the specific architecture is as follows:

[0053] Connector 10 is used to communicate with terminal equipment through a bus interface and communicate with avionics equipment through a multi-channel electrical interface. Figure 1 The connector 10 of the illustrated embodiment will not be described in detail herein.

[0054] The core board 20 is used to communicate with the terminal device based on the first communication protocol corresponding to the terminal device bus, and to communicate with the avionics device based on the second communication protocol corresponding to the airborne device. Figure 1 The core board 20 of the illustrated embodiment will not be described in detail here.

[0055] The signal conversion module 30 is used to communicate with the core board through a media independent interface.

[0056] Specifically, the above-mentioned signal conversion module 30 includes: a physical layer chip PHY31, a clock chip 32 and a network transformer 33, wherein the PHY is connected to the clock chip through a preset first pin, and is connected to the network transformer through a preset second pin, and is communicated with the core board through the third pin corresponding to the above-mentioned MII interface, and is communicated with the connector through the fourth pin corresponding to the connector interface.

[0057] In the embodiment of the present disclosure, the chip model corresponding to the above-mentioned PHY may be JEM971A, and the chip model corresponding to the above-mentioned network transformer may be XECLT0068A. It should be understood that in actual use, the chip models of PHY, network transformer and clock chip may also be other models, which shall be subject to what can be implemented, and the present disclosure does not make any specific limitation on this.

[0058] Specifically, Figure 4 The diagram shows the chip connection of the signal conversion module, wherein the PHY corresponds to the chip U10 in the figure, the clock chip corresponds to U12 in the figure, and the first pin in the PHY includes: pins 1-2. The network transformer corresponds to the chip U11 in the figure, and the second pin in the PHY includes: pins 23-24 and pins 19-20. The third pin in the PHY includes: pins 52-60, pins 45-49, pins 62-64, pin 3, pin 42-43, pins 12-16, and pins 27-31. The fourth pin in the PHY includes: pin 26, pin 5-7, pin 17, pin 32-33, pin 36-39, pin 9, pin 10, and pin 44. It should be understood that the connection method of the third pin and the fourth pin with the corresponding components is based on the corresponding functional implementation in the actual use process, and will not be repeated in this disclosure.

[0059] In addition, the VCC pin (pins 51, 8, 40, 22 and 21) in the above-mentioned PHY is used to connect the power module and power the PHY, and the GND pin (pins 7, 11, 18, 25, 34, 35, 41, 50 and 61) is a ground pin. The GND pin serves as a reference point for the PHY, and all signals can be referenced to zero potential, thereby making the chip work more stably.

[0060] In the disclosed embodiment, the received data may be processed by a signal conversion module, for example, the data may be converted into a digital signal or an analog signal, thereby achieving communication between the terminal device and the avionics device.

[0061] In this embodiment, another onboard device network card is provided. Figure 5 This is an architecture diagram of another airborne device network card according to an embodiment of the utility model, and the specific architecture is as follows:

[0062] Connector 10 is used to communicate with terminal equipment through a bus interface and communicate with avionics equipment through a multi-channel electrical interface. Figure 1 The connector 10 of the illustrated embodiment will not be described in detail herein.

[0063] The core board 20 is used to communicate with the terminal device based on a first communication protocol corresponding to the terminal device bus, and to communicate with the avionics device based on a second communication protocol corresponding to the airborne device.

[0064] Specifically, the core board 20 includes: an FPGA chip 21, wherein the FPGA chip includes bus interface pins, and the bus interface pins are communicatively connected with the terminal device through two pairs of data differential channels and one pair of clock differential channels.

[0065] In the embodiment of the present disclosure, the FPGA chip can use the JFM7K325T-N model chip of Fudan Micro as the core processor of the module. It should be understood that the arrangement of I / O in the FPGA chip is realized by BANK division. Therefore, it can be realized by Figure 6 The method shown allocates related memory (hereinafter referred to as bank) resources to the FPGA chip, wherein the bank resources can be allocated by column (i.e., Column in the figure), and the specific bank resource allocation method is not described in detail in this disclosure.

[0066] In addition, the FPGA chip includes a bus interface pin, which can be used to connect to the bus interface in the connector, thereby establishing a communication connection between the connector and the terminal device.

[0067] Specifically, Figure 7The figure shows a schematic diagram of some bus interface pins in the FPGA chip, wherein the bus interface pins include pin L3, pin L4, pin M5, pin M6, pin N7, and pin N8. Specifically, the two pairs of data differential channels correspond to pins L3, pin L4, pin M5, and pin M6, respectively, and a pair of clock differential channels correspond to pins N7 and pin N8.

[0068] The signal conversion module 30 is used to communicate with the core board through the media independent interface. Figure 1 The signal conversion module 30 of the illustrated embodiment will not be described in detail herein.

[0069] In the embodiments of the present disclosure, network connection can be achieved through the bus interface, thereby achieving high-speed and reliable data communication, and efficiently realizing all the functions of the ARINC664 protocol stack and the end system specified by the ARINC664 protocol. At the same time, the bus interface pins can include a pair of data differential channels and a pair of clock differential channels, thereby improving the anti-interference ability during data transmission and increasing the data transmission rate.

[0070] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes a random access memory 40, which is communicatively connected to the core board;

[0071] The random access memory 40 is used to store the data sent and received by the core board.

[0072] In the embodiment of the present disclosure, the above-mentioned transceived data may be the communication data generated when the above-mentioned avionics equipment communicates with the terminal equipment, and the transceived data may be stored in a random access memory (Double Data Rate, i.e., double data rate storage technology, hereinafter referred to as DDR), so as to facilitate subsequent data analysis and other operations on the transceived data. For example, when testing and verifying the airborne equipment, it is necessary to analyze the transceived data to determine whether the airborne equipment has a fault, and the specific test and verification process is not described in detail in the present disclosure.

[0073] Specifically, the core board can support various types of DDR chips, such as DDR3, DDR3L, DDR2, RLDRAMIII, etc. The specific type of DDR chip used is subject to implementation and is not specifically limited in the present disclosure.

[0074] Here we take the SM47H64M16M DDR chip of SMIC as an example. Figure 8As shown is a schematic diagram of the DDR chip, wherein the DDR chip can be connected to the core board through the fifth pin, and the fifth pin includes: pins DQ0-DQ15, pins A0-A12, pins BA0-BA1, pins LDM, pin UDM, pin LDQS, pin LDQS#, pin UDQS, pin UDQS#, pin CK, pin CK#, pin CKE, pin RAS#, pin CAS#, pin WE#, pin CS#, pins NC1-NC5 and pin COT.

[0075] In the disclosed embodiment, the above-mentioned airborne device network card may include DDR, so as to store the received and sent data through the DDR, thereby facilitating subsequent operations such as data analysis on the received and sent data.

[0076] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes a flash memory 50, wherein the flash memory 50 is communicatively connected with the core board;

[0077] The flash memory 50 is used to store the loading file of the core board, wherein the loading file includes the program file of the core board.

[0078] In the embodiment of the present disclosure, the above-mentioned program files may include an operating system, an application program, a system configuration file, etc. Here, the chip type of the flash memory (hereinafter referred to as Flash) may be the SM25QH256M chip of Guowei Electronics, such as Fig. 9 Shown is a schematic diagram of a Flash chip.

[0079] Specifically, in the above-mentioned Flash chip, pin 2 and pin 7 are power pins for powering the chip, the GND pin is a ground pin, and the remaining pins are used to communicate with the above-mentioned core board core. It should be understood that the core board can be communicated with in response to a modification request of the terminal device, so as to modify the program file in the Flash, for example, to update the system configuration file.

[0080] In the disclosed embodiment, considering that Flash has high reliability and can provide high-speed reading and writing speeds, the above-mentioned program files can be stored in the Flash, and the cost is relatively low, thereby reducing the hardware cost while ensuring the system operation speed of the airborne device network card.

[0081] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes a serial communication interface 60, which is connected to the core board through a parallel data transmission interface;

[0082] The above-mentioned serial communication interface is used to connect to the debugging device through the connector, wherein the debugging device is used to debug the network card of the airborne device.

[0083] In the disclosed embodiment, the above serial communication interface is a configuration interface, and the user can connect the debugging device based on the configuration interface to debug the avionics equipment. Here, the serial communication interface can be an RS232 interface, and the chip type selected by the RS232 interface can be SM3232 of Guowei Electronics, and the maximum communication rate of the RS232 interface can reach 1Mbps. In addition, the above RS232 interface can be connected to the core board through a parallel data transmission interface (Transistor Transistor Logic, hereinafter referred to as TTL).

[0084] like Fig.10 The figure shows a schematic diagram of the above-mentioned RS232 interface chip, wherein pins 1-6 are used to adjust the chip voltage, pins 7-10 are used to connect the above-mentioned connector, thereby communicating with the debugging device based on the connector, pins 11-14 are used to communicate with the above-mentioned core board, pin 16 is a power pin, used to power the chip, and pin 15, i.e. the above-mentioned GND pin, is a ground pin.

[0085] In the disclosed embodiment, a serial communication interface may be reserved in the above-mentioned airborne device network card as a debugging interface, so as to debug the avionics equipment to reduce the equipment failure rate and ensure the equipment safety.

[0086] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes a power supply device 70, wherein the power supply device includes: a connection module 71, a filter circuit 72, a first power supply chip 73 and a second power supply chip 74;

[0087] The connection module 71 is used to input direct current of a preset voltage into the filter circuit.

[0088] The filter circuit 72 is used to filter the DC power and input it to the first power chip and the second power chip respectively.

[0089] The first power chip 73 is used to convert direct current into direct current of target voltage and input it into the first sub-functional module in the core board.

[0090] The second power chip 74 is used to supply power to each second sub-function module in the core board according to the rated voltage of the second sub-function module, wherein the second sub-function module is the remaining sub-function module in the core board except the first sub-function module.

[0091] In the disclosed embodiment, the power supply device is used to supply power to each functional module in the airborne device network card according to a preset voltage. Here, the rated power of the airborne device network card can be determined first, and the preset voltage can be determined based on the rated power.

[0092] Specifically, we can first analyze the main power consumption of the above-mentioned airborne device network card. From the above, we can know that the airborne device network card includes: a core board (using FPGA chip), an RS232 interface, a connector, a PHY, a DDR, a Flash and a power supply device. Fig.11 The figure shows the architecture diagram of another airborne device network card provided by the present disclosure. As can be seen from the figure, the chip used by FPGA is JFM7K325T-N, with a power consumption of 3W, the chip used by RS232 interface is SM3232, with a power consumption of 0.05W, the chip used by PHY is JEM971A, with a power consumption of 0.3W, the chip used by DDR is SM47H64M16M, with a power consumption of 0.3W, the chip used by Flash is SM25QH256M, with a power consumption of 0.05W, and the chip used by the power supply device is SM4644MPY, with a power consumption of 0.4W. In addition, the other power consumption in the airborne device network card is about 0.15W.

[0093] It should be understood that, as can be seen from the above, the multi-channel electrical interface used for communication connection with avionics equipment adopts a dual redundant ARINC664 electrical interface, therefore, the PHY corresponding to the multi-channel electrical interface should be two-channel, and the number of JEM971A chips is two. Similarly, the power supply device includes a first power chip and a second power chip, and the number of SM4644MPY chips is two.

[0094] Based on this, it can be calculated that the power consumption of the above-mentioned airborne device network card is approximately: 3W+0.05W+0.3W×2+0.3W+0.05W+0.4W×2=4.95W, so the rated power can be determined as 4.95 W. The preset voltage determined based on the rated power can be 5V.

[0095] In addition, considering that the instantaneous power of the capacitor charging and discharging process when the above-mentioned power supply device is powered on may exceed 5.5W, the power chip used in the airborne equipment network card has a power-on soft start function, which can effectively slow down the overshoot current until the power supply and the entire board power stabilize at 4.95W.

[0096] When the filter circuit obtains the 5V 1A DC current input from the connector, it can perform EMC (electromagnetic compatibility) protection and filtering on the DC current, and input the processed DC current into the first power chip and the second power chip respectively.

[0097] like Fig.12 The figure shows a schematic diagram of the power supply device, wherein the first power chip is the SM4644VCONT1.0V MGTVCC1.0V chip in the figure, and the second power chip is the SM4644MGTVCC1.2V VCCO3.3VVCCAUX_1V8 VCC_DDR2_1V8 chip in the figure.

[0098] Depend on Fig.12 It can be seen that the above-mentioned FPGA chip can be powered by the first power chip and the second power chip at the same time. Specifically, the above-mentioned first power chip powers the first sub-function module through 1.5A DC power with a target voltage of 5V, and the above-mentioned second power chip powers the second sub-function module in the FPGA with 3.3V 0.2A DC power, 1.8V 0.2A DC power, and 1.2V 0.2A DC power, respectively.

[0099] In the embodiment of the present disclosure, different sub-functional modules in the FPGA chip can be powered by the first power chip and the second power chip respectively, thereby improving the stability of power supply to the FPGA chip.

[0100] In the embodiment of the present disclosure, the above-mentioned second power supply chip 74 is also used to: supply power to each third functional module in the airborne device network card according to the rated voltage of the third functional module, wherein the third functional module is the remaining functional module in the airborne device network card except the core board.

[0101] Depend on Fig.12 It can be seen that the third functional module includes: DDR, Flash, PHY and RS232 interface. Among them, DDR corresponds to a 0.5A DC power supply with a rated voltage of 1.8V, Flash corresponds to a 0.05A DC power supply with a rated voltage of 3.3V, PHY corresponds to a 0.2A DC power supply with a rated voltage of 3.3V, and RS232 interface corresponds to a 0.05A DC power supply with a rated voltage of 3.3V.

[0102] In the disclosed embodiment, different functional modules in the FPGA chip can be powered by an independent second power chip, thereby improving the reliability of power supply to the airborne device network card.

[0103] In the embodiments of the present disclosure, the above Figure 1 The corresponding airborne device network card also includes an indicator light 80, wherein the indicator light includes: indicator light 1, indicator light 2, indicator light 3, indicator light 4 and indicator light 5;

[0104] The indicator light 1 is used to indicate whether the power supply device can provide 3.3V voltage normally. If the indicator light 1 is on, it means that it can be provided normally, otherwise it cannot be provided normally.

[0105] The indicator light 2 is used to indicate whether the loading file in the FPGA is completed. If the indicator light 2 is on, it means that the loading is completed, otherwise it is not completed.

[0106] The indicator light 3 is used to indicate the detection clock and the bus interface status. When the airborne device network card is self-checking, it lights up to indicate that the clock is normal. In addition, the indicator light 3 lights up when the bus interface status is tested during the operation of the airborne device network card.

[0107] The indicator light 4 is used to indicate the DDR status during the self-check of the airborne device network card. If it is on, it means that the DDR status is normal. In addition, the indicator light 4 is on when the Ethernet interface A is connected during the operation of the airborne device network card, and flashes when sending and receiving data.

[0108] The indicator light 5 is used to indicate the DDR status during the self-check of the airborne device network card. If it is on, it means that the DDR status is normal. In addition, the indicator light 4 is on when the Ethernet interface B is connected during the operation of the airborne device network card, and flashes when sending and receiving data.

[0109] In the disclosed embodiment, the indicator lights 1-5 may be LED (light-emitting diode) lights, so that the user can understand the operating status of the airborne device network card through the LED lights.

[0110] In summary, in the disclosed embodiment, the above-mentioned airborne device network card includes: a core board, a connector and a signal conversion module, wherein the connector includes a bus interface and a multi-channel electrical interface, and each electrical interface is connected to the core board through the corresponding signal conversion module; the connector is used to communicate with the terminal device through the bus interface, and communicate with the avionics equipment through the multi-channel electrical interface; the core board is used to communicate with the terminal device based on the first communication protocol corresponding to the terminal device bus, and communicate with the avionics equipment based on the second communication protocol corresponding to the airborne device; the signal conversion module is used to communicate with the core board through the media independent interface. In the process of communication between the terminal device and the airborne device, the airborne device network card can be used to convert the sent and received data according to the ARINC664 protocol, thereby improving the communication efficiency between the terminal device and the avionics equipment and realizing the functions of the avionics equipment.

[0111] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0112] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0113] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0115] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0116] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An airborne device network card, characterized in that: include: A core board, a connector and a signal conversion module, wherein the connector includes a bus interface and a multi-channel electrical interface, and each of the electrical interfaces is connected to the core board through a corresponding signal conversion module; The connector is used to communicate with the terminal device through the bus interface and communicate with the avionics device through the multi-channel electrical interface; The core board is used to communicate with the terminal device based on a first communication protocol corresponding to the terminal device bus, and to communicate with the avionics device based on a second communication protocol corresponding to the airborne device; The signal conversion module is used to communicate with the core board through a media independent interface.

2. The airborne device network card according to claim 1, characterized in that: The signal conversion module includes: a physical layer chip PHY, a clock chip and a network transformer, wherein the PHY is connected to the clock chip through a preset first pin, and is connected to the network transformer through a preset second pin, and is communicatively connected to the core board through a third pin corresponding to a media independent interface, and is communicatively connected to the connector through a fourth pin corresponding to a connector interface.

3. The airborne device network card according to claim 1, characterized in that: The core board includes: an FPGA chip, wherein the FPGA chip includes bus interface pins, and the bus interface pins are communicatively connected with the terminal device through two pairs of data differential channels and a pair of clock differential channels.

4. The airborne device network card according to claim 1, characterized in that: The airborne device network card further includes: a random access memory, wherein the random access memory is communicatively connected with the core board; The random access memory is used to store the sending and receiving data of the core board.

5. The airborne device network card according to claim 1, characterized in that: The airborne device network card further includes: a flash memory, wherein the flash memory is communicatively connected with the core board; The flash memory is used to store the loading file of the core board, wherein the loading file includes the program file of the core board.

6. The airborne device network card according to claim 1, characterized in that: The airborne device network card also includes: a serial communication interface, wherein the serial communication interface is communicatively connected to the core board via a parallel data transmission interface; The serial communication interface is used to connect to a debugging device through the connector, wherein the debugging device is used to debug the airborne device network card.

7. The airborne device network card according to claim 1, characterized in that: The airborne device network card further includes: a power supply device, wherein the power supply device includes: a connector, a filter circuit, a first power supply chip and a second power supply chip; The connector is used to input direct current of a preset voltage into the filter circuit; The filtering circuit is used to filter the DC power and input it to the first power chip and the second power chip respectively; The first power chip is used to convert the direct current into direct current of a target voltage and input it into the first sub-functional module in the core board; The second power chip is used to supply power to each second sub-function module in the core board according to the rated voltage of the second sub-function module, wherein the second sub-function module is the remaining sub-function module in the core board except the first sub-function module.

8. The airborne device network card according to claim 7, characterized in that: The second power chip is also used to: supply power to each third functional module in the airborne device network card according to the rated voltage of the third functional module, wherein the third functional module is the remaining functional module in the airborne device network card except the core board.

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