Packaging structure for improving voltage resistance and creepage distance of high-voltage SLIC chip and chip

Abstract

The utility model provides a packaging structure for improving the voltage resistance and creepage distance of a high-voltage SLIC chip, and the chip. The packaging structure comprises an LV chip, an HV chip, pins, an insulation reinforcement body, and a carrier. The LV chip and the HV chip are fixed on the surface of the carrier in an insulating manner, the pins are fixedly arranged at the periphery of the carrier, the pins are electrically connected with the LV chip through semiconductor bonding gold wires, and the pins are electrically connected with the HV chip through semiconductor bonding gold wires; the pins comprise high-voltage pins and low-voltage pins, and the distance between the high-voltage pins is larger than that between the low-voltage pins; the insulation reinforcement body is arranged between the HV chip and the carrier, and the top surface and the bottom surface of the insulation reinforcement body are fixedly connected with the HV chip and the carrier respectively. According to the utility model, the physical creepage distance between the high-voltage pins can be effectively increased, and the insulation thickness between the high-voltage chip and the bottom plate is increased, so that the safety performance of the product is improved, and the voltage endurance capability is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, and in particular to a packaging structure and a chip for improving the voltage resistance and creepage distance of a high-voltage SLIC chip. Background Art

[0002] At present, the SLIC (Subscriber line IC) chips produced in large quantities on the market basically adopt QFN or LGA packaging. The chip is pasted on the base island of the lead frame. One or several circles of inner pins are designed around the base to bond the IO pads on the surface of the chip together through gold or copper wires. At the same time, the inner pins extend outward to expose the surface of the package to form outer pins. From the appearance, these outer pins are arranged at equal intervals on the edge of the package. The center distance between the pins is the pin pitch. The pitch of the pins in the same row is the same, which makes the appearance more symmetrical and beautiful. Figure 1 shown.

[0003] For SLIC chips, there is usually a high voltage of about 100~200V, which places high demands on the insulation of the chip.

[0004] For the requirements of both a smaller chip area and a larger number of pins, the most likely way is to reduce the pin spacing. However, the disadvantages of reducing the pin spacing are: higher voltage resistance requirements between pins, and the reduction of creepage distance increases the risk of breakdown.

[0005] When the distance between pins becomes smaller, there is a high possibility of the following risks:

[0006] 1. The instantaneous overshoot caused by power supply voltage fluctuation may break down the weak pins of the chip and cause a short circuit in the device.

[0007] 2. When encountering rainy weather, seaside and other high-salinity, humid and hot environments, ions are likely to migrate inside the chip.

[0008] 3. Defects such as pin burrs caused by electroplating during the production and processing process, solder paste overflow during SMT welding, and tin whiskers that grow naturally after long-term use can easily cause tip discharge, which is very likely to cause damage to the chip or the entire equipment, and more seriously may even cause personal injury.

[0009] 4. Even if some solutions set an NC pin between the high-voltage pins, although no electrical connection is made, this will also increase the risk, because the burrs in the welding process may treat the NC pin as a "bridge". In extreme cases, a discharge path is formed under the connection of this "bridge", causing product failure.

[0010] On the other hand, SLIC chips are usually composed of high-voltage chips (HV chips) and low-voltage chips (LV chips). Due to the requirement for high insulation between the carriers, the distance between the high-voltage chip, the low-voltage chip and the carrier needs to be increased. This packaging process has the following disadvantages: a. The distance between the high-voltage chip and the low-voltage chip becomes larger. Under the same package body, the size of the high-voltage chip and the low-voltage chip is limited; b. The solder under the high-voltage chip needs to strike a balance between thickness and size. On the one hand, a certain thickness is required to ensure high insulation, and on the other hand, the size needs to be controlled so as not to cause contamination of the high-voltage chip. Utility Model Content

[0011] In view of the defects in the prior art, the purpose of the utility model is to provide a packaging structure and chip for improving the voltage resistance and creepage distance of a high-voltage SLIC chip.

[0012] According to the utility model, a packaging structure for improving the withstand voltage performance and creepage distance of a high-voltage SLIC chip is provided, comprising: a low-voltage chip, a high-voltage chip, pins, an insulation reinforcement body and a carrier;

[0013] The low voltage chip and the high voltage chip are insulated and fixed on the surface of the carrier, the pins are fixedly arranged around the carrier, the pins are electrically connected to the low voltage chip through semiconductor bonding gold wires (Bonding wires), and the pins are electrically connected to the high voltage chip through semiconductor bonding gold wires;

[0014] The pins include high-voltage pins and low-voltage pins, and the spacing between the high-voltage pins is greater than the spacing between the low-voltage pins;

[0015] The insulation reinforcement body is arranged between the high-voltage chip and the carrier, and the top surface and the bottom surface of the insulation reinforcement body are fixedly connected to the high-voltage chip and the carrier respectively.

[0016] Preferably, the spacing between the low-voltage pins is d, the spacing between the high-voltage pins is D, and D=2d.

[0017] Preferably, the high voltage pin and the low voltage pin are respectively arranged on different sides of the carrier.

[0018] Preferably, the high-voltage pins are arranged on two opposite sides of the carrier, and the low-voltage pins are arranged on the other two opposite sides of the carrier.

[0019] Preferably, it also includes an insulating pad layer, which is filled and arranged between the pins.

[0020] Preferably, the insulation reinforcement body is any one of a DAF film, a dummy film and a glass sheet.

[0021] According to a SLIC chip provided by the utility model, the packaging structure for improving the voltage resistance performance and creepage distance of the high-voltage SLIC chip is adopted.

[0022] Compared with the prior art, the utility model has the following beneficial effects:

[0023] 1. This solution can effectively increase the physical creepage distance between high-voltage pins, so that possible discharge paths disappear due to the increased distance between metal pins, thereby improving product safety performance.

[0024] 2. This solution can increase the insulation thickness between the high-voltage chip and the base plate, improve the voltage resistance, and leave a larger margin for the process window.

[0025] 3. This solution can weaken the production and expand the parameter window of the processing technology under the same process conditions, providing greater redundancy for the production and processing technology, thereby improving the quality of the product.

[0026] 4. This solution can be more resistant to harsh operating environments, such as high temperature, humidity, and high salt content, reducing the possibility of failure.

[0027] 5. This solution can release part of the overvoltage when the power supply voltage is unstable, reducing the probability of product failure under overshoot spikes. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0029] Figure 1 This is a common SLIC chip appearance diagram in the prior art;

[0030] Figure 2 This is the appearance diagram of the SLIC chip in the utility model;

[0031] Figure 3 This is the internal structure diagram of the SLIC chip in the utility model;

[0032] Figure 4 It is a schematic diagram of the insulating cushion layer in the utility model.

[0033] Description of reference numerals:

[0034] Low voltage chip 1; high voltage chip 2; pin 3; carrier 4; semiconductor bonding gold wire 5; insulating adhesive 6; insulating reinforcement 7; insulating cushion layer 8; plastic sealing layer 9. DETAILED DESCRIPTION

[0035] The utility model is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the utility model, but do not limit the utility model in any form. It should be pointed out that for those of ordinary skill in the art, several changes and improvements can be made without departing from the concept of the utility model. These all belong to the protection scope of the utility model.

[0036] Reference Figure 1 As shown in the figure, it is a common SLIC chip appearance diagram in the prior art. The external pins are arranged at equal intervals on the edge of the package body. The center distance between the pins is the pin pitch. The pitch of the pins in the same row is the same. Figure 1 The pins selected by the middle circle are high voltage pins, and the other pins are low voltage pins. The utility model provides a SLIC chip packaging structure with unequal spacing.

[0037] The utility model discloses a packaging structure for improving the withstand voltage performance and creepage distance of a high-voltage SLIC chip, which can greatly improve the withstand voltage capability of the SLIC product, increase the creepage distance, reduce possible high voltage damage caused by process fluctuations and harsh environments, and improve product reliability.

[0038] Reference Figure 2-Figure 4 As shown, the packaging structure includes a low-voltage chip 1, a high-voltage chip 2, pins 3, and a carrier 4; the low-voltage chip 1 and the high-voltage chip 2 are insulated and fixed on the surface of the carrier 4, the pins 3 are fixedly arranged around the carrier 4, the pins 3 are electrically connected to the IO pads on the surface of the low-voltage chip 1 through semiconductor bonding gold wires 5, and the pins 3 are electrically connected to the IO pads on the surface of the high-voltage chip 2 through semiconductor bonding gold wires.

[0039] The pins 3 include high-voltage pins 3 and low-voltage pins 3, which are respectively arranged on different sides of the carrier 4, and the spacing between the high-voltage pins 3 is greater than the spacing between the low-voltage pins 3. In a preferred embodiment, the spacing between the high-voltage pins 3 is equal to the spacing between the low-voltage pins 3 of the two cups. In a preferred embodiment, the welding surface of the carrier 4 is rectangular, the high-voltage pins 3 are arranged on two opposite sides of the carrier 4, and the low-voltage pins 3 are arranged on the other two opposite sides of the carrier 4.

[0040] like Figure 2As shown, the pins N1-N4 indicated by the circled positions are high-voltage pins 3, and the pins N5-Nn are low-voltage pins 3, wherein the spacing between the low-voltage pins 3 is d, and the spacing between the high-voltage pins 3 is D. The value of D is set to 2d, that is, the pin spacing between the high-voltage pins 3 is adjusted to twice the spacing between the low-voltage pins 3, eliminating the NC pin 3 position at the physical level, reducing the possibility of product failure due to the existence of the "bridge", thereby improving the reliability of the product.

[0041] In a preferred embodiment, an insulating pad layer 8 is further included, and the insulating pad layer 8 is filled and arranged between the pins 3. Before the chip is plastic-sealed, a layer of high insulating pad layer 8 is pre-placed inside the mold, so that the material seen on the pin 3 side in the appearance is all this layer of high insulating pad layer 8, which can effectively increase the withstand voltage. The unit including the insulating pad layer 8, the pin 3, the carrier 4 and the chip is plastic-sealed to form a plastic sealing layer 9.

[0042] The high-voltage chip 2 and the low-voltage chip 1 are both insulated and fixed on the carrier 4. Specifically, first, an insulating reinforcement body 7 is bonded under the high-voltage chip 2, and then the high-voltage chip 2 and the insulating reinforcement body 7 are firmly bonded by high-temperature baking. Then, the high-voltage chip 2 and the insulating reinforcement body 7 are fixed on the carrier 4 as a whole by a liquid or solid insulating adhesive 6, and then the high-voltage chip 2 and the pin 3 and the low-voltage chip 1 are interconnected by welding wires.

[0043] In a preferred embodiment, the insulation reinforcement body 7 can be any form of insulation body such as DAF film, dummy film, glass sheet, etc., wherein the DAF film is an organic film that can be bonded to the chip at high temperature, the dummy film is a silicon sheet without a circuit on the surface; and the glass sheet is a glass of a certain thickness. The high-voltage chip 2 and the insulation reinforcement body 7 will form a thicker entity.

[0044] By pre-welding the insulating reinforcement 7 on the high-voltage chip 2 as a solid body, the insulation performance of the high-voltage chip 2 is improved, the insulation requirements of the high-voltage chip 2, the frame carrier 4 and the low-voltage chip 1 of the traditional SLIC packaging structure are improved, the thickness and size of the insulating adhesive 6 can be more flexible, and the high-voltage isolation performance is better.

[0045] In the description of the present application, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0046] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other at will.

Claims

1. A packaging structure for improving the withstand voltage performance and creepage distance of a high-voltage SLIC chip, characterized in that: include: A low-voltage chip (1), a high-voltage chip (2), a pin (3), an insulation reinforcement body (7), and a carrier (4); The low-voltage chip (1) and the high-voltage chip (2) are insulated and fixed on the surface of the carrier (4); the pins (3) are fixedly arranged around the carrier (4); the pins (3) are electrically connected to the low-voltage chip (1) via semiconductor bonding gold wires (5); and the pins (3) are electrically connected to the high-voltage chip (2) via semiconductor bonding gold wires (5); The pins (3) include high-voltage pins (3) and low-voltage pins (3), and the spacing between the high-voltage pins (3) is greater than the spacing between the low-voltage pins (3); The insulation reinforcement body (7) is arranged between the high-voltage chip (2) and the carrier (4), and the top surface and the bottom surface of the insulation reinforcement body (7) are fixedly connected to the high-voltage chip (2) and the carrier (4) respectively.

2. The packaging structure for improving the withstand voltage performance and creepage distance of a high-voltage SLIC chip according to claim 1, characterized in that: The spacing between the low-voltage pins (3) is d, the spacing between the high-voltage pins (3) is D, and D=2d.

3. The packaging structure for improving the withstand voltage performance and creepage distance of a high-voltage SLIC chip according to claim 1, characterized in that: The high-voltage pin (3) and the low-voltage pin (3) are respectively arranged on different sides of the carrier (4).

4. The packaging structure for improving the withstand voltage performance and creepage distance of a high-voltage SLIC chip according to claim 3, characterized in that: The high-voltage pins (3) are arranged on two opposite sides of the carrier (4), and the low-voltage pins (3) are arranged on the other two opposite sides of the carrier (4).

5. The packaging structure for improving the withstand voltage performance and creepage distance of a high-voltage SLIC chip according to claim 1, characterized in that: It also includes an insulating pad layer (8), wherein the insulating pad layer (8) is filled and arranged between the pins (3).

6. The packaging structure for improving the withstand voltage performance and creepage distance of a high-voltage SLIC chip according to claim 1, characterized in that: The insulation reinforcement (7) is any one of a DAF film, a dummy film and a glass sheet.

7. A chip, characterized in that: A packaging structure as claimed in any one of claims 1 to 6 is used to improve the voltage resistance and creepage distance of a high-voltage SLIC chip.

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