Protection circuit and power supply device for power supply control system

Abstract

The utility model discloses a protection circuit and a power supply device for a power supply control system, and relates to the field of circuits, and an output unit is used for outputting a driving signal; the input unit is connected with the output unit, and the input unit is used for transmitting a driving signal to the output unit; the pull-down unit is connected with the output unit and is used for enabling the output unit to stop outputting the driving signal; the protection unit is connected with the pull-down unit and is used for inputting a stop signal to the pull-down unit; and the delay unit is arranged between the pull-down unit and the protection unit and is used for controlling the connection or disconnection between the protection unit and the pull-down unit. The PWM signal can be efficiently, rapidly and accurately enabled to be turned off, a main circuit power device is protected, the service life of the power device is prolonged, the reliability of whole equipment is improved, and meanwhile the defect that due to the fact that all devices of a circuit system are inconsistent in response, misoperation of a protection circuit is caused is overcome.

Description

Technical Field

[0001] The present application relates to the field of circuits, and in particular to a protection circuit and a power supply device for a power control system. Background Art

[0002] With the rapid development of power electronics technology, nonlinear switching power supplies inject a large number of multiple harmonics into the power grid. Severely distorted grid waveforms may cause power supply equipment failures. The power control system needs to cope with limit tests and protection control logic in different usage scenarios, and protection strategies for possible input overvoltage, input undervoltage, power device overtemperature, output overcurrent, output short circuit, emergency stop, water shortage, etc. Therefore, a reliable, stable, fast and efficient protection circuit of the power control system is increasingly used in the power control system. Summary of the invention

[0003] The embodiments of the present application provide a protection circuit for a power control system and a switch protection circuit and a power supply device thereof.

[0004] According to a first aspect of an embodiment of the present application, a protection circuit for a power control system is provided, and the protection circuit for a power control system includes:

[0005] An output unit, the output unit is used to output a driving signal;

[0006] An input unit, the input unit is connected to the output unit, and the input unit is used to transmit a driving signal to the output unit;

[0007] a pull-down unit, the pull-down unit being connected to the output unit and configured to stop the output unit from outputting a driving signal;

[0008] a protection unit, the protection unit being connected to the pull-down unit and being used for inputting a stop signal to the pull-down unit;

[0009] A delay unit is provided between the pull-down unit and the protection unit, and is used to control the connection or disconnection between the protection unit and the pull-down unit.

[0010] In some embodiments, the output unit includes a driving chip and a driving transistor, and the driving chip includes a first control input terminal, a second control input terminal, a first enable terminal, a second enable terminal, a driving power input terminal, a driving ground terminal, a first output terminal, and a second output terminal;

[0011] The first control input terminal and the second control input terminal are respectively connected to the input unit, the first enable terminal is connected to the pull-down unit, the first output terminal and the second output terminal are respectively connected to the driving transistor, the driving power input terminal is connected to the first electrical frequency signal terminal, and the driving ground terminal is connected to the second electrical frequency signal terminal.

[0012] In some embodiments, the pull-down unit includes a first transistor and a comparator, the comparator includes a comparison output terminal, a negative input terminal, and a positive input terminal, and the first transistor includes a first transistor first electrode, a first transistor second electrode, and a first transistor gate;

[0013] The first electrode of the first transistor is connected to the output unit, the second electrode of the first transistor is connected to the second electrical frequency signal terminal, the gate of the first transistor is connected to the comparison output terminal, the negative input terminal is connected to the protection unit, and the positive input terminal is connected to the first electrical frequency signal terminal.

[0014] In some embodiments, the pull-down unit further includes a comparison diode and a comparison resistor, the comparison diode and the comparison resistor are connected to each other, and the comparison diode and the comparison resistor are connected in parallel with the comparator and are connected to the comparison output terminal and the negative input terminal.

[0015] In some embodiments, the protection unit includes multiple diodes, the diodes include an anode end and a cathode end, the anode ends of the multiple diodes are connected to each other, and the anode ends are connected to the pull-down unit, and the cathodes of the multiple diodes are respectively connected to the protection signal input end.

[0016] In some embodiments, the delay unit includes a relay, a timing chip, and a second transistor, the second transistor includes a second transistor first electrode, a second transistor second electrode, and a second transistor gate, the relay is connected to the second transistor first electrode, the second transistor second electrode is connected to the second electrical frequency signal end, the second transistor gate is connected to the timing chip, and the timing chip controls the second transistor gate and thus the opening or closing of the relay.

[0017] In some embodiments, the delay unit also includes a diode, a first delay resistor, and a first delay capacitor. The diode is arranged in parallel with the relay, the first delay resistor is respectively connected to the second electrode of the second transistor and the gate of the second transistor, and the first delay capacitor is respectively connected to the second electrode of the second transistor and the gate of the second transistor.

[0018] In some embodiments, the delay unit further includes an adjustable capacitor, a second delay capacitor, and a second delay resistor, and the timing chip includes a trigger input terminal, a discharge terminal, a threshold terminal, a delay power input terminal, a timing output terminal, a delay ground terminal, and a control voltage terminal;

[0019] The delay power supply input terminal is connected to the first electrical frequency signal terminal, the delay ground terminal is connected to the second electrical frequency signal terminal, the adjustable capacitor is connected to the second delay resistor, and the end of the adjustable capacitor away from the second delay resistor is connected to the second electrical frequency signal terminal, the end of the second delay resistor away from the adjustable capacitor is connected to the first electrical frequency signal terminal, the trigger input terminal and the threshold terminal are connected between the adjustable capacitor and the second delay resistor, the second delay capacitor is arranged between the control voltage terminal and the second electrical frequency signal terminal, and the timing output terminal is connected to the gate of the second transistor.

[0020] In some embodiments, the delay unit further includes an inverter and a reverse capacitor, the inverter includes a reverse input terminal, a reverse output terminal, a reverse power input terminal and a reverse ground terminal, the input terminal is connected to the timing output terminal, the reverse output terminal is connected to the gate of the second transistor, the reverse power input terminal is connected to the first electrical frequency signal terminal, and the reverse ground terminal is connected to the second electrical frequency signal terminal;

[0021] One end of the reverse capacitor is connected to the power input end, and the other end of the reverse capacitor is connected to the second electrical frequency signal end.

[0022] According to a second aspect of the embodiments of the present application, a power supply device is provided, wherein the power supply device includes the protection circuit for a power supply control system described in the above embodiments.

[0023] The technical solution provided by this application may have the following beneficial effects:

[0024] The present application can efficiently, quickly and accurately enable and shut down PWM signals by setting output units, input units, pull-down units, protection units and delay units, so as to protect the power devices of the main circuit, improve the life of the power devices and the reliability of the whole equipment; solve the defect of malfunction of the protection circuit caused by inconsistent responses of various devices in the circuit system; cleverly use the hysteresis characteristics of the comparator to realize the fault self-blocking PWM drive function; and adopt the line-OR circuit structure to realize the normalization of multi-path fault levels.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1It is a structural diagram of an embodiment of the present application.

[0027] Figure 2 It is a structural diagram of an embodiment of the present application.

[0028] Figure 3 It is a schematic diagram of the structure of the output unit and the input unit in one embodiment of the present application.

[0029] Figure 4 It is a structural diagram of a protection unit in an embodiment of the present application.

[0030] Figure 5 It is a schematic diagram of the structure of a pull-down unit in an embodiment of the present application.

[0031] Figure 6 It is a schematic diagram of the structure of a delay unit in an embodiment of the present application.

[0032] Description of Reference Numerals

[0033] Output unit 100

[0034] Input unit 200

[0035] Pull-down unit 300

[0036] Protection unit 400

[0037] Delay unit 500 DETAILED DESCRIPTION

[0038] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0039] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" means two or more. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. "On" and / or "below" and the like are only for the convenience of explanation, and are not limited to a position or a spatial orientation. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0040] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0041] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0042] The use of "adapted to" or "configured to" in this specification is meant to be open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

[0043] The triangles, rectangles, trapezoids, pentagons or hexagons used in the specification and claims of this application are not in a strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0044] The term "about" as used in the specification and claims of this application refers to a numerical value that is not strictly limited and allows for process and measurement errors.

[0045] The transistors used in the present application can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0046] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0047] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0048] With the rapid development of power electronics technology, nonlinear switching power supplies inject a large number of multiple harmonics into the power grid. Severely distorted grid waveforms may cause power supply equipment failures. The power control system needs to cope with limit tests and protection control logic in different usage scenarios, and protection strategies for possible input overvoltage, input undervoltage, power device overtemperature, output overcurrent, output short circuit, emergency stop, water shortage, etc. Therefore, a reliable, stable, fast and efficient protection circuit of the power control system is increasingly used in the power control system.

[0049] refer to Figure 1 As shown, the present application proposes a protection circuit for a power control system, comprising: an output unit 100, an input unit 200, a pull-down unit 300, a protection unit 400 and a delay unit 500. The output unit 100 is used to output a driving signal; the input unit 200 is connected to the output unit 100, and the input unit 200 is used to transmit a driving signal to the output unit 100; the pull-down unit 300 is connected to the output unit 100, and is used to stop the output unit 100 from outputting a driving signal; the protection unit 400 is connected to the pull-down unit 300, and is used to input a stop signal to the pull-down unit 300; the delay unit 500 is arranged between the pull-down unit 300 and the protection unit 400, and is used to control the connection or disconnection of the protection unit 400 and the pull-down unit 300.

[0050] The present application designs a pull-down unit 300, and one end of the pull-down unit 300 is connected to the output unit 100 and the other end is connected to the protection unit 400. When the protection unit 400 inputs a stop signal, the pull-down unit 300 causes the output unit 100 to stop outputting a driving signal.

[0051] In order to avoid the defect of malfunction of the protection circuit caused by inconsistent responses of various components in the circuit system, the present application sets a delay unit 500 in the protection circuit, and sets the delay unit 500 between the pull-down unit 300 and the protection unit 400, and sets it to connect the protection unit 400 with the pull-down unit 300 for a certain time after power-on.

[0052] In one embodiment, reference Figure 1 , Figure 2 as well as Figure 3 As shown, the output unit 100 includes a driving chip U1 and a driving transistor, and the driving chip U1 includes a first control input terminal inA, a second control input terminal inB, a first enable terminal ENA, a second enable terminal ENB, a driving power input terminal VCC, a driving ground terminal GND, a first output terminal OUTA and a second output terminal OUTB; the first control input terminal inA and the second control input terminal inB are respectively connected to the input unit 200, the first enable terminal ENA is connected to the pull-down unit 300, the first output terminal OUTA and the second output terminal OUTB are respectively connected to the driving transistor, the driving power input terminal VCC is connected to the first electrical frequency signal terminal, and the driving ground terminal GND is connected to the second electrical frequency signal terminal GND.

[0053] The driver chip U1 proposed in this application is a PWM drive logic chip with enable on and off functions, which can efficiently, quickly and accurately enable and shut down PWM signals, thereby protecting the main circuit power devices, improving the life of the power devices and the reliability of the entire equipment.

[0054] In one embodiment, reference Figure 1 , Figure 2 as well as Figure 5 As shown, the pull-down unit 300 includes a first transistor Q1 and a comparator U2, the comparator U2 includes a comparison output terminal, a negative input terminal, and a positive input terminal, the first transistor Q1 includes a first transistor Q1 first electrode, a first transistor Q1 second electrode, and a first transistor Q1 gate; the first transistor Q1 first electrode is connected to the output unit 100, the first transistor Q1 second electrode is connected to the second electrical frequency signal terminal GND, the first transistor Q1 gate is connected to the comparison output terminal, the negative input terminal is connected to the protection unit 400, and the positive input terminal is connected to the first electrical frequency signal terminal.

[0055] The gate of the first transistor Q1 is connected to the comparison output terminal, the negative input terminal is connected to the protection unit 400, and the positive input terminal is connected to the first electrical frequency signal terminal. Therefore, when the protection unit 400 inputs the protection signal, the negative input terminal will be pulled down, so that the comparison output terminal of the comparator U2 outputs a positive voltage, so that the first transistor Q1 is turned on, and the first transistor Q1 will be turned on to pull down the first enable terminal ENA and the second enable terminal ENB of the driving chip U1, so as to achieve the function of self-blocking PWM driving.

[0056] For further information, please continue to refer to Figure 1 , Figure 2 as well as Figure 5 As shown, the pull-down unit 300 further includes a comparison diode DV1 and a comparison resistor R14, the comparison diode DV1 and the comparison resistor R14 are connected to each other, and the comparison diode DV1 and the comparison resistor R14 are connected in parallel with the comparator U2, and are connected to the comparison output terminal and the negative input terminal.

[0057] Pin 5 of comparator U2 is the positive input of the comparator, and pin 6 of comparator U2 is the negative input of the comparator. When the input pin 6 voltage of comparator U2 is less than the pin 5 voltage of U2, pin 7 of comparator U2 outputs a high level, and the high level voltage raises the pin 5 voltage of comparator U2 through the comparison diode DV1 and the comparison resistor R14 loop, so that the pin 5 voltage of comparator U2 will always be greater than the input pin 6 voltage of comparator U2. At this time, pin 7 of comparator U2 will always be in an output high level state, and the first transistor Q1 will be turned on to pull down the first enable terminal ENA and the second enable terminal ENB of the driver chip U1, thereby achieving the function of self-blocking PWM drive.

[0058] In one embodiment, reference Figure 1 , Figure 2 as well as Figure 4 As shown, the protection unit 400 includes multiple diodes D, and the diodes include an anode terminal and a cathode terminal. The anode terminals of the multiple diodes D are connected to each other, and the anode terminals are connected to the pull-down unit 300, and the cathodes of the multiple diodes are respectively connected to the protection signal input terminal.

[0059] Since the diodes are all common anode diodes, the anode common terminal 3 is connected together. Any fault signal that pulls down any cathode will pull down the common terminal 3. This logic is a line-or relationship, thereby achieving normalization of multi-path fault levels.

[0060] In one embodiment, reference Figure 1 , Figure 2 as well as Figure 6As shown, the delay unit 500 includes a relay HF1, a timing chip U3, and a second transistor Q2. The second transistor Q2 includes a first electrode of the second transistor Q2, a second electrode of the second transistor Q2, and a gate of the second transistor Q2. The relay HF1 is connected to the first electrode of the second transistor Q2, the second electrode of the second transistor Q2 is connected to the second electrical frequency signal terminal GND, and the gate of the second transistor Q2 is connected to the timing chip U3. The timing chip U3 controls the gate of the second transistor Q2 and thus the opening or closing of the relay HF1.

[0061] The timing chip U3 controls the second transistor Q2 to be turned on, so that the relay HF1 starts to work to connect or disconnect the protection unit 400 and the pull-down unit 300 .

[0062] Please continue to refer to Figure 1 , Figure 2 as well as Figure 6 As shown, the delay unit 500 also includes a delay diode D3, a first delay resistor R18, and a first delay capacitor C7. The delay diode D3 is arranged in parallel with the relay HF1. ​​The first delay resistor R18 is respectively connected to the second electrode of the second transistor Q2 and the gate of the second transistor Q2. The first delay capacitor C7 is respectively connected to the second electrode of the second transistor Q2 and the gate of the second transistor Q2.

[0063] At the moment of relay HF1 switching, the induced electromotive force inside relay HF1 will generate a reverse voltage, which may damage the components of the control relay HF1 such as transistors. Adding a delay diode D3 can form a reverse parallel connection, directing the reverse voltage to the delay diode D3, and protecting components such as transistors from damage. In some scenarios, high-voltage and high-current charges may be generated when relay HF1 switches, endangering the safety of other circuit components. At this time, the charge can be quickly eliminated by connecting the delay diode D3 in series to avoid safety problems caused by charge accumulation. In some scenarios, the response speed of relay HF1 is required to be faster. Adding a delay diode D3 to connect the two ends of the relay HF1 coil in parallel can suppress the induced electromotive force in the coil by the reverse voltage generated by the delay diode D3 at the moment when the relay HF1 is closed, so that the relay HF1 is closed faster. Therefore, the delay diode D3 here can achieve the effect of protecting the relay HF1, quickly eliminating the charge on the relay HF1, and improving the response speed of the relay HF1. ​​The first delay resistor R18 and the first delay capacitor C7 in this embodiment can achieve the function of filtering and protecting the triode.

[0064] Further, in this embodiment, reference Figure 1 , Figure 2 as well as Figure 6As shown, the delay unit 500 also includes an adjustable capacitor E1, a delay capacitor C5, and a delay resistor R16, and the timing chip U3 includes a trigger input terminal Tri, a discharge terminal dischg, a threshold terminal THV, a delay power input terminal VCC, a timing output terminal out, a reverse ground terminal GND, and a control voltage terminal Ctr V;

[0065] The delay power input terminal VCC is connected to the first electrical frequency signal terminal, the delay ground terminal GND is connected to the second electrical frequency signal terminal GND, the adjustable capacitor E1 is connected to the second delay resistor R16, and one end of the adjustable capacitor E1 away from the second delay resistor R16 is connected to the second electrical frequency signal terminal GND, one end of the second delay resistor R16 away from the adjustable capacitor E1 is connected to the first electrical frequency signal terminal, the trigger input terminal Tri and the threshold terminal THV are connected between the adjustable capacitor E1 and the second delay resistor R16, the second delay capacitor C5 is arranged between the control voltage terminal Ctr V and the second electrical frequency signal terminal GND, and the timing output terminal out is connected to the gate of the second transistor Q2.

[0066] In one embodiment, continue to refer to Figure 1 , Figure 2 as well as Figure 6 As shown, the delay unit 500 also includes an inverter U4 and a reverse capacitor C6. The inverter U4 includes a reverse input terminal, a reverse output terminal, a reverse power input terminal VCC and a reverse ground terminal GND. The reverse input terminal is connected to the timing output terminal out, the reverse output terminal is connected to the gate of the second transistor Q2, the reverse power input terminal VCC is connected to the first electrical frequency signal terminal, and the reverse ground terminal GND is connected to the second electrical frequency signal terminal GND; one end of the reverse capacitor C6 is connected to the reverse power input terminal VCC, and the other end of the reverse capacitor C6 is connected to the second electrical frequency signal terminal GND.

[0067] In this embodiment, the inverter U4 is incorporated between the relay HF1 and the timing chip U3, thereby helping to reverse the voltage output by the timing chip U3. The above delay unit 500 can avoid erroneous protection action and solve the defect of erroneous action of the protection circuit caused by inconsistent response of various components in the circuit system.

[0068] The protection circuit for the power control system proposed in the present application can efficiently, quickly and accurately enable and shut down the PWM signal, thereby protecting the power devices of the main circuit, improving the life of the power devices and the reliability of the entire equipment; it solves the defect of malfunction of the protection circuit caused by inconsistent responses of various devices in the circuit system; it cleverly uses the hysteresis characteristics of the comparator to realize the fault self-blocking PWM drive function; and adopts a line-OR circuit structure to realize the normalization of multi-path fault levels.

[0069] The present application also proposes a power supply device, which includes the protection circuit for a power control system described in the above embodiment. Since the power supply device has all the embodiments of the protection circuit of the power control system, the advantages and functions of the protection circuit of the power control system are also possessed by the power supply device.

[0070] In the present application, the structural embodiments and method embodiments may complement each other if they do not conflict.

[0071] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. For example, those of ordinary skill in the art can use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features can be grouped together to simplify the application. This should not be interpreted as a feature of an application that does not require protection being necessary for any claim. On the contrary, the subject matter of the present application may be less than all the features of the embodiments of a specific application. Thus, the following claims are incorporated into the specific embodiments as examples or embodiments, wherein each claim is independently used as a separate embodiment, and it is considered that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present application should be determined with reference to the full scope of the equivalent forms of the attached claims and these claims.

[0072] The present application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown in the present application, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0073] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0074] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The terms "plurality" and "several" refer to two or more than two, unless otherwise clearly defined.

[0075] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure of the present application. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0076] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A protection circuit for a power control system, characterized in that: include: An output unit, the output unit is used to output a driving signal; An input unit, the input unit is connected to the output unit, and the input unit is used to transmit a driving signal to the output unit; a pull-down unit, the pull-down unit being connected to the output unit and configured to stop the output unit from outputting a driving signal; a protection unit, the protection unit being connected to the pull-down unit and being used for inputting a stop signal to the pull-down unit; A delay unit is provided between the pull-down unit and the protection unit, and is used to control the connection or disconnection between the protection unit and the pull-down unit.

2. The protection circuit for a power control system according to claim 1, characterized in that: The output unit includes a driving chip and a driving transistor, and the driving chip includes a first control input terminal, a second control input terminal, a first enable terminal, a second enable terminal, a driving power input terminal, a driving ground terminal, a first output terminal, and a second output terminal; The first control input terminal and the second control input terminal are respectively connected to the input unit, the first enable terminal is connected to the pull-down unit, the first output terminal and the second output terminal are respectively connected to the driving transistor, the driving power input terminal is connected to the first electrical frequency signal terminal, and the driving ground terminal is connected to the second electrical frequency signal terminal.

3. The protection circuit for a power control system according to claim 1, characterized in that: The pull-down unit includes a first transistor and a comparator, the comparator includes a comparison output terminal, a negative input terminal, and a positive input terminal, and the first transistor includes a first transistor first electrode, a first transistor second electrode, and a first transistor gate; The first electrode of the first transistor is connected to the output unit, the second electrode of the first transistor is connected to the second electrical frequency signal terminal, the gate of the first transistor is connected to the comparison output terminal, the negative input terminal is connected to the protection unit, and the positive input terminal is connected to the first electrical frequency signal terminal.

4. The protection circuit for a power control system according to claim 3, characterized in that: The pull-down unit further includes a comparison diode and a comparison resistor, wherein the comparison diode and the comparison resistor are connected to each other, and the comparison diode and the comparison resistor are connected in parallel with the comparator and are connected to the comparison output terminal and the negative input terminal.

5. The protection circuit for a power control system according to claim 1, characterized in that: The protection unit includes a plurality of diodes, the diodes include an anode terminal and a cathode terminal, the anode terminals of the plurality of diodes are connected to each other, and the anode terminals are connected to the pull-down unit, and the cathodes of the plurality of diodes are respectively connected to the protection signal input terminal.

6. The protection circuit for a power control system according to claim 1, characterized in that: The delay unit includes a relay, a timing chip, and a second transistor. The second transistor includes a second transistor first electrode, a second transistor second electrode, and a second transistor gate. The relay is connected to the second transistor first electrode, the second transistor second electrode is connected to the second electrical frequency signal end, and the second transistor gate is connected to the timing chip. The timing chip controls the second transistor gate and thus the opening or closing of the relay.

7. The protection circuit for a power control system according to claim 6, characterized in that: The delay unit also includes a diode, a first delay resistor, and a first delay capacitor. The diode is arranged in parallel with the relay, the first delay resistor is respectively connected to the second electrode of the second transistor and the gate of the second transistor, and the first delay capacitor is respectively connected to the second electrode of the second transistor and the gate of the second transistor.

8. The protection circuit for a power control system according to claim 6, characterized in that: The delay unit also includes an adjustable capacitor, a second delay capacitor, and a second delay resistor, and the timing chip includes a trigger input terminal, a discharge terminal, a threshold terminal, a delay power input terminal, a timing output terminal, a delay ground terminal, and a control voltage terminal; The delay power supply input terminal is connected to the first electrical frequency signal terminal, the delay ground terminal is connected to the second electrical frequency signal terminal, the adjustable capacitor is connected to the second delay resistor, and the end of the adjustable capacitor away from the second delay resistor is connected to the second electrical frequency signal terminal, the end of the second delay resistor away from the adjustable capacitor is connected to the first electrical frequency signal terminal, the trigger input terminal and the threshold terminal are connected between the adjustable capacitor and the second delay resistor, the second delay capacitor is arranged between the control voltage terminal and the second electrical frequency signal terminal, and the timing output terminal is connected to the gate of the second transistor.

9. The protection circuit for a power control system according to claim 8, characterized in that: The delay unit further includes an inverter and a reverse capacitor, the inverter includes a reverse input terminal, a reverse output terminal, a reverse power input terminal and a reverse ground terminal, the input terminal is connected to the timing output terminal, the reverse output terminal is connected to the gate of the second transistor, the reverse power input terminal is connected to the first electrical frequency signal terminal, and the reverse ground terminal is connected to the second electrical frequency signal terminal; One end of the reverse capacitor is connected to the power input end, and the other end of the reverse capacitor is connected to the second electrical frequency signal end.

10. A power supply device, characterized in that: The power supply device includes a protection circuit for a power supply control system as described in any one of claims 1-9.

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