External network isolation circuit

Abstract

The utility model relates to an extranet isolating circuit, and aims to solve the technical problem that an isolating circuit for isolating an extranet host from an external network port is lacked in the prior art, so that the extranet host cannot be prevented from being attacked when data query is not needed. Comprising a level conversion circuit, a micro-control unit, a first optical coupler isolation circuit, a second optical coupler isolation circuit, an internet access control circuit and an internet access connection circuit, one end of the level conversion circuit is connected with a serial port of an external network host, the other end of the level conversion circuit is connected with the micro-control unit, and the micro-control unit is connected with the input end of the first optical coupler isolation circuit and the input end of the second optical coupler isolation circuit. The output end of the first optical coupler isolation circuit and the output end of the second optical coupler isolation circuit are connected with the network port control circuit, the control end of the network port control circuit is connected with the controlled end of the network port connection circuit, and the network port connection end of the network port connection circuit is connected with the physical network interface.

Description

Technical Field

[0001] The utility model belongs to the technical field of external network isolation, and particularly relates to an external network isolation circuit. Background Art

[0002] Intranet, also known as local area network, is a computer communication network that connects various computers, external devices and databases within a local geographical range. Extranet, also known as wide area network or public network, is a remote network that connects computer communications in local area networks or metropolitan area networks in different regions. It usually spans a large physical range, ranging from tens of kilometers to thousands of kilometers. It can connect multiple regions, cities and countries, or span several continents and provide long-distance communications, forming an international remote network.

[0003] As network security becomes more and more important, in order to avoid attacks from external networks, confidential units and organizations generally set up their own intranets to separate internal and external networks and protect the security of internal network operations.

[0004] At present, confidential units and organizations can only use the intranet in their daily work due to the confidentiality of the unit. If they need to access the external network, they need to apply to go to the external host and connect to the external network on the external host to query information.

[0005] The prior art has at least the following problems: there is a lack of an isolation circuit for isolating the external network host from the external network port, and it is impossible to prevent the external network host from being attacked when data query is not required. Utility Model Content

[0006] The utility model provides an external network isolation circuit, aiming to solve the technical problem that the prior art lacks an isolation circuit for isolating an external network host from an external network port, and cannot prevent the external network host from being attacked when data query is not needed.

[0007] The utility model solves the above technical problems with the following technical solutions: an external network isolation circuit, comprising:

[0008] A level conversion circuit, a micro control unit, a first optocoupler isolation circuit, a second optocoupler isolation circuit, a network port control circuit and a network port connection circuit; one end of the level conversion circuit is connected to the serial port of the external network host, the other end of the level conversion circuit is connected to the level instruction input port of the micro control unit, the first level control port of the micro control unit is connected to the input end of the first optocoupler isolation circuit, the second level control port of the micro control unit is connected to the input end of the second optocoupler isolation circuit, the output end of the first optocoupler isolation circuit is connected to the first level receiving port of the network port control circuit, the output end of the second optocoupler isolation circuit is connected to the second level receiving port of the network port control circuit, the command output end of the micro control unit is connected to the command receiving end of the network port control circuit, the control end of the network port control circuit is connected to the controlled end of the network port connection circuit, and the network port connection end of the network port connection circuit is connected to the physical network interface.

[0009] The beneficial effect of the utility model is as follows: the utility model controls the opening and closing of the first optocoupler isolation circuit and the second optocoupler isolation circuit through a microcontroller unit. When the external network host needs to connect to the external network for data query, the first optocoupler isolation circuit and the second optocoupler isolation circuit are controlled to be opened, so that the external network host is connected to the physical network interface. When the external network host does not need to connect to the external network for data query, the first optocoupler isolation circuit and the second optocoupler isolation circuit are controlled to be closed, so that the external network host is isolated from the physical network interface, thereby ensuring that the external network host will not be attacked when data query is not needed.

[0010] On the basis of the above technical solution, the present invention can also be improved as follows.

[0011] Furthermore, the micro control unit comprises an STM32 chip U1, and a clock signal input terminal of the STM32 chip U1 is connected to a first oscillation circuit.

[0012] The beneficial effect of adopting the above further scheme is: the utility model uses the STM32 chip U1 as the single-chip microcomputer control chip, and the STM32 chip U1 has the advantages of high performance and low power consumption, and is easy to learn and debug.

[0013] Furthermore, the first oscillator circuit comprises: a capacitor C1, a capacitor C2, a resistor R1 and a crystal oscillator Y1;

[0014] One end of the resistor R1 is connected to the OSC_I N pin of the STM32 chip U1, the other end of the R1 is connected to the OSC_OUT pin of the STM32 chip U1, the crystal oscillator Y1 is connected to the resistor R1 in parallel, one end of the capacitor C1 is connected to one end of the crystal oscillator Y1, one end of the capacitor C1 is connected to one end of the capacitor C2 and grounded, and the other end of the capacitor C2 is connected to the other end of the crystal oscillator Y1.

[0015] The beneficial effect of adopting the above further solution is that in the utility model, by setting up the first oscillation circuit, a very stable oscillation frequency can be provided, and the amplitude is adjustable and the frequency range is wide.

[0016] Furthermore, the level conversion circuit comprises: a serial interface plug J1, a level conversion chip U4, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6 and a capacitor C7;

[0017] The VCC pin of the level conversion chip U4 is externally connected to a 3.3V voltage, one end of the capacitor C3 is connected to the C1+ pin of the level conversion chip U4, and the other end of the capacitor C3 is connected to the C1- pin of the level conversion chip U4, one end of the capacitor C4, the capacitor C5 and the capacitor C6 are respectively connected to the VCC pin, the V+ pin and the V- pin of the level conversion chip U4, the other ends of the capacitors C4, C5 and C6 are all connected to the GND pin of the level conversion chip U4, and the GND pin is grounded, one end of the capacitor C7 is connected to the C2+ pin of the level conversion chip U4, and the other end of the capacitor C7 is connected to the C2- pin of the level conversion chip U4, the T1OUT pin and the R1 IN pin of the level conversion chip U4 are both connected to the serial interface plug J1, the T1 IN pin of the level conversion chip U4 is connected to the STX pin of the STM32 chip U1, and the R1OUT pin of the level conversion chip U4 is connected to the SRX pin of the STM32 chip U1.

[0018] The beneficial effect of adopting the above further solution is that in the present invention, by providing a level conversion circuit, the leakage current can be reduced, thereby improving the overall efficiency and reliability of the circuit.

[0019] Furthermore, the serial interface plug J1 is a DB9 plug, the T1OUT pin and R1 IN pin of the level conversion chip U4 are connected to pins 2 and 3 of the DB9 plug respectively, and pins 5, 10 and 11 of the DB9 plug are grounded.

[0020] The beneficial effect of adopting the above further solution is: in this embodiment, by setting the serial interface plug J1 to a DB9 plug, it has the advantages of simple structure, low cost, good compatibility and good stability.

[0021] Further, the first optical coupler isolation circuit comprises: a resistor R2, a resistor R3 and a first optical coupler isolator U2;

[0022] An input end of the first optocoupler isolator U2 is connected to one end of the resistor R2, the other end of the resistor R2 is externally connected to a 3.3V voltage, another input end of the first optocoupler isolator U2 is connected to the PA1 pin of the STM32 chip U1, an output end of the first optocoupler isolator U2 is grounded, another output end of the first optocoupler isolator U2 is connected to one end of the resistor R3 and to the network port control circuit, and the other end of the resistor R3 is externally connected to a 1.8V voltage.

[0023] The beneficial effect of adopting the above further solution is: in this embodiment, by providing the first optical coupling isolation circuit, it is possible to isolate the strong and weak electricity well to ensure the opening and closing of the line.

[0024] Furthermore, the second optical coupler isolation circuit comprises: a resistor R4, a resistor R5 and a second optical coupler isolator U5;

[0025] An input end of the second optocoupler isolator U5 is connected to one end of the resistor R4, the other end of the resistor R4 is externally connected to a 3.3V voltage, another input end of the second optocoupler isolator U5 is connected to the PA2 pin of the STM32 chip U1, an output end of the second optocoupler isolator U5 is grounded, another output end of the second optocoupler isolator U5 is connected to one end of the resistor R5 and to the network port control circuit, and the other end of the resistor R5 is externally connected to a 3.3V voltage.

[0026] Furthermore, the network port control circuit comprises: a network port control chip U3, a resistor R6, a resistor R7, a diode D1 and a second oscillation circuit;

[0027] A first common connection port composed of multiple VCC33 pins of the network port control chip U3 is connected to an input end of the first optocoupler isolator U2, a second common connection port composed of multiple VCC18 pins of the network port control chip U3 is connected to an input end of the second optocoupler isolator U5, an RSETE pin of the network port control chip U3 is connected to one end of the resistor R6, and the other end of the resistor R6 is grounded, an RST1 pin of the network port control chip U3 is connected to the PA1 pin of the STM32 chip U1, and is connected to one end of the resistor R7, and the other end of the resistor R7 is grounded, an I NT# pin of the network port control chip U3 is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the PA0 pin of the STM32 chip U1, and the network port control chip U3 is connected to the second oscillation circuit through the X1 pin and the X0 pin.

[0028] The beneficial effect of adopting the above further scheme is: in the utility model, by using an Ethernet chip as the network port control chip U3, the network port control circuit has the advantages of low electromagnetic radiation, low power consumption, bandwidth allocation, low latency and light weight.

[0029] Furthermore, the second oscillator circuit comprises: a capacitor C8, a capacitor C9 and a crystal oscillator Y2;

[0030] One end of the crystal oscillator Y2 is connected to the network port control chip U3 through the X1 pin, and is connected to one end of the capacitor C8, the other end of the capacitor C8 is connected to one end of the capacitor C9 and is grounded, the other end of the capacitor C9 is connected to the other end of the crystal oscillator Y2, and is connected to the network port control chip U3 through the X0 pin.

[0031] Further, the network port connection circuit includes: a network port connection chip U6, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R12, a capacitor C10, a capacitor C11 and a capacitor C12;

[0032] One end of the resistor R8 is connected to the TD- pin of the network port connection chip U6, the other end of the resistor R8 is connected to one end of the resistor R9, the other end of the resistor R9 is connected to the TD+ pin of the network port connection chip U6, one end of the capacitor C11 is connected between the resistor R8 and the resistor R9, the other end of the capacitor C11 is connected to one end of the capacitor C12 and grounded, the other end of the capacitor C12 is respectively connected to one end of the resistor R11 and one end of the resistor R10, the other end of the resistor R11 is connected to the RD+ pin of the network port connection chip U6, and the capacitor C11 is connected to the TD+ pin of the network port connection chip U6. The other end of the resistor R10 is connected to the RD-pin of the network port connection chip U6, the RCT pin and the TCT pin of the network port connection chip U6 are connected to one end of the capacitor C10 and are externally connected to a 3.3V voltage, the other end of the capacitor C10 is grounded, the LED(Y)_K pin of the network port connection chip U6 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the LED(G)_K pin of the network port connection chip U6, and the network port control circuit is connected between the resistor R12 and the resistor R13.

[0033] The beneficial effect of adopting the above further solution is: in the utility model, the network transformer chip is used as the network port connection chip U6, which increases the transmission distance and reduces the power consumption.

[0034] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural schematic diagram of an embodiment of the utility model;

[0036] Figure 2 It is a schematic diagram of the structure of the micro control unit of the utility model;

[0037] Figure 3 It is a structural schematic diagram of the first oscillation circuit of the utility model;

[0038] Figure 4 It is a structural schematic diagram of the level conversion circuit of the utility model;

[0039] Figure 5 It is a structural schematic diagram of a first optical coupling isolation circuit of the utility model;

[0040] Figure 6 It is a structural schematic diagram of the second optical coupling isolation circuit of the utility model;

[0041] Figure 7It is a structural schematic diagram of the network port control circuit of the utility model;

[0042] Figure 8 The utility model is a schematic diagram of the structure of the network port connection circuit. DETAILED DESCRIPTION

[0043] The principles and features of the present invention are described below. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0044] The following specific embodiments are used to describe in detail the technical solution of the utility model and how the technical solution of the utility model solves the above technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The following embodiments of the utility model will be described in conjunction with the accompanying drawings.

[0045] The present utility model embodiment provides a possible implementation method, such as Figure 1-Figure 8 As shown, an external network isolation circuit is provided, comprising:

[0046] A level conversion circuit, a micro control unit, a first optocoupler isolation circuit, a second optocoupler isolation circuit, a network port control circuit and a network port connection circuit; one end of the level conversion circuit is connected to the serial port of the external network host, the other end of the level conversion circuit is connected to the level instruction input port of the micro control unit, the first level control port of the micro control unit is connected to the input end of the first optocoupler isolation circuit, the second level control port of the micro control unit is connected to the input end of the second optocoupler isolation circuit, the output end of the first optocoupler isolation circuit is connected to the first level receiving port of the network port control circuit, the output end of the second optocoupler isolation circuit is connected to the second level receiving port of the network port control circuit, the command output end of the micro control unit is connected to the command receiving end of the network port control circuit, the control end of the network port control circuit is connected to the controlled end of the network port connection circuit, and the network port connection end of the network port connection circuit is connected to the physical network interface.

[0047] Among them, the utility model controls the opening and closing of the first optocoupler isolation circuit and the second optocoupler isolation circuit through a microcontroller unit. When the external network host needs to connect to the external network for data query, the first optocoupler isolation circuit and the second optocoupler isolation circuit are controlled to be opened, so that the external network host is connected to the physical network interface. When the external network host does not need to connect to the external network for data query, the first optocoupler isolation circuit and the second optocoupler isolation circuit are controlled to be closed, so that the external network host is isolated from the physical network interface, ensuring that the external network host will not be attacked when it does not need to query data.

[0048] Optionally, the micro control unit includes an STM32 chip U1, and a clock signal input end of the STM32 chip U1 is connected to a first oscillation circuit.

[0049] Among them, the utility model uses the STM32 chip U1 as the single-chip microcomputer control chip. The STM32 chip U1 has the advantages of high performance and low power consumption and is easy to learn and debug.

[0050] Optionally, the first oscillation circuit includes: a capacitor C1, a capacitor C2, a resistor R1 and a crystal oscillator Y1;

[0051] One end of the resistor R1 is connected to the OSC_I N pin of the STM32 chip U1, the other end of the R1 is connected to the OSC_OUT pin of the STM32 chip U1, the crystal oscillator Y1 is connected to the resistor R1 in parallel, one end of the capacitor C1 is connected to one end of the crystal oscillator Y1, one end of the capacitor C1 is connected to one end of the capacitor C2 and grounded, and the other end of the capacitor C2 is connected to the other end of the crystal oscillator Y1.

[0052] Among them, in the utility model, the first oscillation circuit is provided, which can provide a very stable oscillation frequency, and the amplitude is adjustable and the frequency range is wide.

[0053] Optionally, the level conversion circuit includes: a serial interface plug J1, a level conversion chip U4, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6 and a capacitor C7;

[0054] The VCC pin of the level conversion chip U4 is externally connected to a 3.3V voltage, one end of the capacitor C3 is connected to the C1+ pin of the level conversion chip U4, and the other end of the capacitor C3 is connected to the C1- pin of the level conversion chip U4, one end of the capacitor C4, the capacitor C5 and the capacitor C6 are respectively connected to the VCC pin, the V+ pin and the V- pin of the level conversion chip U4, the other ends of the capacitors C4, C5 and C6 are all connected to the GND pin of the level conversion chip U4, and the GND pin is grounded, one end of the capacitor C7 is connected to the C2+ pin of the level conversion chip U4, and the other end of the capacitor C7 is connected to the C2- pin of the level conversion chip U4, the T1OUT pin and the R1 IN pin of the level conversion chip U4 are both connected to the serial interface plug J1, the T1 IN pin of the level conversion chip U4 is connected to the STX pin of the STM32 chip U1, and the R1 The OUT pin is connected to the SRX pin of the STM32 chip U1.

[0055] Among them, in the utility model, by setting a level conversion circuit, the leakage current can be reduced, and the overall efficiency and reliability of the circuit can be improved.

[0056] Optionally, the serial interface plug J1 is a DB9 plug, the T1OUT pin and R1I N pin of the level conversion chip U4 are respectively connected to pin 2 and pin 3 of the DB9 plug, and pin 5, pin 10 and pin 11 of the DB9 plug are grounded.

[0057] In this embodiment, by setting the serial interface plug J1 as a DB9 plug, it has the advantages of simple structure, low cost, good compatibility and good stability.

[0058] Optionally, the first optical coupler isolation circuit includes: a resistor R2, a resistor R3 and a first optical coupler isolator U2;

[0059] An input end of the first optocoupler isolator U2 is connected to one end of the resistor R2, the other end of the resistor R2 is externally connected to a 3.3V voltage, another input end of the first optocoupler isolator U2 is connected to the PA1 pin of the STM32 chip U1, an output end of the first optocoupler isolator U2 is grounded, another output end of the first optocoupler isolator U2 is connected to one end of the resistor R3 and to the network port control circuit, and the other end of the resistor R3 is externally connected to a 1.8V voltage.

[0060] Among them, in this embodiment, by setting up the first optical coupling isolation circuit, it is possible to well isolate strong and weak electricity to ensure the opening and closing of the line.

[0061] Optionally, the second optical coupler isolation circuit includes: a resistor R4, a resistor R5 and a second optical coupler isolator U5;

[0062] An input end of the second optocoupler isolator U5 is connected to one end of the resistor R4, the other end of the resistor R4 is externally connected to a 3.3V voltage, another input end of the second optocoupler isolator U5 is connected to the PA2 pin of the STM32 chip U1, an output end of the second optocoupler isolator U5 is grounded, another output end of the second optocoupler isolator U5 is connected to one end of the resistor R5 and to the network port control circuit, and the other end of the resistor R5 is externally connected to a 3.3V voltage.

[0063] Optionally, the network port control circuit includes: a network port control chip U3, a resistor R6, a resistor R7, a diode D1 and a second oscillation circuit;

[0064] A first common connection port composed of multiple VCC33 pins of the network port control chip U3 is connected to an input end of the first optocoupler isolator U2, a second common connection port composed of multiple VCC18 pins of the network port control chip U3 is connected to an input end of the second optocoupler isolator U5, an RSETE pin of the network port control chip U3 is connected to one end of the resistor R6, and the other end of the resistor R6 is grounded, an RST1 pin of the network port control chip U3 is connected to the PA1 pin of the STM32 chip U1, and is connected to one end of the resistor R7, and the other end of the resistor R7 is grounded, an I NT# pin of the network port control chip U3 is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the PA0 pin of the STM32 chip U1, and the network port control chip U3 is connected to the second oscillation circuit through the X1 pin and the X0 pin.

[0065] Among them, in the utility model, an Ethernet chip is used as the network port control chip U3, so that the network port control circuit has the advantages of low electromagnetic radiation, low power consumption, bandwidth allocation, low latency and light weight.

[0066] Optionally, the second oscillation circuit includes: a capacitor C8, a capacitor C9 and a crystal oscillator Y2;

[0067] One end of the crystal oscillator Y2 is connected to the network port control chip U3 through the X1 pin, and is connected to one end of the capacitor C8, the other end of the capacitor C8 is connected to one end of the capacitor C9 and is grounded, the other end of the capacitor C9 is connected to the other end of the crystal oscillator Y2, and is connected to the network port control chip U3 through the X0 pin.

[0068] Optionally, the network port connection circuit includes: a network port connection chip U6, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R12, a capacitor C10, a capacitor C11 and a capacitor C12;

[0069] One end of the resistor R8 is connected to the TD- pin of the network port connection chip U6, the other end of the resistor R8 is connected to one end of the resistor R9, the other end of the resistor R9 is connected to the TD+ pin of the network port connection chip U6, one end of the capacitor C11 is connected between the resistor R8 and the resistor R9, the other end of the capacitor C11 is connected to one end of the capacitor C12 and grounded, the other end of the capacitor C12 is respectively connected to one end of the resistor R11 and one end of the resistor R10, the other end of the resistor R11 is connected to the RD+ pin of the network port connection chip U6, and the capacitor C11 is connected to the TD+ pin of the network port connection chip U6. The other end of the resistor R10 is connected to the RD-pin of the network port connection chip U6, the RCT pin and the TCT pin of the network port connection chip U6 are connected to one end of the capacitor C10 and are externally connected to a 3.3V voltage, the other end of the capacitor C10 is grounded, the LED(Y)_K pin of the network port connection chip U6 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the LED(G)_K pin of the network port connection chip U6, and the network port control circuit is connected between the resistor R12 and the resistor R13.

[0070] Among them, in the utility model, the network transformer chip is used as the network port connection chip U6, which increases the transmission distance and reduces power consumption.

[0071] In this embodiment, the DB9 plug J1 is mainly used to connect to the serial port of the external network host;

[0072] The serial port chip U4 is mainly used to convert the TTL level into 232 level. Its function here is that the external network host sends the serial port level command to the STM32 chip U1 (external network isolation circuit MCU) through the serial port chip U4.

[0073] The main function of the STM32 chip U1 is to control the opening and closing of the second optocoupler isolator U5 and the first optocoupler isolator U2, and at the same time send the received external host command to the Ethernet chip U3 through the SPI protocol. The STM32 chip U1 sets PA1 and PA2 to the default high level state through the GPIO pull-up mode setting, so that the second optocoupler isolator U5 and the first optocoupler isolator U2 are usually in the closed state;

[0074] The second optocoupler isolator U5 and the first optocoupler isolator U2 are used to pull down PA2 and PA1 from the default high level to a low level after receiving an instruction from the STM32 chip U1. At this time, the optocoupler switch is turned on, and SG1 and SG2 output 3.3V and 1.8V respectively. At this time, the Ethernet chip U3 controlled by the optocoupler isolator U5 and the optocoupler isolator U2 is in a power-on state. At this time, the STM32 chip U1 sends the serial port command (access external network command) sent by the external network host to the Ethernet chip U3 through the SPI communication protocol of the STM32 chip U1;

[0075] The network transformer chip U6 mainly functions as electrical isolation, impedance matching, and signal transmission. It is connected to the actual physical network port RJ45 and is the chip that connects to the actual external network.

[0076] The above description is only a preferred embodiment of the utility model and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the utility model is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the utility model (but not limited to) by each other to form a technical solution.

Claims

1. An external network isolation circuit, characterized in that: include: A level conversion circuit, a micro control unit, a first optocoupler isolation circuit, a second optocoupler isolation circuit, a network port control circuit and a network port connection circuit; One end of the level conversion circuit is connected to the serial port of the external network host, the other end of the level conversion circuit is connected to the level instruction input port of the micro control unit, the first level control port of the micro control unit is connected to the input end of the first optocoupler isolation circuit, the second level control port of the micro control unit is connected to the input end of the second optocoupler isolation circuit, the output end of the first optocoupler isolation circuit is connected to the first level receiving port of the network port control circuit, the output end of the second optocoupler isolation circuit is connected to the second level receiving port of the network port control circuit, the command output end of the micro control unit is connected to the command receiving end of the network port control circuit, the control end of the network port control circuit is connected to the controlled end of the network port connection circuit, and the network port connection end of the network port connection circuit is connected to the physical network interface.

2. The external network isolation circuit according to claim 1, characterized in that: The micro control unit includes an STM32 chip U1, and a clock signal input end of the STM32 chip U1 is connected to a first oscillation circuit.

3. An external network isolation circuit according to claim 2, characterized in that: The first oscillation circuit comprises: a capacitor C1, a capacitor C2, a resistor R1 and a crystal oscillator Y1; One end of the resistor R1 is connected to the OSC_IN pin of the STM32 chip U1, the other end of the R1 is connected to the OSC_OUT pin of the STM32 chip U1, the crystal oscillator Y1 is connected to the resistor R1 in parallel, one end of the capacitor C1 is connected to one end of the crystal oscillator Y1, one end of the capacitor C1 is connected to one end of the capacitor C2 and grounded, and the other end of the capacitor C2 is connected to the other end of the crystal oscillator Y1.

4. The external network isolation circuit according to claim 2, characterized in that: The level conversion circuit includes: a serial interface plug J1, a level conversion chip U4, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6 and a capacitor C7; The VCC pin of the level conversion chip U4 is externally connected to a 3.3V voltage, one end of the capacitor C3 is connected to the C1+ pin of the level conversion chip U4, and the other end of the capacitor C3 is connected to the C1- pin of the level conversion chip U4, one end of the capacitor C4, the capacitor C5 and the capacitor C6 are respectively connected to the VCC pin, the V+ pin and the V- pin of the level conversion chip U4, the other ends of the capacitors C4, C5 and C6 are all connected to the GND pin of the level conversion chip U4, and the GND pin is grounded, one end of the capacitor C7 is connected to the C2+ pin of the level conversion chip U4, and the other end of the capacitor C7 is connected to the C2- pin of the level conversion chip U4, the T1OUT pin and the R1 IN pin of the level conversion chip U4 are both connected to the serial interface plug J1, the T1 IN pin of the level conversion chip U4 is connected to the STX pin of the STM32 chip U1, and the R1OUT pin of the level conversion chip U4 is connected to the SRX pin of the STM32 chip U1.

5. The external network isolation circuit according to claim 4, characterized in that: The serial interface plug J1 is a DB9 plug, the T1OUT pin and the R1 IN pin of the level conversion chip U4 are connected to the No. 2 pin and the No. 3 pin of the DB9 plug respectively, and the No. 5 pin, the No. 10 pin and the No. 11 pin of the DB9 plug are grounded.

6. The external network isolation circuit according to claim 2, characterized in that: The first optical coupler isolation circuit includes: a resistor R2, a resistor R3 and a first optical coupler isolator U2; An input end of the first optocoupler isolator U2 is connected to one end of the resistor R2, the other end of the resistor R2 is externally connected to a 3.3V voltage, another input end of the first optocoupler isolator U2 is connected to the PA1 pin of the STM32 chip U1, an output end of the first optocoupler isolator U2 is grounded, another output end of the first optocoupler isolator U2 is connected to one end of the resistor R3 and to the network port control circuit, and the other end of the resistor R3 is externally connected to a 1.8V voltage.

7. The external network isolation circuit according to claim 6, characterized in that: The second optical coupler isolation circuit includes: a resistor R4, a resistor R5 and a second optical coupler isolator U5; An input end of the second optocoupler isolator U5 is connected to one end of the resistor R4, the other end of the resistor R4 is externally connected to a 3.3V voltage, another input end of the second optocoupler isolator U5 is connected to the PA2 pin of the STM32 chip U1, an output end of the second optocoupler isolator U5 is grounded, another output end of the second optocoupler isolator U5 is connected to one end of the resistor R5 and to the network port control circuit, and the other end of the resistor R5 is externally connected to a 3.3V voltage.

8. The external network isolation circuit according to claim 7, characterized in that: The network port control circuit includes: a network port control chip U3, a resistor R6, a resistor R7, a diode D1 and a second oscillation circuit; A first common connection port composed of multiple VCC33 pins of the network port control chip U3 is connected to an input end of the first optocoupler isolator U2, a second common connection port composed of multiple VCC18 pins of the network port control chip U3 is connected to an input end of the second optocoupler isolator U5, an RSETE pin of the network port control chip U3 is connected to one end of the resistor R6, and the other end of the resistor R6 is grounded, an RST1 pin of the network port control chip U3 is connected to the PA1 pin of the STM32 chip U1, and to one end of the resistor R7, and the other end of the resistor R7 is grounded, an INT# pin of the network port control chip U3 is connected to the cathode of the diode D1, an anode of the diode D1 is connected to the PA0 pin of the STM32 chip U1, and the network port control chip U3 is connected to the second oscillation circuit through the X1 pin and the X0 pin.

9. The external network isolation circuit according to claim 8, characterized in that: The second oscillator circuit includes: capacitor C8, capacitor C9 and crystal oscillator Y2; One end of the crystal oscillator Y2 is connected to the network port control chip U3 through the X1 pin, and is connected to one end of the capacitor C8, the other end of the capacitor C8 is connected to one end of the capacitor C9 and is grounded, the other end of the capacitor C9 is connected to the other end of the crystal oscillator Y2, and is connected to the network port control chip U3 through the X0 pin.

10. The external network isolation circuit according to claim 1, characterized in that: The network port connection circuit includes: a network port connection chip U6, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R12, a capacitor C10, a capacitor C11 and a capacitor C12; One end of the resistor R8 is connected to the TD- pin of the network port connection chip U6, the other end of the resistor R8 is connected to one end of the resistor R9, the other end of the resistor R9 is connected to the TD+ pin of the network port connection chip U6, one end of the capacitor C11 is connected between the resistor R8 and the resistor R9, the other end of the capacitor C11 is connected to one end of the capacitor C12 and grounded, the other end of the capacitor C12 is respectively connected to one end of the resistor R11 and one end of the resistor R10, the other end of the resistor R11 is connected to the RD+ pin of the network port connection chip U6, and the capacitor C11 is connected to the TD+ pin of the network port connection chip U6. The other end of the resistor R10 is connected to the RD-pin of the network port connection chip U6, the RCT pin and the TCT pin of the network port connection chip U6 are connected to one end of the capacitor C10 and are externally connected to a 3.3V voltage, the other end of the capacitor C10 is grounded, the LED(Y)_K pin of the network port connection chip U6 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the LED(G)_K pin of the network port connection chip U6, and the network port control circuit is connected between the resistor R12 and the resistor R13.

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