TOPCon battery piece capable of reducing back parasitic absorption and photovoltaic module

Abstract

The utility model provides a TOPCon cell sheet capable of reducing back parasitic absorption and a photovoltaic assembly, and relates to the technical field of solar cells. The TOPCon battery piece capable of reducing parasitic absorption on the back surface comprises an N-type crystalline silicon substrate, wherein a first tunneling oxide layer, an intrinsic polycrystalline silicon layer, a second tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a third tunneling oxide layer and a transparent conductive film sequentially cover the back surface of the N-type crystalline silicon substrate. The TOPCon battery piece comprises the N-type crystalline silicon substrate, so that on the basis of reducing the thickness of the Poly-Si composite layer on the back surface, parasitic absorption is reduced, the light utilization rate is increased, and composite current and contact resistance are reduced, so that the efficiency of the battery piece is effectively improved.

Description

Technical Field

[0001] The utility model relates to the technical field of solar cells, in particular to a TOPCon cell sheet and a photovoltaic module for reducing back side parasitic absorption. Background Art

[0002] At present, TOPCon solar cells (Tunnel Oxide Passivating Contacts) usually use N-type silicon wafers. The back structure usually uses a layer of silicon oxide as a tunneling layer on the back, and then covers it with a layer of N-type doped polysilicon layer (i.e., N+Poly-Si layer). The two together form a passivation contact structure, providing good surface passivation for the back of the silicon wafer. The above two characteristics jointly improve the open circuit voltage, fill factor and conversion efficiency of the battery.

[0003] Furthermore, a metal electrode layer is provided on the outermost layer of the back side of the N-type silicon wafer. Considering factors such as reducing ohmic contact resistance, it is easy to have poor contact performance between the front metal paste and silicon, and metal grains may penetrate the doped polysilicon film layer, destroying the passivation effect of the interface oxide layer, thereby affecting the efficiency of the battery. In the prior art, the thickness of the back Poly-Si layer is 110-130nm. The thickness of this Poly-Si layer is relatively thick, resulting in high parasitic absorption of light, resulting in the loss of short-circuit current of the TOPCon battery, low light utilization, and affecting the efficiency of the battery cell.

[0004] In view of this, the present utility model is proposed. Utility Model Content

[0005] The utility model aims to provide a TOPCon cell sheet for reducing back parasitic absorption and a photovoltaic module containing the same. The TOPCon cell sheet has the advantages of good passivation effect, less parasitic absorption, high light utilization rate, high conversion efficiency, etc.

[0006] In a first aspect, the utility model provides a TOPCon cell with reduced back parasitic absorption, wherein the TOPCon cell with reduced back parasitic absorption comprises an N-type crystalline silicon substrate;

[0007] The back side of the N-type crystalline silicon substrate is sequentially covered with a first tunneling oxide layer, an intrinsic polysilicon layer, a second tunneling oxide layer, a phosphorus-doped polysilicon layer, a third tunneling oxide layer, and a transparent conductive film.

[0008] In the utility model, the back side of the N-type crystalline silicon substrate of the TOPCon cell is composed of the above-mentioned specific laminated structure, which can not only ensure the blocking of the internal expansion of the phosphorus source and reduce the corrosion damage of the silver paste to the Poly-Si composite layer and the tunneling oxide layer, and reduce the composite current and contact resistance; but also reduce the thickness of the back Poly-Si composite layer, reduce parasitic absorption, increase light utilization, and improve the efficiency of the cell.

[0009] Furthermore, the thickness of the first tunnel oxide layer is 1-1.6 nm, for example, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, etc.

[0010] Furthermore, the thickness of the intrinsic polysilicon layer is 5 to 20 nm, for example, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, etc.

[0011] Furthermore, the thickness of the second tunnel oxide layer is 0.8-1.5 nm, for example, 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc.

[0012] Furthermore, the thickness of the phosphorus-doped polysilicon layer is 20 to 50 nm, for example, it may be 20 nm, 22 nm, 25 nm, 28 nm, 30 nm, 32 nm, 35 nm, 38 nm, 40 nm, 42 nm, 45 nm, 48 nm, 50 nm, etc.

[0013] Furthermore, in the phosphorus-doped polysilicon layer, the phosphorus doping concentration is 1×10 19 ~1×10 21 cm -3 , for example, it can be 1×10 19 cm -3 , 2×10 19 cm -3 , 5×10 19 cm -3 , 8×10 19 cm -3 , 1×10 20 cm -3 , 2×10 20 cm -3 , 5×10 20 cm -3 , 8×10 20 cm -3 , 1×10 21 cm -3 wait.

[0014] Furthermore, the thickness of the third tunnel oxide layer is 0.8-1.5 nm, for example, 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc.

[0015] Furthermore, the first tunneling oxide layer, the second tunneling oxide layer, and the third tunneling oxide layer are silicon oxide layers.

[0016] Furthermore, the thickness of the transparent conductive film is 15 to 70 nm, for example, it can be 15 nm, 16 nm, 18 nm, 20 nm, 22 nm, 24 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, etc.

[0017] Furthermore, the transparent conductive film is selected from any one of an indium tin oxide (ITO) film, an aluminum zinc oxide (AZO) film or an indium zinc oxide (IZO) film, or a combination of at least two thereof.

[0018] Furthermore, a back silicon nitride layer is also provided on the transparent conductive film.

[0019] Furthermore, the thickness of the silicon nitride layer is 20-40 μm, for example, 20 μm, 22 μm, 24 μm, 26 μm, 28 μm, 30 μm, 32 μm, 34 μm, 36 μm, 38 μm, 40 μm, etc.

[0020] Furthermore, an N-region electrode is also provided on the back side of the N-type crystalline silicon substrate.

[0021] Furthermore, the front surface of the N-type crystalline silicon substrate has a pyramid velvet structure.

[0022] Furthermore, the height of the pyramid velvet surface is 2 to 8 μm, for example, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, etc.

[0023] Furthermore, the front side of the N-type crystalline silicon substrate is sequentially covered with a B emitter, a front side aluminum oxide layer and a front side silicon nitride layer.

[0024] Furthermore, the thickness of the front aluminum oxide layer is 1 to 10 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0025] Furthermore, the thickness of the front silicon nitride layer is 20-40 μm, for example, 20 μm, 22 μm, 24 μm, 26 μm, 28 μm, 30 μm, 32 μm, 34 μm, 36 μm, 38 μm, 40 μm, etc.

[0026] In a second aspect, the utility model provides a photovoltaic module, wherein the photovoltaic module comprises a TOPCon cell sheet for reducing back side parasitic absorption as described in the first aspect.

[0027] Compared with the prior art, the utility model has the following beneficial effects:

[0028] (1) The back side of the N-type crystalline silicon substrate of the TOPCon cell of the utility model is composed of the above-mentioned specific laminated structure, which can ensure the prevention of phosphorus source expansion and reduce the corrosion damage of silver paste to the Poly-Si composite layer and the tunneling oxide layer, thereby reducing the composite current and contact resistance;

[0029] (2) The back side of the N-type crystalline silicon substrate of the TOPCon cell of the present invention is composed of the above-mentioned specific laminated structure, which can reduce the thickness of the back Poly-Si composite layer, reduce parasitic absorption, increase light utilization, and improve cell efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 This is a schematic diagram of the structure of a TOPCon cell for reducing back-side parasitic absorption provided by the utility model.

[0032] Among them, 1 is an N-type crystalline silicon substrate, 2 is a first tunneling oxide layer, 3 is an intrinsic polysilicon layer, 4 is a second tunneling oxide layer, 5 is a phosphorus-doped polysilicon layer, 6 is a third tunneling oxide layer, 7 is a transparent conductive film, 8 is a back silicon nitride layer, 9 is an N region electrode, 10 is a B emitter, 11 is a front aluminum oxide layer, and 12 is a front silicon nitride layer. DETAILED DESCRIPTION

[0033] Unless otherwise defined herein, scientific and technical terms used in conjunction with the present invention shall have the meanings commonly understood by those of ordinary skill in the art. The meaning and scope of the terms should be clear, however, in the case of any potential ambiguity, the definitions provided herein take precedence over any dictionary or external definitions. In this application, unless otherwise stated, the use of "or" means "and / or". In addition, the use of the term "including" and other forms is non-limiting.

[0034] It should be noted that the following description sets forth specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0035] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0036] The technical solution of the utility model will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0037] like Figure 1 As shown, the utility model provides a TOPCon cell sheet for reducing back side parasitic absorption, and the TOPCon cell sheet includes an N-type crystalline silicon substrate 1;

[0038] The back side of the N-type crystalline silicon substrate 1 is sequentially covered with a first tunneling oxide layer 2, an intrinsic polysilicon layer 3, a second tunneling oxide layer 4, a phosphorus-doped polysilicon layer 5, a third tunneling oxide layer 6, a transparent conductive film 7, and a back side silicon nitride layer 8; and an N-region electrode 9 is also provided on the back side of the N-type crystalline silicon substrate 1;

[0039] The front side of the N-type crystalline silicon substrate 1 has a pyramid velvet structure, and the front side of the N-type crystalline silicon substrate 1 is sequentially covered with a B emitter 10 , a front aluminum oxide layer 11 and a front silicon nitride layer 12 .

[0040] Example 1

[0041] This embodiment provides a TOPCon cell for reducing back-side parasitic absorption, wherein the TOPCon cell comprises an N-type crystalline silicon substrate 1;

[0042] The back side of the N-type crystalline silicon substrate 1 is sequentially covered with a first tunneling oxide layer 2, an intrinsic polysilicon layer 3, a second tunneling oxide layer 4, a phosphorus-doped polysilicon layer 5, a third tunneling oxide layer 6, a transparent conductive film 7, and a back side silicon nitride layer 8; and an N-region electrode 9 is also provided on the back side of the N-type crystalline silicon substrate 1;

[0043] The thickness of the first tunnel oxide layer 2 is 1.1 nm; the thickness of the intrinsic polysilicon layer 3 is 6 nm; the thickness of the second tunnel oxide layer 4 is 0.9 nm; the thickness of the phosphorus-doped polysilicon layer 5 is 45 nm, and the phosphorus doping concentration is 1×10 19 cm -3 ; The thickness of the third tunneling oxide layer 6 is 1.4 nm; the transparent conductive film 7 is an indium tin oxide transparent conductive film with a thickness of 20 nm; the thickness of the back silicon nitride layer 8 is 32 μm; the N-region electrode 9 is a silver electrode;

[0044] The front side of the N-type crystalline silicon substrate 1 has a pyramid velvet structure, and the front side of the N-type crystalline silicon substrate 1 is sequentially covered with a B emitter 10, a front aluminum oxide layer 11 and a front silicon nitride layer 12;

[0045] Wherein, the height of the pyramid velvet surface is 2 μm; the thickness of the front aluminum oxide layer is 3 μm; and the thickness of the front silicon nitride layer is 32 μm.

[0046] Example 2

[0047] This embodiment provides a TOPCon cell for reducing back-side parasitic absorption, wherein the TOPCon cell comprises an N-type crystalline silicon substrate 1;

[0048] The back side of the N-type crystalline silicon substrate 1 is sequentially covered with a first tunneling oxide layer 2, an intrinsic polysilicon layer 3, a second tunneling oxide layer 4, a phosphorus-doped polysilicon layer 5, a third tunneling oxide layer 6, a transparent conductive film 7, and a back side silicon nitride layer 8; and an N-region electrode 9 is also provided on the back side of the N-type crystalline silicon substrate 1;

[0049] The thickness of the first tunnel oxide layer 2 is 1.4 nm; the thickness of the intrinsic polysilicon layer 3 is 12 nm; the thickness of the second tunnel oxide layer 4 is 1.4 nm; the thickness of the phosphorus-doped polysilicon layer 5 is 38 nm, and the phosphorus doping concentration is 1×10 20 cm -3; The thickness of the third tunneling oxide layer 6 is 1.2 nm; the transparent conductive film 7 is an aluminum zinc oxide transparent conductive film with a thickness of 36 nm; the thickness of the back silicon nitride layer 8 is 34 μm; the N region electrode 9 is a silver electrode;

[0050] The front side of the N-type crystalline silicon substrate 1 has a pyramid velvet structure, and the front side of the N-type crystalline silicon substrate 1 is sequentially covered with a B emitter 10, a front aluminum oxide layer 11 and a front silicon nitride layer 12;

[0051] Wherein, the height of the pyramid velvet surface is 5 μm; the thickness of the front aluminum oxide layer is 3 μm; and the thickness of the front silicon nitride layer is 36 μm.

[0052] Example 3

[0053] This embodiment provides a TOPCon cell for reducing back-side parasitic absorption, wherein the TOPCon cell comprises an N-type crystalline silicon substrate 1;

[0054] The back side of the N-type crystalline silicon substrate 1 is sequentially covered with a first tunneling oxide layer 2, an intrinsic polysilicon layer 3, a second tunneling oxide layer 4, a phosphorus-doped polysilicon layer 5, a third tunneling oxide layer 6, a transparent conductive film 7, and a back side silicon nitride layer 8; and an N-region electrode 9 is also provided on the back side of the N-type crystalline silicon substrate 1;

[0055] The thickness of the first tunnel oxide layer 2 is 1.5 nm; the thickness of the intrinsic polysilicon layer 3 is 18 nm; the thickness of the second tunnel oxide layer 4 is 1.4 nm; the thickness of the phosphorus-doped polysilicon layer 5 is 25 nm, and the phosphorus doping concentration is 1×10 21 cm -3 ; The thickness of the third tunneling oxide layer 6 is 0.9 nm; the transparent conductive film 7 is an indium zinc oxide transparent conductive film with a thickness of 55 nm; the thickness of the back silicon nitride layer 8 is 38 μm; the N-region electrode 9 is a silver electrode;

[0056] The front side of the N-type crystalline silicon substrate 1 has a pyramid velvet structure, and the front side of the N-type crystalline silicon substrate 1 is sequentially covered with a B emitter 10, a front aluminum oxide layer 11 and a front silicon nitride layer 12;

[0057] Wherein, the height of the pyramid velvet surface is 1 μm; the thickness of the front aluminum oxide layer is 4 μm; and the thickness of the front silicon nitride layer is 38 μm.

[0058] Comparative Example 1

[0059] This comparative example provides a TOPCon cell, wherein the TOPCon cell comprises an N-type crystalline silicon substrate;

[0060] The back side of the N-type crystalline silicon substrate is sequentially covered with a tunneling oxide layer, a phosphorus-doped polysilicon layer, a transparent conductive film, and a back side silicon nitride layer; and an N-region electrode is also provided on the back side of the N-type crystalline silicon substrate;

[0061] The thickness of the tunnel oxide layer is 3.8 nm; the thickness of the phosphorus-doped polysilicon layer is 120 nm, and the phosphorus doping concentration is 1×10 21 cm -3 ; The transparent conductive film is an indium zinc oxide transparent conductive film with a thickness of 55nm; the thickness of the back silicon nitride layer is 38μm; the N-region electrode is a silver electrode;

[0062] The front side of the N-type crystalline silicon substrate 1 has a pyramid velvet structure, and the front side of the N-type crystalline silicon substrate 1 is sequentially covered with a B emitter 10, a front aluminum oxide layer 11 and a front silicon nitride layer 12;

[0063] Wherein, the height of the pyramid velvet surface is 1 μm; the thickness of the front aluminum oxide layer is 4 μm; and the thickness of the front silicon nitride layer is 38 μm.

[0064] Comparative Example 2

[0065] This comparative example provides a TOPCon cell, wherein the TOPCon cell comprises an N-type crystalline silicon substrate;

[0066] The back side of the N-type crystalline silicon substrate is sequentially covered with a first tunneling oxide layer, a phosphorus-doped polysilicon layer 5, a second tunneling oxide layer, a transparent conductive film, and a back side silicon nitride layer; and an N-region electrode is also provided on the back side of the N-type crystalline silicon substrate;

[0067] The thickness of the first tunnel oxide layer is 1.1 nm; the thickness of the phosphorus-doped polysilicon layer is 51 nm, and the phosphorus doping concentration is 1×10 19 cm -3 ; The thickness of the second tunneling oxide layer is 2.3 nm; the transparent conductive film is an indium tin oxide transparent conductive film with a thickness of 20 nm; the thickness of the back silicon nitride layer is 32 μm; the N-region electrode is a silver electrode;

[0068] The front side of the N-type crystalline silicon substrate has a pyramid velvet structure, and the front side of the N-type crystalline silicon substrate is sequentially covered with a B emitter, a front aluminum oxide layer, and a front silicon nitride layer;

[0069] Wherein, the height of the pyramid velvet surface is 2 μm; the thickness of the front aluminum oxide layer is 3 μm; and the thickness of the front silicon nitride layer is 32 μm.

[0070] Comparative Example 3

[0071] This comparative example provides a TOPCon cell, wherein the TOPCon cell comprises an N-type crystalline silicon substrate;

[0072] The back side of the N-type crystalline silicon substrate is sequentially covered with a first tunneling oxide layer, an intrinsic polysilicon layer, a second tunneling oxide layer, a transparent conductive film, and a back side silicon nitride layer; and an N-region electrode is also provided on the back side of the N-type crystalline silicon substrate;

[0073] The thickness of the first tunnel oxide layer is 1.4 nm; the thickness of the intrinsic polysilicon layer 3 is 50 nm; the thickness of the second tunnel oxide layer is 2.6 nm; the transparent conductive film is an aluminum zinc oxide transparent conductive film with a thickness of 36 nm; the thickness of the back silicon nitride layer is 34 μm; the N region electrode is a silver electrode;

[0074] The front side of the N-type crystalline silicon substrate has a pyramid velvet structure, and the front side of the N-type crystalline silicon substrate is sequentially covered with a B emitter, a front aluminum oxide layer, and a front silicon nitride layer;

[0075] Wherein, the height of the pyramid velvet surface is 5 μm; the thickness of the front aluminum oxide layer is 3 μm; and the thickness of the front silicon nitride layer is 36 μm.

[0076] Comparative Example 4

[0077] This comparative example provides a TOPCon cell, which is different from Example 1 only in that the transparent conductive film is not provided, and the other layers are arranged in the same manner as in Example 1.

[0078] Test Case

[0079] Test samples: TOPCon cells for reducing back-side parasitic absorption provided in Examples 1 to 3, and TOPCon cells provided in Comparative Examples 1 to 4;

[0080] Test method: Use solar energy simulation electric efficiency tester to test the electrical performance under standard conditions (air quality AM1.5, light intensity 1000W / m 2 , test temperature 25℃);

[0081] The test results are shown in Table 1 below:

[0082] Table 1

[0083]

[0084] As shown in Table 1, the back side of the N-type crystalline silicon substrate of the TOPCon cell with reduced back side parasitic absorption described in the utility model is composed of the above-mentioned specific laminated structure, which can not only ensure the blocking of the internal expansion of the phosphorus source and reduce the corrosion damage of the silver paste to the Poly-Si composite layer and the tunneling oxide layer, and reduce the composite current and contact resistance; but also reduce the thickness of the back side Poly-Si composite layer, reduce parasitic absorption, increase light utilization, and improve the efficiency of the cell.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A TOPCon cell with reduced backside parasitic absorption, characterized in that: The TOPCon cell for reducing back parasitic absorption comprises an N-type crystalline silicon substrate; The back side of the N-type crystalline silicon substrate is sequentially covered with a first tunneling oxide layer, an intrinsic polysilicon layer, a second tunneling oxide layer, a phosphorus-doped polysilicon layer, a third tunneling oxide layer, and a transparent conductive film.

2. The TOPCon cell with reduced backside parasitic absorption according to claim 1, characterized in that: The thickness of the first tunnel oxide layer is 1-1.6 nm.

3. The TOPCon cell with reduced backside parasitic absorption according to claim 1, characterized in that: The thickness of the intrinsic polysilicon layer is 5 to 20 nm; And / or, the thickness of the second tunneling oxide layer is 0.8-1.5 nm.

4. The TOPCon cell with reduced backside parasitic absorption according to claim 1, characterized in that: The thickness of the phosphorus-doped polysilicon layer is 20 to 50 nm; And / or, the thickness of the third tunnel oxide layer is 0.8-1.5 nm.

5. The TOPCon cell with reduced backside parasitic absorption according to claim 1, characterized in that: The thickness of the transparent conductive film is 15 to 70 nm; Wherein, the transparent conductive film is selected from any one of indium tin oxide film, aluminum zinc oxide film or indium zinc oxide film, or a combination of at least two thereof.

6. The TOPCon cell with reduced backside parasitic absorption according to claim 1 or 5, characterized in that: A back silicon nitride layer is also provided on the transparent conductive film; Wherein, the thickness of the silicon nitride layer is 20 to 40 μm; And / or, an N-region electrode is also provided on the back side of the N-type crystalline silicon substrate.

7. The TOPCon cell with reduced backside parasitic absorption according to claim 1, characterized in that: The front side of the N-type crystalline silicon substrate has a pyramid velvet structure; Wherein, the height of the pyramid velvet surface is 2 to 8 μm.

8. The TOPCon cell with reduced backside parasitic absorption according to claim 1 or 7, characterized in that: The front side of the N-type crystalline silicon substrate is sequentially covered with a B emitter, a front side aluminum oxide layer and a front side silicon nitride layer.

9. The TOPCon cell with reduced backside parasitic absorption according to claim 8, characterized in that: The thickness of the front aluminum oxide layer is 1 to 10 μm; And / or, the thickness of the front silicon nitride layer is 20-40 μm.

10. A photovoltaic module, characterized in that: The photovoltaic module comprises the TOPCon cell sheet for reducing back side parasitic absorption according to any one of claims 1 to 9.

Images