High-speed signal processing circuit board layout structure and high-speed signal processing circuit board

Abstract

The utility model relates to the technical field of high-frequency signal processing, in particular to a high-speed signal processing circuit board layout structure and a signal processing board. The Fr-4 board is provided with a micro-control device area, a digital signal processing area, a programmable logic area, a signal input and output device area and an analog-to-digital conversion and digital-to-analog conversion device area. The signal input and output device area comprises a 10 g optical port placing area and a 40 g optical port placing area, the 10 g optical port placing area is located on the upper right portion of the programmable logic area, and the 40 g optical port placing area is located on the upper left portion of the programmable logic area. According to the utility model, the layout of related devices is designed according to the interconnection relationship of high-speed signals, and the layout structure can ensure that the transmission loss of a 10g signal line is less than 1.2 dB under a common Fr-4 board, so that the data transmission in the board and between the boards at the rate of 10g can be realized.

Description

Technical Field

[0001] The utility model relates to the technical field of high-frequency signal processing, in particular to a high-speed signal processing circuit board layout structure and a signal processing board. Background Art

[0002] High-frequency signals are common processed signals in the field of signal processing. The common circuit boards that process them use AD processing circuits to sample them, convert the high-frequency signals into digital signals, and then process them through the FPGA's signal processing circuits and the main control circuit's digital algorithms before sending the digital signals through the network interface.

[0003] In the prior art, for circuit boards with digital signal processing units with a transmission rate greater than 10g, high-speed board design is mostly used, which results in high cost. Therefore, there is an urgent need for a layout structure that can achieve 10g intra-board and inter-board data transmission using ordinary Fr-4 boards. Utility Model Content

[0004] The purpose of the utility model is to provide a high-speed signal processing circuit board layout structure and a signal processing board. According to the high-speed signal interconnection relationship, the layout of related devices is designed. The layout structure can ensure that the transmission loss of the signal line under the ordinary Fr-4 board is small, thereby realizing 10g rate intra-board and inter-board data transmission.

[0005] The embodiment of the utility model is realized by the following technical scheme: a high-speed signal processing circuit board layout structure, the high-speed signal processing circuit board adopts Fr-4 plate, and the Fr-4 plate is provided with a microcontroller device area, a digital signal processing area, a programmable logic area, a signal input and output device area, and an analog-to-digital conversion and a digital-to-analog conversion device area;

[0006] The signal input and output device area includes a 10g optical port placement area and a 40g optical port placement area. The 10g optical port placement area is located at the upper right of the programmable logic area, and the 40g optical port placement area is located at the upper left of the programmable logic area.

[0007] According to a preferred embodiment, the analog-to-digital conversion and digital-to-analog conversion device area is located above the programmable logic area and at the lower right of the 40g optical port placement area and at the lower left of the 10g optical port placement area, the microcontroller device area is located on the right side of the programmable logic area and at the lower left of the 10g optical port placement area, and the digital signal processing area is located at the lower left of the 10g optical port placement area and above the microcontroller device area.

[0008] According to a preferred embodiment, the 40g optical port placement area includes a first 40g optical port placement area and a second 40g optical port placement area.

[0009] According to a preferred embodiment, the programmable logic area includes a first FPGA placement area and a second FPGA placement area.

[0010] According to a preferred implementation, a first gold finger area is provided below the programmable logic area, and a second gold finger area is provided below the microcontroller area.

[0011] The utility model also provides a high-speed signal processing circuit board, comprising a PCB board and the high-speed signal processing circuit board layout structure as described above.

[0012] According to a preferred embodiment, the 10g optical port placement area is provided with a 10g optical port, the first 40g optical port placement area is provided with a first 40g optical port, the second 40g optical port placement area is provided with a second 40g optical port, the first FPGA placement area is provided with a first FPGA, the second FPGA placement area is provided with a second FPGA, the first gold finger area is provided with a first inter-board connector and a second inter-board connector, the second gold finger area is provided with a third inter-board connector, the microcontroller area is provided with a microprocessor, the digital signal processing area is provided with a DSP chip, and the analog-to-digital conversion and digital-to-analog conversion device area is provided with a high-speed AD / DA card;

[0013] The first 40g optical port is connected to the first end of the first FPGA, the second 40g optical port is connected to the second end of the first FPGA, the first end of the DSP chip is connected to the third end of the first FPGA, the fourth end of the first FPGA is connected to the first end of the second FPGA, the fifth end of the first FPGA is connected to the first end of the microprocessor, the sixth end of the first FPGA is connected to the first inter-board connector, the second end of the second FPGA is connected to the high-speed AD / DA card, the third end of the second FPGA is connected to the second end of the DSP chip, the fourth end of the second FPGA is connected to the second end of the microprocessor, the fifth end of the second FPGA is connected to the second inter-board connector, the 10g optical port is connected to the third end of the microprocessor, and the fourth end of the microprocessor is connected to the third inter-board connector.

[0014] According to a preferred implementation, the DSP chip is a TMS320C6678 chip.

[0015] According to a preferred implementation, the FPGA uses an XC7VX690T chip.

[0016] According to a preferred embodiment, the microprocessor adopts an XC7Z045 chip.

[0017] A high-speed signal processing circuit board layout structure and a technical solution for a signal processing board provided by an embodiment of the utility model have at least the following advantages and beneficial effects: the utility model designs the layout of related devices according to the high-speed signal interconnection relationship, and the layout structure can ensure that the transmission loss of the 10g signal line under the ordinary Fr-4 board is less than 1.2dB, thereby realizing 10g rate intra-board and inter-board data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the layout structure of a high-speed signal processing circuit board provided in Example 1 of the utility model;

[0019] Figure 2 A circuit schematic diagram of a high-speed signal processing circuit board provided in Example 1 of the utility model;

[0020] Icons: 1-microcontroller device area, 2-digital signal processing area, 3-first FPGA placement area, 4-second FPGA placement area, 5-10g optical port placement area, 6-first 40g optical port placement area, 7-second 40g optical port placement area, 8-analog-to-digital conversion and digital-to-analog conversion device area, 9-first gold finger area, 10-second gold finger area. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0022] Example 1

[0023] See also Figure 1 As shown, the embodiment of the utility model provides a high-speed signal processing circuit board layout structure. More specifically, different from the high-speed board required for 10g rate intra-board and inter-board data transmission, in this embodiment, the high-speed signal processing circuit board adopts ordinary Fr-4 board, and the layout of the Fr-4 board is designed according to the high-speed signal interconnection relationship, so that the Fr-4 board can also realize 10g rate intra-board and inter-board data transmission. The specific layout structure is as follows:

[0024] The top layer of the Fr-4 board is provided with a microcontroller device area 1, a digital signal processing area 2, a programmable logic area, a signal input / output device area, and an analog-to-digital conversion and digital-to-analog conversion device area 8; further, the signal input / output device area includes a 10g optical port placement area 5 and a 40g optical port placement area, the 10g optical port placement area 5 is located at the upper right of the programmable logic area, and the 40g optical port placement area is located at the upper left of the programmable logic area; through the above layout design, suitable components are selected for each area, and the components selected in this embodiment are finally tested to obtain a transmission loss of the 10g signal line of less than 1.2dB, which will be described in detail later, and 10g rate intra-board and inter-board data transmission can be achieved.

[0025] Furthermore, the overall layout of each component is as follows:

[0026] The analog-to-digital conversion and digital-to-analog conversion device area 8 is located above the programmable logic area and at the lower right of the 40g optical port placement area and at the lower left of the 10g optical port placement area 5. The microcontroller device area 1 is located on the right side of the programmable logic area and at the lower left of the 10g optical port placement area 5. The digital signal processing area 2 is located at the lower left of the 10g optical port placement area 5 and above the microcontroller device area 1.

[0027] In addition, in this embodiment, the 40g optical port placement area includes a first 40g optical port placement area 6 and a second 40g optical port placement area 7; the programmable logic area includes a first FPGA placement area 3 and a second FPGA placement area 4; a first gold finger area 9 is provided below the programmable logic area, and a second gold finger area 10 is provided below the microcontroller device area 1.

[0028] See also Figure 2 As shown, this embodiment also provides a high-speed signal processing circuit board, which is based on the layout structure provided above and also uses Fr-4 board material.

[0029] Further specifically, in this embodiment, the 10g optical port placement area 5 is provided with a 10g optical port; the first 40g optical port placement area 6 is provided with a first 40g optical port, and the second 40g optical port placement area 7 is provided with a second 40g optical port; the first FPGA placement area 3 is provided with a first FPGA, and the second FPGA placement area 4 is provided with a second FPGA, and both the first FPGA and the second FPGA here use XC7VX690T chips; the first gold finger area 9 is provided with a first inter-board connector and a second inter-board connector, and the second gold finger area 10 is provided with a third inter-board connector; the microcontroller device area 1 is provided with a microprocessor, and the microprocessor here uses an XC7Z045 chip; the digital signal processing area 2 is provided with a DSP chip, and the DSP chip here uses a TMS320C6678 chip; the analog-to-digital conversion and digital-to-analog conversion device area 8 is provided with a high-speed AD / DA card.

[0030] The first 40g optical port is connected to the first end of the first FPGA, where the signal name is 40GBASE-R1, the transmitted signal type is Aurora_64b66b, the signal specification is X4, and the signal design line rate is 11g; the second 40g optical port is connected to the second end of the first FPGA, where the signal name is 40G BASE-R2, the transmitted signal type is Aurora_64b66b, the signal specification is X4, and the signal design line rate is 11g; the first end of the DSP chip is connected to the third end of the first FPGA, where the signal name is Srio, the transmitted signal type is srio_gen2, the signal specification is X1, and the signal design line rate is 6.25g; the fourth end of the first FPGA is connected to the first end of the second FPGA, where the signal name is Aurora2, the transmitted signal type is Aurora_64b66b, the signal specification is X4, and the signal design line rate is 11g; the fifth end of the first FPGA is connected to the first end of the microprocessor, where the signal name is Aurora, the transmitted signal type is Aurora_64b66b, the signal specification is X4, and the signal design line rate is 11g; the sixth end of the first FPGA is connected to the first inter-board connector, and the Aurora protocol is used for inter-board interconnection. The transmitted signal type is Aurora_64b66b, and the signal specification is X 4, the signal design line rate is 11g; the second end of the second FPGA is connected to the high-speed AD / DA card, the signal name is JESD204B, the transmitted signal type is jesd204_phy, the signal specification is X8, and the signal design line rate is 10g; the third end of the second FPGA is connected to the second end of the DSP chip, where the signal name is Srio, the transmitted signal type is srio_gen2, the signal specification is X1, and the signal design line rate is 6.25g; the fourth end of the second FPGA is connected to the second end of the microprocessor, where the signal name is Aurora1, the transmitted signal type is Aurora_64b66b, the signal specification is X2, and the signal design line rate is 11g; the fifth end of the second FPGA is connected to the second inter-board connector, and the Aurora protocol is used for inter-board interconnection. The transmitted signal type is Aurora_64b66b, the signal specification is X4, and the signal design line rate is 11g; the 10g optical port is connected to the third end of the microprocessor, and the signal name is 10G BASE-R, the transmitted signal type is 10geth_pes_pma, the signal specification is X1, and the signal design line rate is 10g; the fourth end of the microprocessor is connected to the third inter-board connector, and the PCIe2.0 protocol is used for inter-board interconnection, the signal specification is X4, and the signal design line rate is 5g.

[0031] When the line width is 4mil, the loss of 10g differential 100 ohm impedance signal transmission on Fr-4 board is about 1.15dB / inch, that is, 9.58e-5 / mil; and according to the 10g line rate calculation, the line loss of each signal is shown in Table 1 below:

[0032] Table 1. Line loss of each signal at 10g line rate

[0033]

[0034] From the above, we can see that only the Srio loss between TMS320C6678 and XC7VX690T is greater than 0.5dB (0.526dB), and the actual Srio maximum line rate is 6.25g, so it can meet the design requirements of 10g rate intra-board and inter-board data transmission.

[0035] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may be subject to various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A high-speed signal processing circuit board layout structure, characterized in that: The high-speed signal processing circuit board adopts Fr-4 plate, and the Fr-4 plate is provided with a microcontroller device area (1), a digital signal processing area (2), a programmable logic area, a signal input and output device area, and an analog-to-digital conversion and digital-to-analog conversion device area (8); The signal input and output device area comprises a 10g optical port placement area (5) and a 40g optical port placement area, wherein the 10g optical port placement area (5) is located at the upper right of the programmable logic area, and the 40g optical port placement area is located at the upper left of the programmable logic area.

2. The high-speed signal processing circuit board layout structure according to claim 1, characterized in that: The analog-to-digital conversion and digital-to-analog conversion device area (8) is located above the programmable logic area and is located at the lower right of the 40g optical port placement area and the lower left of the 10g optical port placement area (5); the microcontroller device area (1) is located at the right of the programmable logic area and is located at the lower left of the 10g optical port placement area (5); and the digital signal processing area (2) is located at the lower left of the 10g optical port placement area (5) and is located above the microcontroller device area (1).

3. The high-speed signal processing circuit board layout structure as claimed in claim 2, characterized in that: The 40g optical port placement area includes a first 40g optical port placement area (6) and a second 40g optical port placement area (7).

4. The high-speed signal processing circuit board layout structure as claimed in claim 3, characterized in that: The programmable logic area comprises a first FPGA placement area (3) and a second FPGA placement area (4).

5. The high-speed signal processing circuit board layout structure as claimed in claim 4, characterized in that: A first gold finger area (9) is provided below the programmable logic area, and a second gold finger area (10) is provided below the microcontroller area (1).

6. A high-speed signal processing circuit board, characterized in that: It comprises a PCB board and the high-speed signal processing circuit board layout structure as claimed in claim 5.

7. The high-speed signal processing circuit board according to claim 6, characterized in that: The 10g optical port placement area (5) is provided with a 10g optical port, the first 40g optical port placement area (6) is provided with a first 40g optical port, the second 40g optical port placement area (7) is provided with a second 40g optical port, the first FPGA placement area (3) is provided with a first FPGA, the second FPGA placement area (4) is provided with a second FPGA, the first gold finger area (9) is provided with a first inter-board connector and a second inter-board connector, the second gold finger area (10) is provided with a third inter-board connector, the microcontroller area (1) is provided with a microprocessor, the digital signal processing area (2) is provided with a DSP chip, and the analog-to-digital conversion and digital-to-analog conversion device area (8) is provided with a high-speed AD / DA card; The first 40g optical port is connected to the first end of the first FPGA, the second 40g optical port is connected to the second end of the first FPGA, the first end of the DSP chip is connected to the third end of the first FPGA, the fourth end of the first FPGA is connected to the first end of the second FPGA, the fifth end of the first FPGA is connected to the first end of the microprocessor, the sixth end of the first FPGA is connected to the first inter-board connector, the second end of the second FPGA is connected to the high-speed AD / DA card, the third end of the second FPGA is connected to the second end of the DSP chip, the fourth end of the second FPGA is connected to the second end of the microprocessor, the fifth end of the second FPGA is connected to the second inter-board connector, the 10g optical port is connected to the third end of the microprocessor, and the fourth end of the microprocessor is connected to the third inter-board connector.

8. The high-speed signal processing circuit board according to claim 7, characterized in that: The DSP chip adopts TMS320C6678 chip.

9. The high-speed signal processing circuit board according to claim 7, characterized in that: The FPGA adopts XC7VX690T chip.

10. The high-speed signal processing circuit board according to claim 7, characterized in that: The microprocessor adopts XC7Z045 chip.

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