Deposition mask and display device manufactured using the same

Abstract

A deposition mask, a method for manufacturing the same, and a display device manufactured using the same are provided. A deposition mask includes: a mask substrate including an opening; and a mask pattern disposed on the mask substrate and including a plurality of hole patterns spaced apart from each other, in which the mask pattern further includes: a first portion on the mask substrate; and a second portion protruding from the first portion in a direction opposite to the mask substrate, the second portion including: a first protruding portion and a second protruding portion disposed adjacent to the plurality of hole patterns; and a recessed portion disposed between the first protruding portion and the second protruding portion, and a height of the recessed portion is smaller than a height of the first protruding portion and the second protruding portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority and all rights arising from Korean Patent Application No. 10-2023-0069718 filed in the Korean Intellectual Property Office on May 31, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a deposition mask, a method for manufacturing the same, and a display device manufactured using the same. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. The display device may be a flat panel display such as a liquid crystal display, a field emission display, or a light-emitting display panel. The light-emitting display device may include an organic light-emitting diode display device including an organic light-emitting diode element as a light-emitting element or an inorganic light-emitting diode display device including an inorganic light-emitting diode element such as a light-emitting diode (LED) as a light-emitting element.

[0005] In a self-luminous display device such as an organic light-emitting display device, as a technology for depositing an organic material for each pixel, a fine metal mask (FMM) method is mainly used, in which a thin metal mask is brought into close contact with a substrate to deposit the organic material at a desired position.

[0006] On the other hand, in manufacturing thin plates such as FMM masks, research on the electroforming method is being actively conducted. The electroforming method is a method for immersing an anode body or a cathode body in an electrolyte and applying electricity to electrodeposit a metal sheet on the surface of the anode body or the cathode body. Since the electroforming method is a method for directly electrodepositing metal ions, the electroforming method can manufacture very thin sheets and has advantages in mass production. Utility Model Content

[0007] Aspects of the present disclosure provide a deposition mask having a pattern width with high uniformity and a method for manufacturing the same.

[0008] Aspects of the present disclosure also provide a deposition mask for an ultra-high resolution display, a method for manufacturing the same, and a display device manufactured using the same.

[0009] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0010] According to aspects of the present disclosure, a deposition mask is provided, comprising: a mask substrate comprising an opening; and a mask pattern, disposed on the mask substrate and comprising a plurality of hole patterns spaced apart from each other, wherein the mask pattern further comprises: a first portion, on the mask substrate; and a second portion, protruding from the first portion in a direction opposite to the mask substrate, the second portion comprising: a first protruding portion and a second protruding portion, disposed adjacent to the plurality of hole patterns; and a recessed portion, disposed between the first protruding portion and the second protruding portion, and a height of the recessed portion being less than a height of the first protruding portion and the second protruding portion.

[0011] In an embodiment, the first portion has an inverted tapered shape.

[0012] In an embodiment, the first portion includes: a first surface positioned close to the mask substrate; a second surface positioned on an opposite side of the first surface; and a first side surface disposed between the first surface and the second surface, and a width of the first surface is smaller than a width of the second surface.

[0013] In an embodiment, the first side surface is an inclined surface inclined from the second surface toward the first surface toward the inner side of the first portion. Each of the plurality of hole patterns has a forward tapered shape.

[0014] In an embodiment, an upper width of each of the plurality of hole patterns is narrower than a lower width.

[0015] In an embodiment, a width of each of the portions of the plurality of hole patterns positioned between the second portions of the mask pattern is constant from an upper portion to a lower portion.

[0016] In an embodiment, a width of a plurality of hole patterns is the same as a width of a plurality of adjacent hole patterns.

[0017] In an embodiment, the first part and the second part are physically connected as one.

[0018] In an embodiment, the mask pattern includes at least one of Invar, Super Invar, and Nickel.

[0019] In an embodiment, the mask substrate further includes: an electric field former configured to form an electric field.

[0020] According to aspects of the present disclosure, a method for manufacturing a deposition mask is provided, the method comprising: forming a mother substrate and a frame including a first material pattern on the mother substrate, a metal pattern on the first material pattern, and a second material pattern on the metal pattern; forming a first metal layer between the frames using an electroforming method; and forming a mask pattern including the first metal layer and a plurality of hole patterns spaced apart from each other on the mother substrate by removing the frame, wherein the second material pattern includes a tip protruding more than a side surface of the metal pattern.

[0021] In an embodiment, the first metal layer in the mask pattern includes: a first portion, positioned on a mother substrate; and a second portion, protruding from the first portion in a direction opposite to the mother substrate, the second portion including: a first protruding portion and a second protruding portion, arranged to be adjacent to a plurality of hole patterns; and a recessed portion, arranged between the first protruding portion and the second protruding portion, and a height of the recessed portion is less than a height of the first protruding portion and the second protruding portion.

[0022] In an implementation, a width of the metal pattern is the same as a width of an upper surface of the first material pattern.

[0023] In an embodiment, in the process of forming the first metal layer, the mother substrate further includes an electric field former configured to form an electric field, and the first metal layer grows in an upward direction from an upper surface of the mother substrate by the electric field formed by the electric field former.

[0024] In an embodiment, when forming the first metal layer, the first metal layer grows in a horizontal direction from a side surface of the metal pattern when the first metal layer contacts the metal pattern.

[0025] In an embodiment, when the first metal layer is formed, an electric field is formed in the metal pattern when the first metal layer contacts the metal pattern.

[0026] In an embodiment, the method may further include: forming a second material pattern by patterning the first material layer; forming a metal pattern by patterning the first metal layer using the second material pattern as a mask; and forming the first material pattern by patterning the second material layer using the metal pattern as a mask.

[0027] In an embodiment, the method may further include forming a mask substrate including an opening by etching a portion of the mother substrate.

[0028] According to aspects of the present disclosure, a display device manufactured using a mask substrate is provided, the mask substrate including an opening; and a mask pattern, which is arranged on the mask substrate and includes a plurality of hole patterns spaced apart from each other, the mask pattern also including: a first portion, which is positioned on the mask substrate; and a second portion, which protrudes from the first portion in a direction opposite to the mask substrate, the second portion including: a first protruding portion and a second protruding portion, which are arranged adjacent to the plurality of hole patterns; and a recessed portion, which is arranged between the first protruding portion and the second protruding portion, and the height of the recessed portion is less than the height of the first protruding portion and the second protruding portion, the display device including: a substrate; a plurality of light-emitting elements, which are arranged on the substrate; a dam, which is configured to separate the light-emitting elements; and a spacer, which is arranged on the dam, wherein the first protruding portion and the second protruding portion are configured to contact the spacer.

[0029] According to the deposition mask and the method for manufacturing the same according to the embodiments of the present disclosure, a pattern width may have high uniformity.

[0030] According to the deposition mask, the method for manufacturing the same, and the display device manufactured using the same according to the embodiment of the present disclosure, the deposition mask may be used to manufacture an ultra-high-resolution display.

[0031] However, the effects of the embodiments are not limited to those set forth herein. The above and other effects of the embodiments will become more apparent to those skilled in the art to which the embodiments pertain by referring to the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view showing an electronic device according to an embodiment;

[0034] Figure 2 is a perspective view showing a display device according to an embodiment;

[0035] Figure 3 is a view showing an example of a display panel according to an embodiment;

[0036] Figure 4 is a cross-sectional view showing a deposition mask according to an embodiment;

[0037] Figure 5 yes Figure 4 an enlarged view of a portion A of;

[0038] Figure 6 is a cross-sectional view showing a process of manufacturing a display device using a deposition mask according to an embodiment;

[0039] Figure 7 is a flow chart illustrating a method for manufacturing a deposition mask according to an embodiment;

[0040] Figure 8 It is shown Figure 7 A cross-sectional view of step S100;

[0041] Fig. 9 It is shown Figure 7 A cross-sectional view of step S200;

[0042] Fig.10 It is shown Figure 7 A cross-sectional view of step S300;

[0043] Fig.11 It is shown Figure 7A cross-sectional view of step S400;

[0044] Fig.12 yes Fig.11 an enlarged view of a portion B of;

[0045] Fig.13 It is shown Figure 7 A cross-sectional view of step S500;

[0046] Fig.14 and Fig.15 yes Fig.13 an enlarged view of a portion C of;

[0047] Fig.16 It is shown Figure 7 A cross-sectional view of step S600;

[0048] Fig.17 It is shown Figure 7 A cross-sectional view of step S700; and

[0049] Fig.18 and Fig.19 is a cross-sectional view comparing a method for manufacturing a deposition mask according to a conventional example and an embodiment. DETAILED DESCRIPTION

[0050] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0051] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0052] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a perspective view showing an electronic device according to an embodiment.

[0054] refer to Figure 1, the electronic device 1 according to the embodiment displays a moving image or a still image. The electronic device 1 may refer to any electronic device that provides a display screen. For example, the electronic device 1 may include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, an extended reality (XR) device such as a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation, a game console, a digital camera, a video camera, etc. that provide a display screen.

[0055] Figure 1 An augmented reality (AR) device is shown as an example of the electronic device 1 according to the embodiment. However, the electronic device 1 according to the embodiment is not limited thereto, and may be any of a virtual reality (VR) device and a mixed reality (MR) device, and may be any of the other electronic devices mentioned above. Hereinafter, for ease of explanation, an example in which the electronic device 1 according to the embodiment is an augmented reality (AR) device will be described.

[0056] The electronic device 1 according to the embodiment may be a glasses type device. The electronic device 1 may include a display device 10, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, glasses frame legs 30a and 30b, a reflective member 40, and a display device accommodating portion 50.

[0057] The display device 10 may provide a display screen. Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. Hereinafter, an example in which an organic light emitting diode display device is used as the display device 10 is shown, but the present disclosure is not limited thereto, and the present disclosure may also be applied to other display devices as long as the same technical idea can be applied thereto.

[0058] The left eye lens 10a and the right eye lens 10b can be configured as transparent lenses. For example, the left eye lens 10a and the right eye lens 10b may include a transparent material such as glass or plastic, and may be formed to be transparent or translucent. Therefore, the user can observe the real image through the left eye lens 10a and the right eye lens 10b. In some embodiments, the left eye lens 10a and the right eye lens 10b may also include a refractive lens configured to correct the user's vision. The left eye lens 10a and the right eye lens 10b may be assembled or attached to the support frame 20.

[0059] exist Figure 1, the left-eye lens 10a and the right-eye lens 10b are shown as being separated on the left and right sides, but the present disclosure is not limited thereto. For example, the electronic device 1 may also include left and right integrated lenses.

[0060] The eyeglass frame legs 30a and 30b may be connected to the support frame 20. The eyeglass frame legs 30a and 30b may be configured to fix the electronic device 1 to the user's body. For example, the eyeglass frame legs 30a and 30b may include curved portions so as to be placed over the user's ears.

[0061] exist Figure 1 , the electronic device 1 including the glasses frame legs 30a and 30b is shown, but the electronic device 1 according to the embodiment may also be a head-mounted electronic device including a head mounting band that can be mounted on the user's head instead of the glasses frame legs 30a and 30b.

[0062] The display device accommodating portion 50 may provide a space in which the display device 10 and the reflective member 40 may be accommodated. The image displayed on the display device 10 may be reflected by the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user may view the virtual reality image displayed on the display device 10 through the right eye.

[0063] exist Figure 1 , it is shown that the display device accommodating portion 50 is disposed at the right distal end of the support frame 20, but the embodiments of the present specification are not limited thereto. For example, the display device accommodating portion 50 may be disposed at the left distal end of the support frame 20. In this case, the image displayed on the display device 10 may be reflected by the reflective member 40 and provided to the user's left eye through the left eye lens 10a. Therefore, the user may view the virtual reality image displayed on the display device 10 through the left eye. Alternatively, the display device accommodating portion 50 may be disposed at both the left distal end and the right distal end of the support frame 20. In this case, the user may view the virtual reality image displayed on the display device 10 through both the left eye and the right eye.

[0064] Figure 2 is a perspective view showing a display device according to an embodiment.

[0065] Apart from Figure 1 In addition, reference Figure 2 The display device 10 may be an image display module configured to display an augmented reality content image superimposed on a real image visible to a user. To this end, the display device 10 may include a display panel 100 configured to display an augmented reality content image and an image transmission member 200 for transmitting the image to the left eye lens 10a and the right eye lens 10b.

[0066] The display panel 100 may provide a display screen that displays images such as augmented reality content images. Examples of the display panel 100 may include an organic light-emitting display panel, a micro-LED display panel, a nano-LED display panel, a quantum dot light-emitting display panel, a liquid crystal display panel, a plasma display panel, a field emission display panel, an electrophoretic display panel, and an electrowetting display panel. Hereinafter, a case where an organic light-emitting display panel is applied as an example of the display panel 100 will be described by way of example, but the present disclosure is not limited thereto, and the present disclosure may be applied to other display panels as long as the same technical concept can be applied.

[0067] The image transmission member 200 may include at least one of an optical waveguide (e.g., a prism), a diffusion lens 210, and a focusing lens 220. Therefore, the augmented reality content image displayed through the display panel 100 may be provided to the focal plane FP through the optical members such as the optical waveguide, the diffusion lens 210, and the focusing lens 220. The focal plane FP may be formed on the left-eye lens 10a and the right-eye lens 10b or directly on the user's retina.

[0068] Figure 3 is a view showing an example of a display panel according to an embodiment.

[0069] refer to Figure 3 The display panel 100 may include a base member BS, a display layer DU, and a thin film encapsulation layer TFEL. The display layer DU may include a thin film transistor layer TFTL and a light emitting element layer EML.

[0070] The base member BS may include a first substrate SUB1, a first buffer film BF1 disposed on the first substrate SUB1, and a second substrate SUB2 disposed on the first buffer film BF1.

[0071] The first substrate SUB1 and the second substrate SUB2 may be made of an insulating material such as glass, quartz or a polymer resin. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) or a combination thereof. Optionally, the substrate may also include a metal material.

[0072] The first substrate SUB1 and the second substrate SUB2 may be rigid substrates or flexible substrates that may be bent, folded, and rolled. When the substrate is a flexible substrate, the substrate may be formed of polyimide (PI), but is not limited thereto.

[0073] The first buffer film BF1 is a film for protecting the first thin film transistor ST1 and the light emitting layer 172 from moisture penetrating through the first substrate SUB1 and the second substrate SUB2 susceptible to moisture penetration. The first buffer film BF1 may be formed of a plurality of inorganic layers alternately stacked. For example, the first buffer film BF1 may be formed of a plurality of films in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0074] The thin film transistor layer TFTL may include a lower metal layer BML, a second buffer film BF2, a first thin film transistor ST1, a first gate insulating film GI1, a first interlayer insulating film 141, a first capacitor electrode CAE1, a second interlayer insulating film 142, a first anode connection electrode ANDE1, a first organic film 160, a second anode connection electrode ANDE2, and a second organic film 180. In an embodiment, the first interlayer insulating film 141 and the second interlayer insulating film 142 may be collectively referred to as an interlayer insulating film 140.

[0075] The lower metal layer BML may be disposed on the second substrate SUB2. The lower metal layer BML may be disposed to overlap the first active layer ACT1 of the first thin film transistor ST1 in the thickness direction to prevent leakage current from occurring when light is incident on the first active layer ACT1 of the first thin film transistor ST1. The lower metal layer BML may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The lower metal layer BML may be omitted.

[0076] The second buffer film BF2 may be disposed on the lower metal layer BML. The second buffer film BF2 is a film for protecting the first thin film transistor ST1 and the light emitting layer 172 from moisture penetrating through the first substrate SUB1 and the second substrate SUB2 susceptible to moisture penetration. The second buffer film BF2 may be formed of a plurality of inorganic layers alternately stacked. For example, the second buffer film BF2 may be formed of a plurality of films in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0077] The first active layer ACT1 of the first thin film transistor ST1 may be disposed on the second buffer film BF2. The first active layer ACT1 of the first thin film transistor ST1 includes polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. The first active layer ACT1 of the first thin film transistor ST1 that is exposed and not covered by the first gate insulating film GI1 may be doped with impurities or ions to have conductivity. Thus, a first source electrode TS1 and a first drain electrode TD1 of the first active layer ACT1 of the first thin film transistor ST1 may be formed.

[0078] The first gate insulating film GI1 may be disposed on the first active layer ACT1 of the first thin film transistor ST1. Figure 3 1 and 2 show that the first gate insulating film GI1 is disposed between the first gate electrode TG1 of the first thin film transistor ST1 and the first active layer ACT1, but the present disclosure is not limited thereto. The first gate insulating film GI1 may also be disposed between the first interlayer insulating film 141 and the first active layer ACT1 and between the first interlayer insulating film 141 and the second buffer film BF2. The first gate insulating film GI1 may be formed as an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0079] The first gate electrode TG1 of the first thin film transistor ST1 may be disposed on the first gate insulating film GI1. The first gate electrode TG1 of the first thin film transistor ST1 may overlap the first active layer ACT1 in the thickness direction. The first gate electrode TG1 of the first thin film transistor ST1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0080] The first interlayer insulating film 141 may be disposed on the first gate electrode TG1 of the first thin film transistor ST1. The first interlayer insulating film 141 may be formed as an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include a plurality of inorganic films.

[0081] The first capacitor electrode CAE1 may be disposed on the first interlayer insulating film 141. The first capacitor electrode CAE1 may overlap the first gate electrode TG1 of the first thin film transistor ST1 in the third direction (thickness direction). Since the first interlayer insulating film 141 has a predetermined dielectric constant, a capacitor may be formed by the first capacitor electrode CAE1, the first gate electrode TG1, and the first interlayer insulating film 141 disposed between the first capacitor electrode CAE1 and the first gate electrode TG1. The first capacitor electrode CAE1 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0082] The second interlayer insulating film 142 may be disposed on the first capacitor electrode CAE1. The second interlayer insulating film 142 may be formed as an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include a plurality of inorganic films.

[0083] The first anode connection electrode ANDE1 may be disposed on the second interlayer insulating film 142. The first anode connection electrode ANDE1 may be connected to the first drain electrode TD1 of the first thin film transistor ST1 through a first anode contact hole ANCT1 that penetrates the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the first drain electrode TD1 of the first thin film transistor ST1. The first anode connection electrode ANDE1 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0084] The first organic film 160 for planarization may be disposed on the first anode connection electrode ANDE 1. The first organic film 160 may be formed as an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0085] The second anode connection electrode ANDE2 may be disposed on the first organic film 160. The second anode connection electrode ANDE2 may be connected to the first anode connection electrode ANDE1 through a second anode contact hole ANCT2 penetrating the first organic film 160 to expose the first anode connection electrode ANDE1. The second anode connection electrode ANDE2 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0086] The second organic film 180 may be disposed on the second anode connection electrode ANDE2. The second organic film 180 may be formed as an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0087] exist Figure 3 1 shows that the first thin film transistor ST1 is formed as a top gate type in which the first gate electrode TG1 is positioned above the first active layer ACT1, but the present disclosure is not limited thereto. The first thin film transistor ST1 may be formed as a bottom gate type in which the first gate electrode TG1 is positioned below the first active layer ACT1 or a dual gate type in which the first gate electrode TG1 is positioned both above and below the first active layer ACT1.

[0088] The light emitting element layer EML may be disposed on the second organic film 180. The light emitting element layer EML may include light emitting elements 170 and a bank 190. Each of the light emitting elements 170 may include a first light emitting electrode 171, a light emitting layer 172, and a second light emitting electrode 173.

[0089] The first light emitting electrode 171 may be formed on the second organic film 180. The first light emitting electrode 171 may be connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCT3 penetrating the second organic film 180 to expose the second anode connection electrode ANDE2.

[0090] The first light emitting electrode 171 may be formed on the second organic film 180. The first light emitting electrode 171 may be connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCT3 penetrating the second organic film 180 to expose the second anode connection electrode ANDE2.

[0091] In a top emission structure in which light is emitted toward the second light emitting electrode 173 based on the light emitting layer 172, the first light emitting electrode 171 may be formed of a metal material having high reflectivity such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0092] The bank 190 may be formed to partition the first light emitting electrode 171 on the second organic film 180 to define the light emitting area EA. The bank 190 may be formed to cover the edge of the first light emitting electrode 171. The bank 190 may be formed as an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0093] The plurality of pixels PX may include corresponding emission areas EA. The plurality of pixels PX may include multi-color pixels PX including corresponding emission areas EA for realizing different colors. For example, the plurality of pixels PX may include, but are not limited to, a first red pixel PX1, a second green pixel PX2, and a third blue pixel PX3.

[0094] The spacer 191 may be disposed on the bank 190. The spacer 191 may be used to support the deposition mask 500 during the process of manufacturing the light emitting layer 172 (see Figure 4 ). The spacer 191 may be formed as an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0095] The emission area EA refers to a region where the first emission electrode 171 , the emission layer 172 , and the second emission electrode 173 are sequentially stacked and holes from the first emission electrode 171 and electrons from the second emission electrode 173 are combined with each other in the emission layer 172 to emit light.

[0096] The light emitting layer 172 is formed on the first light emitting electrode 171 and the bank 190. The light emitting layer 172 may include an organic material to emit light of a predetermined color. For example, the light emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0097] The second light emitting electrode 173 may be disposed on the light emitting layer 172. The second light emitting electrode 173 may be formed to cover the light emitting layer 172. The second light emitting electrode 173 may be a common layer commonly formed in all light emitting areas EA. Although not shown, a capping layer may be formed on the second light emitting electrode 173.

[0098] In the top emission structure, the second light emitting electrode 173 may be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second light emitting electrode 173 is formed of a semi-transmissive conductive material, light emission efficiency may be improved by the microcavity.

[0099] The thin film encapsulation layer TFEL may be disposed on the second light emitting electrode 173. The thin film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust. For example, the thin film encapsulation layer TFEL may include a first encapsulation film TFE1, a second encapsulation film TFE2, and a third encapsulation film TFE3.

[0100] The first encapsulation film TFE1 (e.g., a first inorganic encapsulation film) may be disposed on the second light emitting electrode 173. The first encapsulation film TFE1 may be a single layer or a plurality of layers of an inorganic film. The first encapsulation film TFE1 may be formed as a plurality of films or a single film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0101] The second encapsulation film TFE2 (e.g., the first organic encapsulation film) may be disposed on the first encapsulation film TFE1. The second encapsulation film TFE2 may be a single layer or a plurality of layers of an organic film. The second encapsulation film TFE2 may include a polymer-based material. Examples of polymer-based materials may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0102] The third encapsulation film TFE3 (e.g., the second inorganic encapsulation film) may be disposed on the second encapsulation film TFE2. The third encapsulation film TFE3 may be a single layer or a plurality of layers of an inorganic film. The third encapsulation film TFE3 may include the same material as the first encapsulation film TFE1. For example, the third encapsulation film TFE3 may be formed as a plurality of films or a single film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0103] Hereinafter, a deposition mask for manufacturing the above-described display device 10 will be described.

[0104] Figure 4 is a cross-sectional view illustrating a deposition mask according to an embodiment. Figure 5 yes Figure 4 Magnified view of portion A.

[0105] refer to Figure 4 and Figure 5 The deposition mask 500 according to the embodiment may be a mask for manufacturing an ultra-high resolution display. For example, the deposition mask 500 may be a mask for manufacturing a display included in an extended reality device (XR device) such as a VR device, an AR device, or an MR device.

[0106] In some embodiments, the deposition mask 500 can be used to perform a pixel deposition process on a silicon wafer that is a large area substrate that is not used in a conventional display. In the case of a display included in an extended reality device, since its screen is positioned directly in front of the user's eyes, the display can have a small screen instead of a large screen. In addition, since the display is positioned close to the user's eyes, an ultra-high resolution may be required. For example, a display included in an extended reality device may require a resolution of approximately 1000PPI or greater, and preferably may require an ultra-high resolution of 2000PPI or greater. The deposition mask 500 according to an embodiment may be a mask for manufacturing such an ultra-high resolution display.

[0107] The deposition mask 500 may include a mask substrate 510 and a mask pattern 520. In an implementation, the deposition mask 500 may be a mask in which the mask pattern 520 is directly mounted on the mask substrate 510.

[0108] The mask substrate 510 may include a silicon wafer. Since the silicon wafer can be processed more finely and accurately than a large area substrate by utilizing the technology developed in semiconductor processing, the silicon wafer can be used as a substrate for an ultra-high resolution display. The deposition mask 500 according to the embodiment can use the same silicon wafer to form pixels on the silicon wafer of such an ultra-high resolution display.

[0109] The mask substrate 510 may have a shape corresponding to the silicon wafer of the ultra-high resolution display. For example, the mask substrate 510 may have the same size or shape as the silicon wafer of the ultra-high resolution display.

[0110] However, the mask substrate 510 is not limited thereto and may also include a large area substrate in another embodiment. For example, the mask substrate 510 may also include materials such as glass, quartz, and polymer resin.

[0111] The mask substrate 510 may include a mask opening OP positioned on opposite sides of the mask pattern 520. The inner surface of the mask opening OP may be an inclined surface. For example, the mask opening OP may be formed by a method S1 for manufacturing a deposition mask to be described later (see Figure 7 ) in etching the mother substrate MSUB (see Fig.16 ) is formed by a portion of the mask opening OP. In this case, when wet etching is performed, the inner surface of the mask opening OP may have an inclined surface due to the isotropy of the etchant.

[0112] The mask opening OP may be a deposition source DSC (see Figure 6 ) provides a passage for moving toward the mask pattern 520. The mask substrate 510 may block the deposition source DSC in a region other than a region where the mask opening OP is located (see Figure 6 ).

[0113] Although not shown, the mask substrate 510 may further include an electric field former (not shown) configured to form an electric field. The electric field former (not shown) of the mask substrate 510 may be a wiring or an electrode capable of applying a voltage. The electric field former (not shown) may form an electric field for use in the method S1 for manufacturing a deposition mask to be described later (see Figure 7 ) using an electroforming method. As the electric field former (not shown) of the mask substrate 510 forms an electric field, the second metal layer MTL2 (see Fig.14 ) can be obtained from the framework FRM (see Fig.14 ) grows from the lower part.

[0114] The mask pattern 520 may include a plurality of metal patterns spaced apart from each other in the first direction DR1 or the second direction DR2 in cross section. The plurality of metal patterns are spaced apart from each other in cross section, but may be one mask pattern 520 connected to each other in plan view. Hereinafter, the mask pattern 520 may be a term referring to all of the plurality of metal patterns disposed on the mask substrate 510 as a single component, and may be a term referring to a component of each of the plurality of metal patterns. That is, the mask pattern 520 may be interchangeably used to refer to the entire group of the plurality of metal patterns as a single component, or to refer to each of the plurality of metal patterns.

[0115] In the drawings shown, the first direction DR1 and the second direction DR2 are horizontal directions, respectively, and intersect each other. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. In addition, the third direction DR3 may be a vertical direction intersecting with the first direction DR1 and the second direction DR2 (for example, orthogonal to the first direction DR1 and the second direction DR2). In this specification, the direction indicated by the arrows in the first direction DR1, the second direction DR2, and the third direction DR3 may be referred to as one side, and the opposite direction thereof may be referred to as the other side.

[0116] The mask pattern 520 may include at least one of invar and super invar. In another embodiment, the mask pattern 520 may also include nickel (Ni). However, the mask pattern 520 is not limited thereto, and may include a material having a low thermal expansion coefficient and being magnetic. The mask pattern 520 may have a circular shape in a plan view, but is not limited thereto. The height 520_H of the mask pattern 520 may be approximately 1 μm to 5 μm, but is not limited thereto.

[0117] like Figure 5 As shown in FIG. 5 , the mask pattern 520 may include a first portion 521 and a second portion 522 disposed on the first portion 521. In this specification, for convenience of explanation, the first portion 521 and the second portion 522 are described separately, but the first portion 521 and the second portion 522 may be one component physically connected to each other.

[0118] The first portion 521 may include a first surface 521a, a second surface 521b positioned on an opposite side of the first surface 521a, and a first side surface 521c disposed between the first surface 521a and the second surface 521b. The first surface 521a may be a surface close to the mask substrate 510, and the second surface 521b may be a surface opposite to the mask substrate 510. The first side surface 521c may be a surface connecting the first surface 521a and the second surface 521b.

[0119] The first portion 521 may have an inverted tapered shape. For example, the width 521_W1 of the first surface 521a may be smaller than the width 521_W2 of the second surface 521b. That is, the first portion 521 may have a narrower width from the second surface 521b toward the first surface 521a. The width 521_W2 of the second surface 521b may be approximately 5 μm or less, but is not limited thereto. The first side surface 521c may be an inclined surface inclined from the second surface 521b toward the first surface 521a toward the inner side of the first portion 521.

[0120] The second portion 522 may be disposed on the first portion 521. The second portion 522 may be positioned on the opposite side of the mask substrate 510, and the first portion 521 is interposed between the second portion 522 and the mask substrate 510. The second portion 522 may have a shape protruding from the first portion 521 in the third direction DR3. The second portion 522 may include a first protruding portion 522a, a recessed portion 522b, and a second protruding portion 522c. A width 522_W2 of the second portion 522 may be the same as a width 521_W2 of a second surface 521b of the first portion 521.

[0121] The first protrusion portion 522a and the second protrusion portion 522c may have a shape protruding from the first portion 521. The first protrusion portion 522a and the second protrusion portion 522c may be spaced apart from each other in the first direction DR1 or the second direction DR2 in cross section. However, it is shown that the first protrusion portion 522a and the second protrusion portion 522c are disposed to be spaced apart from each other in cross section, but in some embodiments, the first protrusion portion 522a and the second protrusion portion 522c may be components connected to each other in a plan view.

[0122] The recessed portion 522b may be disposed between the first protruding portion 522a and the second protruding portion 522c. The recessed portion 522b may have a shape recessed toward the first portion 521 instead of the first protruding portion 522a and the second protruding portion 522c. For example, the height of the recessed portion 522b in the third direction DR3 may be smaller than the heights of the first protruding portion 522a and the second protruding portion 522c.

[0123] The mask pattern 520 may include a plurality of hole patterns HPT spaced apart from each other between the mask patterns 520 adjacent to each other (eg, a plurality of metal patterns adjacent to each other).

[0124] The plurality of hole patterns HPT may have a positive tapered shape. For example, the upper width HPT_W2 of the plurality of hole patterns HPT may be narrower than the lower width HPT_W1. The upper width HPT_W2 of the plurality of hole patterns HPT may be 2.5 μm or less, but is not limited thereto. The width of each of the portions of the plurality of hole patterns HPT positioned between the second portions 522 of the mask pattern 520 may be constant from the upper portion to the lower portion.

[0125] In some embodiments, all of the plurality of hole patterns HPT may overlap with the mask opening OP of the mask substrate 510. Therefore, the deposition source DSC (see Figure 6 ) can reach multiple hole patterns HPT.

[0126] Figure 6is a cross-sectional view illustrating a process of manufacturing a display device using a deposition mask according to an embodiment.

[0127] Apart from Figures 3 to 5 In addition, reference Figure 6 The deposition mask 500 may be used to form the light emitting layer 172 for each pixel PX of the display panel 100. The display panel 100 may be arranged such that the base member BS is positioned away from the deposition source supply unit DSP. For example, the base member BS may be arranged in an upward direction, and the pixel PX may be arranged in a downward direction.

[0128] When the first pixel PX1, the second pixel PX2, and the third pixel PX3 are pixels realizing different colors, the material of the light emitting source included in the light emitting layer 172 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be different. That is, the deposition source DSC used to form the light emitting layer 172 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be different.

[0129] Therefore, when the light emitting layer 172 is formed on any one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the pixel PX on which the light emitting layer 172 is formed may be disposed to overlap the hole pattern HPT, and the pixel PX on which the light emitting layer 172 is not formed may be disposed to overlap the mask pattern 520. Therefore, the deposition source DSC ejected from the deposition source supply unit DSP may pass through the mask opening OP of the mask substrate 510 and the hole pattern HPT of the mask pattern 520 only in the pixel PX on which the light emitting layer 172 is formed, and may be disposed on the base member BS of the display panel 100.

[0130] The deposition mask 500 may be disposed on the spacer 191 of the display panel 100. For example, the first and second protrusions 522a and 522c of the second portion 522 may be disposed on the spacer 191. The first and second protrusions 522a and 522c of the second portion 522 may directly contact the spacer 191.

[0131] Since the deposition mask 500 according to the present embodiment includes the first protruding portion 522a, the recessed portion 522b, and the second protruding portion 522c in the second portion 522, the contact area with the spacer 191 may be minimized. Therefore, the occurrence of defects due to contact between the deposition mask 500 and the display panel 100 may be minimized.

[0132] Meanwhile, in the deposition mask 500 according to the present embodiment, the upper width HPT_W2 of the plurality of hole patterns HPT may be formed to be the same as the upper width HPT_W2 of the plurality of adjacent hole patterns HPT. Figure 1 and Figure 2 For an ultra-high-resolution display like the display device 10 described in the embodiment, it is necessary to form the upper width HPT_W2 of the plurality of hole patterns HPT to be completely the same as the upper width HPT_W2 of the plurality of adjacent hole patterns HPT. Therefore, according to the deposition mask 500 of the present embodiment, a deposition mask 500 having high uniformity of the critical dimension (CD) of the width of the plurality of hole patterns HPT can be provided. A method for manufacturing the deposition mask 500 having high uniformity of the critical dimension (CD) of the width of the plurality of hole patterns HPT will be described below.

[0133] Figure 7 is a flowchart illustrating a method for manufacturing a deposition mask according to an embodiment. Figure 8 It is shown Figure 7 FIG. 5 is a cross-sectional view of step S100. Fig. 9 It is shown Figure 7 FIG. 5 is a cross-sectional view of step S200. Fig.10 It is shown Figure 7 FIG. 5 is a cross-sectional view of step S300. Fig.11 It is shown Figure 7 A cross-sectional view of step S400. Fig.12 yes Fig.11 An enlarged view of portion B. Fig.13 It is shown Figure 7 FIG. 5 is a cross-sectional view of step S500. Fig.14 and Fig.15 yes Fig.13 An enlarged view of portion C. Fig.16 It is shown Figure 7 FIG. 5 is a cross-sectional view of step S600. Fig.17 It is shown Figure 7 FIG. 5 is a cross-sectional view of step S700.

[0134] refer to Figures 7 to 17 According to an embodiment, a method S1 for manufacturing a deposition mask may include a step of forming a first material layer, a first metal layer, and a second material layer on a mother substrate (S100), a step of forming a first material pattern by patterning the first material layer (S200), a step of forming a metal pattern by patterning the first metal layer (S300), a step of forming a second material pattern by patterning the second material layer (S400), a step of forming a second metal layer between frames by an electroforming method (S500), a step of forming a mask pattern including a hole pattern by removing the frame (S600), and a step of forming a mask substrate including a mask opening by etching a portion of the mother substrate (S700).

[0135] like Figure 8As shown in, in the step (S100) of forming a first material layer, a first metal layer and a second material layer on a mother substrate, a second material layer PRL2 can be set on the mother substrate MSUB, a first metal layer MTL1 can be set on the second material layer PRL2, and the first material layer PRL1 can be set on the first metal layer MTL1.

[0136] The mother substrate MSUB may include the above reference Figure 4 The mask substrate 510 described (see Figure 4 )same materials.

[0137] The first material layer PRL1 and the second material layer PRL2 may include a photosensitive material such as a photoresist. The first material layer PRL1 and the second material layer PRL2 may include the same material, but are not limited thereto.

[0138] The first metal layer MTL1 may include a metal material having high conductivity and high reactivity to an etchant. For example, the first metal layer MTL1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0139] like Fig. 9 As shown in FIG. 2 , in the step (S200) of forming the first material pattern by patterning the first material layer, the first material layer PRL1 may be patterned by an exposure and development process. For example, after aligning a separate exposure mask (not shown) on the first material layer PRL1, the first material layer PRL1 may be exposed to light such as ultraviolet rays.

[0140] When the type of photoresist included in the first material layer PRL1 is positive or negative, a portion exposed to light may be dissolved and disappear by a developer, or conversely, a portion not exposed to light may be dissolved and disappear. Thus, a first material pattern PR1 may be formed.

[0141] like Fig.10 As shown in , in the step (S300) of forming a metal pattern by patterning the first metal layer, the first metal layer MTL1 may be patterned by an etching process using the first material pattern PR1 provided on the first metal layer MTL1 as a mask. For example, a portion of the first metal layer MTL1 overlapping with the first material pattern PR1 may not be etched by an etchant, and a portion of the first metal layer MTL1 not overlapping with the first material pattern PR1 may be etched by an etchant. Thus, a metal pattern MTP may be formed.

[0142] However, in the method S1 for manufacturing a deposition mask according to the present embodiment, a portion of the first metal layer MTL1 overlapping with the first material pattern PR1 may be further etched. For example, when a wet etching process is performed, the etchant may penetrate into a lower portion of the first material pattern PR1 and over-etch the first metal layer MTL1. In addition, the first metal layer MTL1 may be over-etched to form a tip in the first material pattern PR1 that protrudes more than the metal pattern MTP.

[0143] like Fig.11 As shown in, in the step (S400) of forming the second material pattern by patterning the second material layer, the second material layer PRL2 may be patterned by an exposure and development process using the metal pattern MTP disposed on the second material layer PRL2 as a mask. For example, a portion of the second material layer PRL2 overlapping with the metal pattern MTP may not be exposed to the exposure light, and a portion of the second material layer PRL2 not overlapping with the metal pattern MTP may be exposed to the exposure light.

[0144] When the type of photoresist included in the second material layer PRL2 is positive or negative, a portion exposed to light may be dissolved and disappear by a developer, or conversely, a portion not exposed to light may be dissolved and disappear. Thus, a second material pattern PR2 may be formed.

[0145] like Fig.12 As shown in FIG, the first material pattern PR1, the metal pattern MTP, and the second material pattern PR2 may be included in the frame FRM.

[0146] The second material pattern PR2 may have a positive tapered shape. For example, the width PR2b_W of the upper surface PR2b of the second material pattern PR2 may be less than the width PR2a_W of the lower surface PR2a of the second material pattern PR2. That is, the width of the second material pattern PR2 may increase from the upper surface PR2b to the lower surface PR2a. The side surface of the second material pattern PR2 may be an inclined surface inclined outward from the upper surface PR2b to the lower surface PR2a.

[0147] The side surface of the metal pattern MTP may be a substantially vertical surface. The width MTP_W of the metal pattern MTP may be the same as the width PR2b_W of the upper surface PR2b of the second material pattern PR2. The distance MTP_D between adjacent metal patterns MTP may be greater than the distance PR2_D between adjacent lower surfaces PR2a of the second material pattern PR2.

[0148] The side surface of the first material pattern PR1 may be a substantially vertical surface. The first material pattern PR1 may include a tip TIP that protrudes more than the side surface of the metal pattern MTP. The width PR1_W of the first material pattern PR1 may be greater than the width MTP_W of the metal pattern MTP.

[0149] Therefore, the distance PR1_D between the first material patterns PR1 adjacent to each other may be smaller than the distance MTP_D between the metal patterns MTP adjacent to each other. For example, the distance PR1_D between the first material patterns PR1 adjacent to each other may be about 4 μm or less, and the distance MTP_D between the metal patterns MTP adjacent to each other may be about 5 μm or less, but is not limited thereto. The width TIP_W of the tip TIP may be approximately 0.5 μm on each side, but is not limited thereto.

[0150] like Figures 13 to 15 As shown in FIG. 5 , in the step ( S500 ) of forming the second metal layer between the frames by the electroforming method, the second metal layer MTL2 may be formed between the frames FRM on the mother substrate MSUB. The second metal layer MTL2 may be grown between the frames FRM by the electroforming method.

[0151] The second metal layer MTL2 may include at least one of invar, super invar, and nickel. The second metal layer MTL2 may be formed by depositing metal ions from an electroplating solution including at least one of invar, super invar, and nickel.

[0152] For example, the mother substrate MSUB may include an electric field former (not shown). The electric field former (not shown) may be used as a first electrode. A second electrode (not shown) opposite to the electric field former may be additionally provided to form an electric field. The frame FRM may have an insulating property to prevent the second metal layer MTL2 from being formed on the frame FRM.

[0153] The mother substrate MSUB including the frame FRM and the second electrode (not shown) may be immersed in an electroplating solution. Due to the electric field formed between the first electrode (field former) and the second electrode, the second metal layer MTL2 may grow vertically from the surface of the mother substrate MSUB between the frame FRM.

[0154] like Fig.14As shown in, when the second metal layer MTL2 grown from the surface of the mother substrate MSUB reaches the boundary point P1 where the second material pattern PR2 and the metal pattern MTP intersect, the second metal layer MTL2 may contact the metal pattern MTP. The metal pattern MTP that is not charged when the second metal layer MTL2 is first grown may be electrically connected to the electric field former (not shown) through the second metal layer MTL2 by contacting the second metal layer MTL2. Therefore, the metal pattern MTP may have the same potential as the first electrode.

[0155] like Fig.15 As shown in , the second metal layer MTL2 may also be grown in a horizontal direction on the side surface of the metal pattern MTP having the same potential as the first electrode. Figure 5 The mask pattern 520 has the same shape as described.

[0156] like Fig.16 As shown in , in the step (S600) of forming a mask pattern including a hole pattern by removing the frame, the frame FRM can be removed. For example, the frame FRM can be removed by a stripping process for removing the photoresist. While removing the second material pattern PR2, the metal pattern MTP and the first material pattern PR1 can be removed together. Therefore, the second metal layer MTL2 remains on the mother substrate MSUB, so that only the mask pattern 520 can be formed, and the hole pattern HPT can be formed at the position where the frame FRM is located.

[0157] like Fig.17 As shown in FIG. 5 , in the step ( S700 ) of forming the mask substrate including the mask opening by etching a portion of the mother substrate MSUB, the mask opening OP may be formed by etching a portion of the mother substrate MSUB overlapping the mask pattern 520 .

[0158] In some embodiments, the mask opening OP may be formed by a wet etching process In this case, an inclined surface may be formed on a side surface of the mask opening OP due to isotropy.

[0159] According to the method S1 for manufacturing the deposition mask according to the present embodiment, the deposition mask 500 in which the mask substrate 510 and the mask pattern 520 are integrally formed may be manufactured.

[0160] Fig.18 and Fig.19 is a cross-sectional view comparing a method for manufacturing a deposition mask according to a conventional example and an embodiment. Fig.18 A method for manufacturing a deposition mask according to a conventional example is shown, and Fig.19 A method for manufacturing a deposition mask according to an embodiment is shown.

[0161] refer to Fig.18 and Fig.19 According to the method for manufacturing a deposition mask according to conventional examples and embodiments, when the second metal layers MTL2' and MTL2 are formed between the frames FRM' and FRM according to the electroforming method, the sizes of the second metal layers MTL2' and MTL2 grown for each pattern may be different. For example, when the second metal layers MTL2' and MTL2 are formed according to the electroforming method, the minimum size patterns MTL2'_m and MTL2_m and the maximum size patterns MTL2'_M and MTL2_M may be formed, respectively.

[0162] According to the method for manufacturing a deposition mask according to the conventional example, since the second metal layer MTL2' includes only the second material pattern PR2' when growing in an inverted tapered shape, the maximum width MTL2'_m_W of the minimum size pattern MTL2'_m and the maximum width MTL2'_M_W of the maximum size pattern MTL2'_M may be different. Therefore, since the width CD'_W of the critical dimension formed between the minimum size pattern MTL2'_m and the maximum size pattern MTL2'_M varies between each pattern, the uniformity of the critical dimension may be reduced.

[0163] On the other hand, according to the method for manufacturing a deposition mask according to the present embodiment, since the metal pattern MTP and the first material pattern PR1 are also included on the second material pattern PR2 after the second metal layer MTL2 grows in an inverted cone shape, the widths of the minimum size pattern MTL2_m and the maximum size pattern MTL2_M can be the same.

[0164] For example, in the method for manufacturing a deposition mask according to an embodiment, the width Wm of the protruding portion of the minimum size pattern MTL2_m may be smaller than the width WM of the protruding portion of the maximum size pattern MTL2_M. However, since the second metal layer MTL2 grows in the horizontal direction on the side surface of the metal pattern MTP, even if the width Wm of the protruding portion of the minimum size pattern MTL2_m is smaller than the width WM of the protruding portion of the maximum size pattern MTL2_M, the widths of the minimum size pattern MTL2_m and the maximum size pattern MTL2_M may be the same.

[0165] Therefore, since the width CD_W of the critical dimension formed between the minimum size pattern MTL2_m and the maximum size pattern MTL2_M is constant between the patterns, the uniformity of the critical dimension can be improved. Therefore, the reliability as a deposition mask for an ultra-high resolution display can be improved.

[0166] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present disclosure. Therefore, the preferred embodiments of the present disclosure disclosed are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A deposition mask, characterized in that include: a mask substrate including an opening; as well as a mask pattern disposed on the mask substrate and including a plurality of hole patterns spaced apart from each other, Wherein, the mask pattern further includes: a first portion on the mask substrate; and a second portion protruding from the first portion in a direction opposite to the mask substrate, The second part includes: first and second protruding portions disposed adjacent to the plurality of hole patterns; and a recessed portion disposed between the first protruding portion and the second protruding portion, and The height of the recessed portion is smaller than heights of the first protruding portion and the second protruding portion.

2. The deposition mask according to claim 1, characterized in that The first portion has an inverted tapered shape.

3. The deposition mask according to claim 2, characterized in that The first part includes: a first surface positioned proximate to the mask substrate; a second surface positioned on an opposite side of the first surface; and a first side surface disposed between the first surface and the second surface, and The width of the first surface is smaller than the width of the second surface.

4. The deposition mask according to claim 3, characterized in that The first side surface is an inclined surface inclined from the second surface toward the first surface toward the inner side of the first portion.

5. The deposition mask according to claim 1, characterized in that Each of the plurality of hole patterns has a forward tapered shape.

6. The deposition mask according to claim 5, characterized in that An upper width of each of the plurality of hole patterns is narrower than a lower width.

7. The deposition mask according to claim 6, characterized in that A width of each portion of the plurality of hole patterns positioned between the second portions of the mask pattern is constant from an upper portion to a lower portion.

8. The deposition mask according to claim 1, characterized in that The first portion and the second portion are integral with each other.

9. The deposition mask according to claim 1, characterized in that The mask substrate further includes an electric field former configured to form an electric field.

10. A display device, characterized in that include: substrate; A plurality of light emitting elements are arranged on the substrate; a bank configured to separate the plurality of light emitting elements; as well as a spacer, disposed on the bank, wherein the display device is manufactured using a mask including a mask pattern disposed on a mask substrate, the mask substrate including an opening, and the mask pattern including a plurality of hole patterns spaced apart from each other, the mask pattern also including a first portion positioned on the mask substrate and a second portion protruding from the first portion in a direction opposite to the mask substrate, the second portion including a first protruding portion and a second protruding portion disposed adjacent to the plurality of hole patterns and a recessed portion disposed between the first protruding portion and the second protruding portion, and a height of the recessed portion is smaller than a height of the first protruding portion and the second protruding portion, and The first protruding portion and the second protruding portion are configured to be in contact with the spacer.

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