High-precision resistance detection circuit, chip and electronic equipment

Abstract

The utility model discloses a high-precision resistance detection circuit, a chip and electronic equipment. The high-precision resistance detection circuit comprises a current mirror module, a driving module, a resistance detection module and a reference resistor, the current mirror module is connected with the resistance detection module and is used for providing stable voltage for the resistance detection module; the driving module is connected with the reference resistor and the first end of the tested resistor and is used for providing current for the reference resistor and the tested resistor; the first end of the reference resistor is also connected with the resistance detection module, and the second end is grounded for providing the resistance value of the reference resistor for the resistance detection module; and the resistance detection module is used for detecting the resistance value of the detected resistor according to the resistance value of the reference resistor. The device has the advantages of high precision, simple structure, low cost benefit and high reliability.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit technology, and in particular to a high-precision resistance detection circuit, chip and electronic equipment. Background Art

[0002] Resistance values ​​often need to be monitored and detected in electronic circuits to ensure normal operation of the circuit and the safety of the equipment. Changes in resistance may affect the performance of the circuit or even cause circuit failure. Therefore, various resistance detection circuits have been developed to detect in real time whether the resistance value in the circuit is within a predetermined range.

[0003] Threshold comparator circuit, a comparator circuit constructed using an operational amplifier can detect resistance changes. The resistor in the circuit is connected in series with a reference resistor, and then the voltage of the two resistor divider points is compared with the preset reference voltage by the comparator. If the change in resistance value causes the voltage at the divider point to be higher or lower than the reference voltage, the output of the comparator will switch, indicating the change in resistance value. However, the comparator detects resistance changes based on a fixed reference voltage, which may result in insufficient sensitivity to small resistance changes. In addition, the accuracy of the circuit is limited by the stability of the comparator and the reference voltage source, and there is a problem of insufficient reliability.

[0004] Voltage window comparator, this circuit uses two comparators to form a voltage window, which can detect whether the resistance value falls within a specific voltage range. If the voltage caused by the resistor falls outside this window, the circuit will output a signal. However, the voltage window comparator requires two comparators and additional circuit components to set the window threshold, which increases the complexity and cost of the circuit.

[0005] Wheatstone bridge, when a certain resistance in the bridge circuit changes, the balance state of the bridge circuit is destroyed, and a differential voltage is generated, which can then be amplified and detected. Although this method has high sensitivity, it also requires precise matching of resistors and complex adjustment processes, which increases the difficulty of design and production.

[0006] Although the existing technology provides a variety of resistance detection solutions, they often have problems such as high cost, great complexity and insufficient reliability. Utility Model Content

[0007] In view of this, the utility model provides a high-precision resistance detection circuit, chip and electronic equipment.

[0008] The first scheme, the embodiment of the present application provides a high-precision resistance detection circuit, including a current mirror module, a driving module, a resistance detection module and a reference resistor; the current mirror module is connected to the resistance detection module to provide a stable voltage for the resistance detection module; the resistance detection module is connected to the reference resistor and the first end of the measured resistor, and is used to detect the resistance value of the measured resistor according to the resistance value of the reference resistor; the driving module is connected to the reference resistor and the first end of the measured resistor, the second end of the measured resistor is grounded, and the driving module provides current for the reference resistor and the measured resistor; the second end of the reference resistor is grounded to provide the resistance value of the reference resistor to the resistance detection module.

[0009] In a possible implementation, the resistance detection module includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and an inverter; the gate of the first PMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube are connected to the current mirror module; the source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to the working voltage; the drain of the first NMOS tube is connected to the gate of the first NMOS tube, the gate of the second NMOS tube and the drain of the first PMOS tube, and the source of the first NMOS tube is connected to the first end of the reference resistor; the drain of the second NMOS tube is connected to the drain of the second PMOS tube and the gate of the third NMOS tube, the source of the second NMOS tube is connected to the first end of the measured resistor, and the second end of the measured resistor is grounded; the drain of the third NMOS tube is connected to the drain of the third PMOS tube and the input end of the inverter, and the source of the third NMOS tube is grounded.

[0010] In a possible implementation, the on-voltage of the third NMOS tube is equal to the drain voltage of the second NMOS tube when the resistance detection module is at a DC operating point.

[0011] In a possible implementation, the driving module includes a first port and a second port, the first port outputs a first current, the second port outputs a second current, the first current is N times the second current, and N is a positive number; the first end of the measured resistor is connected to the first port of the driving module, the reference resistor is connected to the second port of the driving module, and the resistance of the reference resistor is A; the resistance detection module is specifically used to, when the resistance value of the measured resistor is greater than or equal to A / N, the inverter outputs a high level, and when the resistance value of the measured resistor is less than A / N, the inverter outputs a low level.

[0012] In a possible implementation manner, the first PMOS transistor and the second PMOS transistor have the same size.

[0013] In a possible implementation, the current mirror module includes a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a third resistor and an output end; the source of the fourth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube, the drain of the fifth PMOS tube, and the drain of the fifth NMOS tube, and the drain of the fourth PMOS tube is connected to the first end of the third resistor and the gate of the fourth NMOS tube; the second end of the third resistor is connected to the drain of the fourth NMOS tube and the gate of the fifth NMOS tube, and the source of the fourth NMOS tube is connected to the source of the fifth NMOS tube; the output end is connected to the fifth PMOS tube and the fifth NMOS tube, and is also connected to the resistance detection module.

[0014] The present application provides a high-precision resistance detection circuit, including a current mirror module, a driving module, a resistance detection module, and a reference resistor; the current mirror module is connected to the resistance detection module, and is used to provide a stable voltage for the resistance detection module; the driving module is connected to the reference resistor and the first end of the measured resistor, and is used to provide current for the reference resistor and the measured resistor; the first end of the reference resistor is also connected to the resistance detection module, and the second end is grounded, and is used to provide the resistance value of the reference resistor to the resistance detection module; the resistance detection module is used to detect the resistance value of the measured resistor according to the resistance value of the reference resistor. The high-precision resistance detection circuit provided by the present application can perform real-time resistance detection, and has the advantages of high precision, simple structure, high cost-effectiveness and strong reliability.

[0015] In a second embodiment, an embodiment of the present application provides a chip, wherein the chip includes the high-precision resistance detection circuit provided by the first embodiment.

[0016] A third solution, an embodiment of the present application provides an electronic device, which includes the chip provided by the second solution, or includes the high-precision resistance detection circuit provided by the first solution.

[0017] It can be understood that the beneficial effects of the second and third schemes mentioned above can be found in the relevant description of the first scheme mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] in:

[0020] Figure 1A schematic diagram of the module structure of the high-precision resistance detection circuit provided in this application;

[0021] Figure 2 A schematic diagram of the structure of another high-precision resistance detection circuit provided by the present application;

[0022] Figure 3 This is a schematic diagram of the structure of the current mirror module provided in this application. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0024] It should be understood that the references to "one embodiment" or "some embodiments" throughout the specification mean that specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0025] Example 1

[0026] The embodiment of the present application provides a high-precision resistance detection circuit, which belongs to the field of integrated circuits, can detect resistance changes in real time, has a simple circuit structure, low cost, and high detection accuracy.

[0027] See also Figure 1 , Figure 1 The module structure diagram of a high-precision resistance detection circuit provided by the present application is shown in FIG. Figure 1 As shown, the high-precision resistance detection circuit provided by the present application includes a current mirror module 10, a driving module 30, a resistance detection module 20, and a reference resistor 40; the current mirror module 10 is connected to the resistance detection module 20, and is used to provide a stable voltage for the resistance detection module 20; the driving module 30 is connected to the reference resistor 40 and the first end of the measured resistor 50, and is used to provide current for the reference resistor 40 and the measured resistor 50; the first end of the reference resistor 40 is also connected to the resistance detection module 20, and the second end is grounded, and is used to provide the resistance value of the reference resistor 40 to the resistance detection module 20; the resistance detection module 20 is used to detect the resistance value of the measured resistor 50 according to the resistance value of the reference resistor 40.

[0028] In this embodiment, the current mirror module 10 provides a stable voltage to the resistance detection module 20, the driving module 30 provides current to the reference resistor 40 and the measured resistor 50, the reference resistor 40 provides the resistance value of the reference resistor 40 to the resistance detection module 20, the resistance value of the reference resistor 40 is fixed, and the resistance detection module 20 can detect the resistance value of the measured resistor 50 according to the resistance value of the reference resistor 40.

[0029] In some embodiments, see Figure 2 The resistance detection module 20 includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3 and an inverter INV; the gate of the first PMOS tube MP1, the gate of the second PMOS tube MP2 and the gate of the third PMOS tube MP3 are connected to the current mirror module; the source of the first PMOS tube MP1, the source of the second PMOS tube MP2 and the source of the third PMOS tube MP3 are connected to the working voltage; the drain of the first NMOS tube MN1 and the drain of the first NMOS tube MN2 are connected to the drain of the first NMOS tube MN3. The gate of the first NMOS tube MN1, the gate of the second NMOS tube MN2 and the drain of the first PMOS tube MP1 are connected, and the source of the first NMOS tube MN1 is connected to the first end of the reference resistor 40; the drain of the second NMOS tube MN2 is connected to the drain of the second PMOS tube MP2 and the gate of the third NMOS tube MN3, the source of the second NMOS tube MN2 is connected to the first end of the measured resistor 50, and the second end of the measured resistor 50 is grounded; the drain of the third NMOS tube MN3 is connected to the drain of the third PMOS tube MP3 and the input end of the inverter INV, and the source of the third NMOS tube MN3 is grounded.

[0030] The source of the second NMOS tube is connected to the first end of the measured resistor 50. When the resistance of the measured resistor 50 changes, the source voltage of the second NMOS tube MN2 also changes accordingly, thereby causing the drain voltage of the second NMOS tube MN2 to change. The drain of the second NMOS tube MN2 is connected to the gate of the third NMOS tube MN3. When the drain voltage of the second NMOS tube MN2 changes to be higher than or lower than the turn-on voltage of the third NMOS tube MN3, the third NMOS tube MN3 is turned on or off, thereby affecting the input voltage of the inverter INV. The inverter INV outputs a low level or a high level. Since the first NMOS tube MN1 and the second NMOS tube MN2 are combined into a current mirror module, at the DC operating point, the drain voltage and source voltage of the first NMOS tube MN1 are equal to the drain voltage of the second NMOS tube MN2. Therefore, the resistance value of the measured resistor 50 when the gate of the third NMOS tube is at the threshold voltage point can be obtained by the resistance value of the reference resistor 40.

[0031] In some embodiments, the turn-on voltage of the third NMOS transistor MN3 is equal to the drain voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2 when they are at a DC operating point.

[0032] In this embodiment, the size (ie, aspect ratio) of the third NMOS transistor MN3 can be adjusted so that the on-voltage of MN3 is equal to the drain voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2 when they are at a DC operating point.

[0033] In some embodiments, the driving module 30 includes a first port 301 and a second port 302, the first port 301 outputs a first current, the second port 302 outputs a second current, the first current is N times the second current, and N is a positive number; the first end of the measured resistor 50 is connected to the first port 301 of the driving module 30, the reference resistor 40 is connected to the second port 302 of the driving module 30, and the resistance of the reference resistor 40 is A; the resistance detection module 20 is specifically used for, when the resistance value of the measured resistor 50 is greater than or equal to A / N, the inverter INV outputs a high level, and when the resistance value of the measured resistor 50 is less than A / N, the inverter INV outputs a low level.

[0034] In this embodiment, the drain of the first NMOS tube MN1 is connected to the gate, and then connected to the gate of the second NMOS tube MN2. The first NMOS tube MN1 and the second NMOS tube MN2 are combined into a current mirror module. According to the circuit working principle of the current mirror, at the DC operating point, the drain voltage of the first NMOS tube MN1 is equal to the drain voltage of the second NMOS tube MN2, and the source voltage of the first NMOS tube MN1 is equal to the source voltage of the second NMOS tube MN2.

[0035] Among them, V MN1_S =R1×(I0+I), V MN2_S =R2×[I0+(N×I)],V MN1_S is the source voltage value of the first NMOS tube MN1, V MN2_S is the source voltage value of the second NMOS transistor MN2, R1 is the resistance value of the reference resistor 40, R2 is the resistance value of the measured resistor 50, I0 is the current of the first PMOS transistor MP1 and the second PMOS transistor MP2, I is the current value of the second current, and N×I is the current value of the first current. When the first NMOS transistor MN1 and the second NMOS transistor MN2 are at the DC operating point, V MN1_S =V MN2_S, that is, R1×(I0+I)=R2×[I0+(N×I)]. The current I output by the driving module 30 can be set to be much larger than the current of the first PMOS tube MP1 and the second PMOS tube MP2, so as to reduce the influence of the current of the first PMOS tube MP1 and the second PMOS tube MP2 on the gate voltage of the first NMOS tube MN1 and the second NMOS tube MN2, that is, when I is much larger than I0, I0 can be ignored, that is, R1×I=R2×N×I, and R2=R1 / N. In summary, when the first NMOS tube MN1 and the second NMOS tube MN2 are at the DC operating point, the resistance of the measured resistor 50 is 1 / N times the resistance of the reference resistor 40.

[0036] When the resistance of the measured resistor 50 is equal to 1 / N times the resistance of the reference resistor 40, the first NMOS tube MN1 and the second NMOS tube MN2 are at a DC operating point. At this time, the drain voltages of the first NMOS tube MN1 and the second NMOS tube are equal and equal to the turn-on voltage of the third NMOS tube, and the drain of the third NMOS tube MN3 is connected to the drain of the third PMOS tube MP3 and the input end of the inverter INV. When the third NMOS tube MN3 is turned on, the input end of the inverter inputs a low level and the output end outputs a high level. When the third NMOS tube MN3 is turned off, the input end of the inverter inputs a high level and the output end outputs a low level. Therefore, when the resistance of the measured resistor 50 in this embodiment is lower than 1 / N times the resistance of the reference resistor 40 or higher than or equal to 1 / N times the resistance of the reference resistor 40, the inverter will output a corresponding signal.

[0037] More specifically, when the resistance of the measured resistor 50 decreases, that is, R2 decreases, the source voltage of the second NMOS tube MN2 decreases, and the gate voltage remains unchanged, that is, the gate-source voltage of the second NMOS tube MN2 increases, and the conductivity of the second NMOS tube MN2 is enhanced, so the drain voltage of the second NMOS tube MN2 decreases. When the resistance of the measured resistor 50 decreases to less than 1 / N times the resistance of the reference resistor 40, that is, the drain voltage of the second NMOS tube MN2 decreases to less than the turn-on voltage of the third NMOS tube MN3, the third NMOS tube MN3 is turned off, and the input terminal of the inverter INV inputs a high level and outputs a low level; when When the resistance of the measured resistor 50 increases, that is, R2 increases, the drain voltage of the second NMOS tube MN2 increases, and the gate voltage remains unchanged, that is, the gate-source voltage of the second NMOS tube MN2 decreases, and the conductivity of the second NMOS tube MN2 weakens, so the drain voltage of the second NMOS tube MN2 increases. When the resistance of the measured resistor 50 increases to be greater than or equal to 1 / N times the resistance of the reference resistor 40, that is, the drain voltage of the second NMOS tube MN2 increases to be greater than or equal to the turn-on voltage of the third NMOS tube MN3, the third NMOS tube MN3 is turned on, and the input end of the inverter INV inputs a low level and outputs a high level.

[0038] As an example, when R1=50Ω, N=100, R2=50 / 100=0.5Ω, that is, the theoretical value of the resistance of R2 corresponding to the inverter INVI3 flip voltage point is 0.5Ω. Under this condition, the simulation results of the measured resistance value corresponding to the inverter INV flip voltage point with different working voltages VDD are shown in Table 1:

[0039] Table 1

[0040]

[0041] As shown in Table 1, under different operating voltages (VDD=2.6~4.2V), the resistance value of the measured resistor corresponding to the inverter INV flip voltage point can be seen that the resistance value of the measured resistor does not change, and the deviation from the theoretical value of 0.5Ω is only 0.007Ω, which is less affected by the operating voltage, with high reliability and high accuracy.

[0042] As an example, the resistance value of the measured resistor corresponding to the inverter INV flip voltage point can also be adjusted by adjusting the resistance value of the reference resistor (N is 100) to meet more different detection requirements. As shown in Table 2:

[0043] Table 2

[0044]

[0045] As shown in Table 2, under different reference resistances (R1=50-90Ω), the resistance deviation of the measured resistor corresponding to the inverter INV flip voltage point is small and the accuracy is high.

[0046] This embodiment utilizes the characteristic that when the current mirror composed of the first NMOS tube MN1 and the second NMOS tube MN2 is at the DC working point, the source voltage of the first NMOS tube MN1 and the drain voltage of the second NMOS tube MN2 are equal, and the measured resistor 50 is detected by the resistance provided by the reference resistor 40. When the resistance of the measured resistor is greater than or equal to 1 / N times of the reference resistor, the inverter INV outputs a low level, and when the resistance of the measured resistor is less than 1 / N times of the reference resistor, the inverter INV outputs a high level. The resistance detection module provided in this embodiment can detect the change of the resistance of the measured resistor with high precision, and has the advantages of high precision, simple structure, high cost-effectiveness and strong reliability.

[0047] In some embodiments, the first PMOS transistor MP1 and the second PMOS transistor MP2 have the same size.

[0048] In this embodiment, by setting the sizes of the first PMOS transistor MP1 and the second PMOS transistor MP2 to be the same, the currents of the first PMOS transistor MP1 and the second PMOS transistor MP2 are the same, which not only improves the resistance detection accuracy, but also the first NMOS transistor MN1 and the second NMOS transistor MN2 can use the same size, thereby reducing the design complexity of the circuit.

[0049] Specifically, if the sizes of the first PMOS tube MP1 and the second PMOS tube MP2 are different, the current of the first PMOS tube MP1 and the current of the second PMOS tube MP2 are different, and the current of the first NMOS tube MN1 and the second NMOS tube MN2 are also different. According to the above, at the DC operating point, the drain voltage and the source voltage of the first NMOS tube MN1 and the second NMOS tube MN2 are the same, that is, the voltage drop from the drain to the source of the first NMOS tube MN1 and the second NMOS tube MN2 is the same, so the sizes of the first NMOS tube MN1 and the second NMOS tube MN2 are different. In summary, if the sizes of the first PMOS tube MP1 and the second PMOS tube MP2 are different, it is necessary to set the sizes of the first NMOS tube MN1 and the second NMOS tube MN2 according to the sizes of the first PMOS tube MP1 and the second PMOS tube MP2. Therefore, this embodiment reduces the design complexity and design cost of the circuit by setting the sizes of the first PMOS tube MP1 and the second PMOS tube MP2 to be the same.

[0050] In some embodiments, the current mirror module includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a third resistor and an output terminal 101; the source of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5, the gate of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5, the drain of the fifth PMOS transistor MP5 and the drain of the fifth NMOS transistor MN5, the drain of the fourth PMOS transistor MP4 is connected to the first end of the third resistor and the gate of the fourth NMOS transistor MN4; the second end of the third resistor is connected to the drain of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5, the source of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5; the output terminal 101 is connected to the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5, and is also connected to the resistance detection module 20.

[0051] In this embodiment, the current mirror module provides a stable voltage to the resistance detection module, so as to maintain the functional stability and performance consistency of the circuit.

[0052] Example 2

[0053] This embodiment also discloses a chip, including the high-precision resistance detection circuit provided in Embodiment 1. Therefore, it has all the above technical features and can achieve the same effect, so it will not be described in detail here.

[0054] Example 3

[0055] This embodiment also discloses an electronic product, including the high-precision resistance detection circuit provided in Embodiment 1 or the chip provided in Embodiment 2. Therefore, it has all the above technical features and can achieve the same effect, so it will not be repeated here.

[0056] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or terminal including the element.

[0057] Obviously, the above embodiments of the utility model are only examples for clearly explaining the utility model, and are not intended to limit the implementation methods of the utility model. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. It is not necessary and impossible to list all the implementation methods here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the utility model should be included in the protection scope of the claims of the utility model.

Claims

1. A high-precision resistance detection circuit, characterized in that: It includes a current mirror module, a driving module, a resistance detection module and a reference resistor; The current mirror module is connected to the resistance detection module to provide a stable voltage for the resistance detection module; The resistance detection module is connected to the reference resistor and the first end of the resistor to be measured, and is used to detect the resistance value of the resistor to be measured according to the resistance value of the reference resistor; The driving module is connected to the first end of the reference resistor and the resistor to be measured, the second end of the resistor to be measured is grounded, and the driving module provides current for the reference resistor and the resistor to be measured; The second end of the reference resistor is grounded to provide the resistance value of the reference resistor to the resistance detection module.

2. The high-precision resistance detection circuit according to claim 1, characterized in that: The resistance detection module includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and an inverter; The gate of the first PMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube are connected to the current mirror module; The source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to the operating voltage; The drain of the first NMOS tube is connected to the gate of the first NMOS tube, the gate of the second NMOS tube and the drain of the first PMOS tube, and the source of the first NMOS tube is connected to the first end of the reference resistor; The drain of the second NMOS tube is connected to the drain of the second PMOS tube and the gate of the third NMOS tube, and the source of the second NMOS tube is connected to the first end of the measured resistor; The drain of the third NMOS tube is connected to the drain of the third PMOS tube and the input end of the inverter, and the source of the third NMOS tube is grounded.

3. The high-precision resistance detection circuit according to claim 2, characterized in that: The on-state voltage of the third NMOS tube is equal to the drain voltage of the second NMOS tube when the first NMOS tube and the second NMOS tube are at a DC operating point.

4. The high-precision resistance detection circuit according to claim 3, characterized in that: The driving module comprises a first port and a second port, the first port outputs a first current, the second port outputs a second current, the first current is N times the second current, and N is a positive number; The first end of the measured resistor is connected to the first port of the driving module, the reference resistor is connected to the second port of the driving module, and the resistance value of the reference resistor is A; The resistance detection module is specifically configured to: when the resistance value of the measured resistor is greater than or equal to A / N, the inverter outputs a high level; when the resistance value of the measured resistor is less than A / N, the inverter outputs a low level.

5. The high-precision resistance detection circuit according to claim 1, characterized in that: The current mirror module includes a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a third resistor and an output end; The source of the fourth PMOS tube is connected to the source of the fifth PMOS tube and the working voltage, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube, the drain of the fifth PMOS tube, and the drain of the fifth NMOS tube, and the drain of the fourth PMOS tube is connected to the first end of the third resistor and the gate of the fourth NMOS tube; The second end of the third resistor is connected to the drain of the fourth NMOS tube and the gate of the fifth NMOS tube, and the source of the fourth NMOS tube is connected to the source of the fifth NMOS tube and ground; The output end is connected to the fifth PMOS tube and the fifth NMOS tube, and is also connected to the resistance detection module.

6. A chip, characterized in that: The chip comprises the high-precision resistance detection circuit according to any one of claims 1 to 5.

7. An electronic device, characterized in that: The electronic device comprises the chip according to claim 6, or comprises the high-precision resistance detection circuit according to any one of claims 1-5.

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