Circuit for collecting plurality of AD signals through one GPIO (General Purpose Input / Output) port

Abstract

The utility model discloses a circuit for collecting a plurality of AD signals through a GPIO port, which comprises a divider resistor R62, a capacitor C128, a capacitor C129 and a plurality of AD collection circuits connected in parallel, each AD collection circuit comprises a voltage division circuit and a switching circuit which are connected in sequence, low-frequency interference of input voltage is filtered out through the capacitor C128, and the voltage division circuit is connected with the switching circuit through the capacitor C129. High-frequency interference is filtered out through a capacitor C129 and then sent to a voltage division circuit of each AD acquisition circuit, voltage signals are adjusted to a proper voltage range through the voltage division circuit and then output to a switching circuit, the switching circuit comprises a switching element, and the output end of the switching circuit is used for being connected with an I / O port of a single-chip microcomputer. Independent connection and disconnection of corresponding channels of each AD acquisition circuit are controlled; when GPIO ports are insufficient, the single-chip microcomputer does not need to be replaced, a schematic diagram of a product and a PCB are prevented from being greatly modified, redevelopment time is saved, cost rise is avoided, the requirement for the number of external pins is effectively reduced, and cost reduction is achieved.

Description

Technical Field

[0001] The utility model relates to the field of AD acquisition, in particular to a circuit for acquiring multiple AD signals through a GPIO port. Background Art

[0002] In recent years, most products require the design of protection circuits, such as overcurrent protection, overtemperature protection, etc., so it is necessary to collect current signals and temperature signals. Generally, these signals are converted into voltage signals, and the voltage is used to reflect the changes in current or temperature. At present, most AD acquisition circuits on the market basically adopt a one-to-one method, that is, one acquisition circuit corresponds to one GPIO port. In this way, the microcontroller needs to have enough GPIO ports. However, based on different circuit designs and microcontroller selection, it is inevitable to encounter too many acquisition parameters and insufficient GPIO ports during the application process, especially when improving product performance or expanding functions. At this time, if the microcontroller is replaced, the product solution will be greatly changed. First, it takes a lot of time to re-learn the microcontroller and greatly change the product hardware schematic and PCB. Second, it is bound to increase the product hardware cost; so in this case, it is particularly important to design an acquisition circuit without changing the microcontroller, a circuit that can collect multiple AD signals through the same GPIO port, and has low cost and simple structure. Utility Model Content

[0003] The purpose of the utility model is to provide a circuit for collecting multiple AD signals through a GPIO port, so as to solve the technical problem that the traditional AD collection circuit adopts a one-to-one mode and one collection circuit can only correspond to one GPIO port. Therefore, when it is found that the GPIO port is insufficient during the development process, there is no need to replace the single-chip microcomputer, which reduces the hardware cost and saves the learning time of technical personnel. The circuit structure is simple and the cost is low.

[0004] In order to solve the above problems, the utility model adopts the following technical solutions:

[0005] A circuit for collecting multiple AD signals through a GPIO port, comprising a voltage-dividing resistor R62, a capacitor C128, a capacitor C129, and multiple parallel AD acquisition circuits, each AD acquisition circuit comprising a voltage-dividing circuit and a switch circuit connected in sequence, one end of the voltage-dividing resistor R62 is connected to a power supply, the other end of the voltage-dividing resistor R62 is connected to the voltage-dividing circuits of multiple AD acquisition circuits, one end of the capacitor C128 is connected to the power supply and the other end is grounded, one end of the capacitor C129 is connected to the other end of the voltage-dividing resistor R62, and the other end of the capacitor C129 is grounded;

[0006] The input voltage is first filtered out by capacitor C128 to remove low-frequency interference, and then filtered out by capacitor C129 to remove high-frequency interference before being sent to the voltage divider circuit of each AD acquisition circuit. The voltage divider circuit adjusts the voltage signal to a suitable voltage range before outputting it to the switch circuit.

[0007] The switch circuit includes a switch element, and the output end of the switch circuit is used to connect to the I / O port of the single-chip microcomputer to control the independent connection and disconnection of the corresponding channel of each AD acquisition circuit.

[0008] Furthermore, the voltage divider circuit of each AD acquisition circuit includes a thermistor NTC and a bypass capacitor C connected in parallel, one end of the thermistor NTC is connected to the voltage divider resistor R62, and the other end of the thermistor NTC serves as the output end of the voltage divider circuit.

[0009] Furthermore, the switch element of the switch circuit adopts an N-channel MOS tube Q, and the switch circuit of each AD acquisition circuit also includes two resistors R. The drain of the N-channel MOS tube Q is connected to the output end of the voltage divider circuit, a resistor R is connected in parallel between the gate and source of the N-channel MOS tube Q and grounded, and one end of the other resistor R is connected to the gate of the N-channel MOS tube Q, and the other end is used as the output end of the switch circuit to connect to the I / O port of the single-chip computer.

[0010] Furthermore, the model of the N-channel MOS tube Q is 2N7002.

[0011] Furthermore, the capacitance of capacitor C128 is 1uF, and the capacitance of capacitor C129 is 100nF.

[0012] Compared with the prior art, the beneficial effects of the utility model are:

[0013] 1. The utility model adds capacitor C128 to the voltage input end to filter out low-frequency interference of the input voltage and improve the load-carrying capacity of the circuit to prevent the input voltage from being unstable when the load changes suddenly. The input voltage passes through the voltage-dividing resistor R62 and then through the capacitor C129 to filter out high-frequency interference. By filtering out low-frequency and high-frequency interference, the voltage of the acquisition circuit can be kept stable and not affected by power supply voltage fluctuations and external interference.

[0014] 2. The external interface GPIO usually requires hardware support, such as pins, connectors, etc. The utility model can effectively reduce the number of external pins without reducing product performance. Selecting a connector with fewer pins can simplify the external interface circuit, thereby reducing costs. The utility model is low-cost and simple in structure.

[0015] 3. The utility model connects multiple acquisition circuits in parallel and adopts a resistor voltage division method. The voltage division circuit includes a thermistor, and a MOS tube is connected in series at the rear end of each thermistor to control the on-off of the circuit. The MOS tube is driven on and off by the single-chip microcomputer in a cycle. When the product function is expanded or the performance is improved, if the number of GPIO ports of the single-chip microcomputer is insufficient, the utility model can be used to collect AD acquisition circuits through the same GPIO port, without replacing the single-chip microcomputer, avoiding major modifications to the product schematic and PCB, saving redevelopment time, and avoiding cost increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Shown is a specific circuit diagram of the utility model. DETAILED DESCRIPTION

[0017] To make the content of the utility model clearer, the specific implementation of the utility model is further described in detail below in conjunction with the accompanying drawings. It should be noted that for the purpose of clarity, the representation and description of components that are not related to the utility model and are known to ordinary technicians in the field are omitted in the drawings and descriptions.

[0018] refer to Figure 1 , this embodiment includes a voltage-dividing resistor R62, a capacitor C128, a capacitor C129 and four parallel AD acquisition circuits, each AD acquisition circuit includes a voltage-dividing circuit and a switch circuit connected in sequence, one end of the voltage-dividing resistor R62 is connected to a power supply, the other end of the voltage-dividing resistor R62 is connected to the voltage-dividing circuits of multiple AD acquisition circuits, one end of the capacitor C128 is connected to the power supply and the other end is grounded, one end of the capacitor C129 is connected to the other end of the voltage-dividing resistor R62, and the other end of the capacitor C129 is grounded, wherein the voltage-dividing resistor R62 is 10kΩ, the capacitance of the capacitor C128 is 1uF, and the capacitance of the capacitor C129 is 100nF. The input voltage first passes through capacitor C128 to filter out low-frequency interference and flows to voltage-dividing resistor R62, and then passes through capacitor C129 to filter out high-frequency interference and is sent to the voltage-dividing circuit of each AD acquisition circuit. The voltage signal is adjusted to a suitable voltage range by the voltage-dividing circuit and then output to the switching circuit; the switching circuit includes a switching element, specifically, the switching element adopts an N-channel MOS tube, and the output end of the switching circuit is used to connect to the I / O port of the single-chip computer to control the independent connection and disconnection of the corresponding channel of each AD acquisition circuit.

[0019] AD acquisition circuit 1:

[0020] The voltage divider circuit 1 includes a thermistor NTC2 and a bypass capacitor C131 connected in parallel, one end of the thermistor NTC2 is connected to a resistor R62 and the other end is connected to a switch circuit;

[0021] The switch circuit 1 includes an N-channel MOS transistor Q22, resistors R102 and R103, a thermistor NTC2 and a bypass capacitor C131 are connected to the drain of the N-channel MOS transistor Q22, a resistor R102 is connected in parallel between the gate and source of the N-channel MOS transistor Q22 and grounded, one end of the resistor R103 is connected to the gate of the N-channel MOS transistor Q22, and the other end of the resistor R103 is connected to the I / O port 1 of the single-chip computer.

[0022] AD acquisition circuit 2:

[0023] The voltage divider circuit 2 includes a thermistor NTC3 and a bypass capacitor C130 connected in parallel, one end of the thermistor NTC3 is connected to the resistor R62 and the other end is connected to the switch circuit;

[0024] The switch circuit 2 includes an N-channel MOS transistor Q23, resistors R104 and R105, the thermistor NTC3 and the bypass capacitor C130 are connected to the drain of the N-channel MOS transistor Q23, the resistor R104 is connected in parallel between the gate and the source of the N-channel MOS transistor Q23 and is grounded, one end of the resistor R105 is connected to the gate of the N-channel MOS transistor Q, and the other end of the resistor R105 is connected to the I / O port 2 of the single-chip computer.

[0025] AD acquisition circuit 3:

[0026] The voltage divider circuit 3 includes a thermistor NTC4 and a bypass capacitor C132 connected in parallel, one end of the thermistor NTC4 is connected to the resistor R62 and the other end is connected to the switch circuit;

[0027] The switch circuit 3 includes an N-channel MOS transistor Q24, resistors R106 and R108, the thermistor NTC4 and the bypass capacitor C132 are connected to the drain of the N-channel MOS transistor Q24, the resistor R106 is connected in parallel between the gate and the source of the N-channel MOS transistor Q24 and is grounded, one end of the resistor R108 is connected to the gate of the N-channel MOS transistor Q24, and the other end of the resistor R108 is connected to the I / O port 3 of the single-chip computer.

[0028] AD acquisition circuit 4:

[0029] The voltage divider circuit 4 includes a thermistor NTC5 and a bypass capacitor C133 connected in parallel, one end of the thermistor NTC5 is connected to the resistor R62 and the other end is connected to the switch circuit;

[0030] The switch circuit 4 includes an N-channel MOS transistor Q25, resistors R107 and R109, the thermistor NTC5 and the bypass capacitor C133 are connected to the drain of the N-channel MOS transistor Q25, the resistor R107 is connected in parallel between the gate and the source of the N-channel MOS transistor Q25 and is grounded, one end of the resistor R109 is connected to the gate of the N-channel MOS transistor Q25, and the other end of the resistor R109 is connected to the I / O port 4 of the single-chip computer.

[0031] Among them, the bypass capacitors C130, C131, C132 and C133 are 100nF, the thermistors NTC2, NTC3, NTC4 and NTC5 are 10kΩ; the N-channel MOS tube model is 2N7002; the resistors R102, R104, R106 and R107 are 10kΩ, and the resistors R103, R105, R108 and R109 are 2.2kΩ.

[0032] In this embodiment, a capacitor C128 is added to the voltage input end to filter out low-frequency interference of the input voltage and improve the load-carrying capacity of the circuit to prevent input voltage instability caused by a sudden load change. The input voltage passes through the voltage-dividing resistor R62 and then through the capacitor C129 to filter out high-frequency interference. The two capacitors are provided to filter out low-frequency and high-frequency interference, so that the voltage of the acquisition circuit can be kept stable and not affected by power supply voltage fluctuations and external interference. The thermistor is connected in parallel with a capacitor with a small capacitance value, which can effectively filter out high-frequency interference and prevent external interference from causing adverse effects on the microcontroller acquisition signal.

[0033] It should be noted that the switch element in this embodiment is an N-channel MOS tube, and other components such as IGBT etc. may also be used in practical applications.

[0034] The working principle of this embodiment is specifically applied to the BS9118AM64 single-chip microcomputer produced by BYD Semiconductor Co., Ltd. In the application, the four analog signal input ports (U_PCBA_TEMP_CTR, MCU_COIL1_TEMP_CTR, MCU_COIL2_TEMP_CTR, MCU_COIL3_TEMP_CTR) are respectively connected to the four IO input pins of the single-chip microcomputer, that is, the single-chip microcomputer BS9118AM64 controls the on-off of MOS tubes Q22, Q23, Q24 and Q25 through these four IO ports, thereby activating the circuits where NTC2, NTC3, NTC4 and NTC5 are located, and connects the common end (MCU_TEMP_SNS_AI) to the GPIO port of the single-chip microcomputer. The common end is a node for connecting the input ends of multiple parallel AD acquisition circuits. The voltage signal of the common end is collected in sequence according to the conduction sequence and time period of the MOS tubes Q22, Q23, Q24 and Q25, thereby realizing the function of collecting multiple AD signals through the same GPIO port.

[0035] The number of parallel acquisition circuits listed in this embodiment is 4. In actual applications, the number of parallel acquisition circuits can be increased according to demand. After testing and certification, the utility model can connect at least 10 acquisition circuits in parallel. The utility model forms a circuit with low-cost resistors, capacitors and MOS tubes. The MOS tube controls the on and off of a separate acquisition channel. The MOS tube is driven on and off by a single-chip microcomputer in a cycle to realize the function of collecting multiple AD signals through the same GPIO port. There is no need to replace the single-chip microcomputer, thereby avoiding an increase in development costs. In addition, the utility model can effectively reduce the number of external pins without reducing product performance. By selecting a connector with fewer pins, the external interface circuit can be simplified, thereby reducing costs.

Claims

1. A circuit for collecting multiple AD signals through a GPIO port, characterized in that: It includes a voltage-dividing resistor R62, a capacitor C128, a capacitor C129, and a plurality of AD acquisition circuits connected in parallel, each AD acquisition circuit includes a voltage-dividing circuit and a switch circuit connected in sequence, one end of the voltage-dividing resistor R62 is connected to a power supply, the other end of the voltage-dividing resistor R62 is connected to the voltage-dividing circuits of the plurality of AD acquisition circuits, one end of the capacitor C128 is connected to the power supply and the other end is grounded, one end of the capacitor C129 is connected to the other end of the voltage-dividing resistor R62, and the other end of the capacitor C129 is grounded; The input voltage is first filtered out by capacitor C128 to remove low-frequency interference, and then filtered out by capacitor C129 to remove high-frequency interference before being sent to the voltage divider circuit of each AD acquisition circuit. The voltage divider circuit adjusts the voltage signal to a suitable voltage range before outputting it to the switch circuit. The switch circuit includes a switch element, and the output end of the switch circuit is used to connect to the I / O port of the single-chip microcomputer to control the independent connection and disconnection of the corresponding channel of each AD acquisition circuit.

2. The circuit for collecting multiple AD signals through one GPIO port according to claim 1, characterized in that: The voltage divider circuit of each AD acquisition circuit includes a thermistor NTC and a bypass capacitor C connected in parallel, one end of the thermistor NTC is connected to the voltage divider resistor R62, and the other end of the thermistor NTC serves as the output end of the voltage divider circuit.

3. The circuit for collecting multiple AD signals through one GPIO port according to claim 2, characterized in that: The switch element of the switch circuit adopts an N-channel MOS tube Q. The switch circuit of each AD acquisition circuit also includes two resistors R. The drain of the N-channel MOS tube Q is connected to the output end of the voltage divider circuit. A resistor R is connected in parallel between the gate and source of the N-channel MOS tube Q and grounded. One end of the other resistor R is connected to the gate of the N-channel MOS tube Q, and the other end is used as the output end of the switch circuit to connect to the I / O port of the microcontroller.

4. The circuit for collecting multiple AD signals through one GPIO port according to claim 3, characterized in that: The model used by N-channel MOS tube Q is 2N7002.

5. The circuit for collecting multiple AD signals through one GPIO port according to claim 1, characterized in that: The capacitance of capacitor C128 is 1uF, and the capacitance of capacitor C129 is 100nF.

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