Electronic device

Abstract

An electronic device includes a plurality of integrated circuits, each including a power transistor connected between an input voltage node and a load node, and a regulation circuit that generates at least one sense current representative of an output current of the power transistor. The regulation circuit modulates an output current of its power transistor based on a value derived from a sense current generated by the regulation circuit of the other integrated circuit. This derived value can be based on one of an average value of the sense current generated by the adjustment circuit or the sense current. In particular, the integrated circuits can be arranged in a daisy chain relationship, allowing each regulation circuit to compare its sense current with the sense current from the immediately preceding circuit, but the first regulation circuit, except for the first regulation circuit, compares its sense current with the sense current of the last circuit in the chain.

Description

Technical Field

[0001] The present disclosure relates to the field of providing power to multiple power integrated circuits (ICs), and in particular, to circuits for balancing current supplied to multiple power ICs. Background Art

[0002] In electronic devices, powering multiple power integrated circuits (ICs) in parallel is a particularly interesting design aspect. Failure to balance the current supplied to these power ICs can lead to various problems such as overheating, voltage drop, reduced efficiency, and noise / interference.

[0003] When the supplied current is unbalanced, some power ICs receive excess current, causing them to overheat and potentially damage not only themselves but other components in the device. This ultimately shortens the life of the device. In addition, the lack of current balance can cause voltage drops in certain areas of the device, causing the device to malfunction. Noise and interference can also be generated due to current imbalance, further affecting the performance of the device and potentially causing errors.

[0004] The above will now be explained in more detail. Figure 1 , an electronic device 10 is shown including a first power IC 11, the first power IC 11 having a first controller 12 driving a gate of a power MOS MN1 connected between an input voltage Vin and a load (denoted as Rload), the first controller 12 driving the gate of the power MOS MN1 based on sensing an output current Iout1 of the first power IC 11 as feedback. Similarly, the electronic device 10 includes a second power IC 14, the second power IC 14 having a second controller 15 driving a gate of a power MOS MN2 also connected between the input voltage Vin and the load, the second controller 15 driving the gate of the power MOS MN2 based on sensing an output current Iout2 of the second power IC 14 as feedback.

[0005] The electrical characteristics between the power ICs 11 and 14 may not match. Therefore, the gate voltages applied to the power MOS MN1 and MN2 are not equal when compared to each other and actually have different offsets Voffset1 and Voffset2 applied thereto (represented as voltage sources in the figure). Due to these different voltage offsets Voffset1 and Voffset2, the output currents Iout1 and Iout2 are not equal.

[0006] First consider the effect when the power MOS MN1 and MN2 operate in linear mode. In linear mode, the power MOS MN1 and MN2 act as variable resistors. When one of the power MOS MN1 and MN2 begins to conduct more current than the other, it will consume more power, causing it to heat up. When the MOSFET heats up when operating in linear mode, its on-resistance increases. However, according to Ohm's law, the current I through the resistor is proportional to the voltage V across the resistor and inversely proportional to the resistance R of the resistor (for example, I=V / R), which means that as the resistance of the resistor increases, the current through the resistor decreases. This effectively self-limits the results of current mismatch.

[0007] However, now consider the impact when the power MOS MN1 and MN2 are operated in saturation mode. In saturation mode, the power MOS MN1 and MN2 act as voltage-controlled current sources. Therefore, the different voltage offsets Voffset1 and Voffset2 (caused by the mismatched electrical characteristics described above) cause the output currents Iout1 and Iout2 to not match. When one of the power MOS MN1 and MN2 begins to conduct more current than the other, it will consume more power, causing it to heat up. When operating in a saturated state, if the gate-to-source voltage is operated with a positive temperature coefficient relative to temperature, the heating of the MOS will increase the current through the MOS. This in turn will cause the MOS to heat up further and conduct even more current, resulting in a positive feedback loop, which can lead to thermal runaway and ultimately failure of the MOS. Utility Model Content

[0008] Current balancing schemes need to be developed to provide safe and correct operation for multiple parallel-connected power ICs when they are expected to operate in saturation mode for a period of time.

[0009] One aspect of the present disclosure provides an electronic device, comprising: an input voltage node and a load node; a first integrated circuit, comprising: a first power transistor, connected between the input voltage node and the load node; and a first regulation circuit, configured to generate a first sensing current and a second sensing current representing an output current of the first power transistor; and a second integrated circuit, comprising: a second power transistor, connected between the input voltage node and the load node; and a second regulation circuit, configured to generate a third sensing current and a fourth sensing current representing an output current of the second power transistor; wherein the first regulation circuit is configured to cause the first power transistor to reduce its output current when the first sensing current is greater than an average value of the second sensing current and the fourth sensing current; wherein the first regulation circuit is configured to cause the first power transistor to increase its output current when the first sensing current is less than an average value of the second sensing current and the fourth sensing current; wherein the second regulation circuit is configured to cause the second power transistor to reduce its output current when the third sensing current is greater than an average value of the second sensing current and the fourth sensing current; and wherein the second regulation circuit is configured to cause the second power transistor to increase its output current when the third sensing current is less than an average value of the second sensing current and the fourth sensing current.

[0010] In some embodiments of the present disclosure, the electronic device also includes: a first resistor, located outside the first integrated circuit and the second integrated circuit and coupled to receive a first sensing current, so that a first voltage formed across the first resistor represents an output current of the first power transistor; a second resistor, located outside the first integrated circuit and the second integrated circuit and coupled to receive a third sensing current, so that a second voltage formed across the second resistor represents the output current of the second power transistor; and a third resistor, located outside the first integrated circuit and the second integrated circuit and coupled to receive the second sensing current and a fourth sensing current, so that a third voltage formed across the third resistor represents an average value of the output currents of the first power transistor and the second power transistor.

[0011] In some embodiments of the present disclosure, the first regulation circuit includes: a first amplifier, whose input terminal is coupled to receive a first voltage and a third voltage, the first amplifier being configured to source current to its output terminal when the first voltage is greater than the third voltage, and to sink current from its output terminal when the first voltage is less than the third voltage; and a second amplifier, whose input terminal is coupled to receive a soft start voltage and a voltage generated at the output terminal of the first amplifier, wherein the output terminal of the second amplifier is coupled to drive a control terminal of the first power transistor; and wherein the second regulation circuit includes: a third amplifier, whose input terminal is coupled to receive the second voltage and the third voltage, the third amplifier being configured to source current to its output terminal when the second voltage is greater than the third voltage, and to sink current from its output terminal when the second voltage is less than the third voltage; and a fourth amplifier, whose input terminal is coupled to receive the soft start voltage and the voltage generated at the output terminal of the third amplifier, wherein the output terminal of the fourth amplifier is coupled to drive the control terminal of the second power transistor.

[0012] In some embodiments of the present disclosure, the first regulation circuit also includes a first resistor ladder coupled between the output terminal of the second amplifier and a reference voltage, wherein a tap of the first resistor ladder is coupled to the output terminal of the first amplifier; and the second regulation circuit also includes a second resistor ladder coupled between the output terminal of the fourth amplifier and the reference voltage, wherein a tap of the second resistor ladder is coupled to the output terminal of the third amplifier.

[0013] In some embodiments of the present disclosure, the first regulation circuit also includes a first resistor ladder coupled between the output terminal of the first power transistor and a reference voltage, wherein a tap of the first resistor ladder is coupled to the output terminal of the first amplifier; and the second regulation circuit also includes a second resistor ladder coupled between the output terminal of the second power transistor and the reference voltage, wherein a tap of the second resistor ladder is coupled to the output terminal of the third amplifier.

[0014] In some embodiments of the present disclosure, a control terminal of a first power transistor is coupled to a first soft start voltage and a control terminal of a second power transistor is coupled to a second soft start voltage; a first regulation circuit includes a first amplifier whose input terminal is coupled to receive a first voltage and a third voltage, the first amplifier being configured to sink current from its output terminal when the first voltage is greater than the third voltage, and to source current to its output terminal when the first voltage is less than the third voltage, wherein the output terminal of the first amplifier is coupled to drive the control terminal of the first power transistor; and a second regulation circuit includes a second amplifier whose input terminal is coupled to receive a second voltage and a third voltage, the second amplifier being configured to sink current from its output terminal when the second voltage is greater than the third voltage, and to source current to its output terminal when the second voltage is less than the third voltage, wherein the output terminal of the second amplifier is coupled to drive the control terminal of the second power transistor.

[0015] In some embodiments of the present disclosure, the electronic device also includes: a first resistor, located in the first integrated circuit and coupled to receive a first sensing current, so that a first voltage formed across the first resistor represents the output current of the first power transistor; a second resistor, located in the first integrated circuit and coupled to receive a second sensing current; a third resistor, located in the second integrated circuit and coupled to receive a third sensing current, so that a second voltage formed across the second resistor represents the output current of the second power transistor; a fourth resistor, located in the second integrated circuit and coupled to receive a fourth sensing current; wherein the second resistor and the fourth resistor are coupled in parallel, so that the third voltage formed across the second resistor and the fourth resistor represents the average value of the output currents of the first power transistor and the second power transistor.

[0016] In some embodiments of the present disclosure, a first regulation circuit includes: a first amplifier, whose input terminal is coupled to receive a first voltage and a third voltage, the first amplifier being configured to source current to its output terminal when the first voltage is greater than the third voltage, and to sink current from its output terminal when the first voltage is less than the third voltage; and a second amplifier, whose input terminal is coupled to receive a soft start voltage and a voltage generated at an output terminal of the first amplifier, wherein the output terminal of the second amplifier is coupled to drive a control terminal of a first power transistor; and a second regulation circuit includes: a third amplifier, whose input terminal is coupled to receive a second voltage and a third voltage, the third amplifier being configured to source current to its output terminal when the second voltage is greater than the third voltage, and to sink current from its output terminal when the second voltage is less than the third voltage; and a fourth amplifier, whose input terminal is coupled to receive the soft start voltage and the voltage generated at the output terminal of the third amplifier, wherein the output terminal of the fourth amplifier is coupled to drive the control terminal of the second power transistor.

[0017] Another aspect of the present disclosure provides an electronic device, comprising: an input voltage node and a load node; a first integrated circuit, comprising: a first power transistor, connected between the input voltage node and the load node; and a first regulating circuit, configured to generate a first sensing current representing an output current of the first power transistor; and a second integrated circuit, comprising: a second power transistor, connected between the input voltage node and the load node; and a second regulating circuit, configured to generate a second sensing current representing an output current of the second power transistor; and a third integrated circuit, comprising: a third power transistor, connected between the input voltage node and the load node; and a third regulating circuit, configured to generate a third sensing current representing an output current of the third power transistor; wherein the first regulating circuit The circuit is configured to cause the first power transistor to reduce its output current when the first sensing current is greater than the third sensing current; wherein the first regulation circuit is configured to cause the first power transistor to increase its output current when the first sensing current is less than the third sensing current; wherein the second regulation circuit is configured to cause the second power transistor to reduce its output current when the second sensing current is greater than the first sensing current; wherein the second regulation circuit is configured to cause the second power transistor to increase its output current when the second sensing current is less than the first sensing current; wherein the third regulation circuit is configured to cause the third power transistor to reduce its output current when the third sensing current is greater than the second sensing current; and wherein the third regulation circuit is configured to cause the third power transistor to increase its output current when the third sensing current is less than the second sensing current.

[0018] In some embodiments of the present disclosure, a first resistor is located outside the first integrated circuit, the second integrated circuit, and the third integrated circuit and is coupled to receive a first sensing current, so that a first voltage formed across the first resistor represents an output current of the first power transistor; a second resistor is located outside the first integrated circuit, the second integrated circuit, and the third integrated circuit and is coupled to receive a second sensing current, so that a second voltage formed across the second resistor represents an output current of the second power transistor; and a third resistor is located outside the first integrated circuit, the second integrated circuit, and the third integrated circuit and is coupled to receive a third sensing current, so that a third voltage formed across the third resistor represents an output current of the third power transistor.

[0019] In some embodiments of the present disclosure, a first regulation circuit includes: a first amplifier, whose input terminal is coupled to receive a first voltage and a third voltage, the first amplifier being configured to source a current to its output terminal when the first voltage is greater than the third voltage, and to sink a current from its output terminal when the first voltage is less than the third voltage; and a second amplifier, whose input terminal is coupled to receive a soft start voltage and a voltage generated at an output terminal of the first amplifier, wherein an output terminal of the second amplifier is coupled to drive a control terminal of a first power transistor; and a second regulation circuit includes: a third amplifier, whose input terminal is coupled to receive a second voltage and the first voltage, the third amplifier being configured to source a current to its output terminal when the second voltage is greater than the first voltage, and to sink a current from its output terminal when the second voltage is less than the third voltage. The third amplifier comprises a first amplifier and a second amplifier, wherein the first amplifier is configured to receive the soft start voltage and the second voltage, the second amplifier is configured to sink current from its output terminal when the third voltage is greater than the second voltage, and sink current from its output terminal when the third voltage is less than the second voltage; and a fourth amplifier, whose input terminal is coupled to receive the soft start voltage and the voltage generated at the output terminal of the third amplifier, wherein the output terminal of the fourth amplifier is coupled to drive the control terminal of the second power transistor; the third regulation circuit comprises: a fifth amplifier, whose input terminal is coupled to receive the third voltage and the second voltage, the fifth amplifier being configured to source current to its output terminal when the third voltage is greater than the second voltage, and sink current from its output terminal when the third voltage is less than the second voltage; and a sixth amplifier, whose input terminal is coupled to receive the soft start voltage and the voltage generated at the output terminal of the fifth amplifier, wherein the output terminal of the fourth amplifier is coupled to drive the control terminal of the third power transistor.

[0020] In some embodiments of the present disclosure, the first regulation circuit also includes a first resistor ladder coupled between the output terminal of the second amplifier and a reference voltage, wherein a tap of the first resistor ladder is coupled to the output terminal of the first amplifier; the second regulation circuit also includes a second resistor ladder coupled between the output terminal of the fourth amplifier and the reference voltage, wherein a tap of the second resistor ladder is coupled to the output terminal of the third amplifier; and the third regulation circuit also includes a third resistor ladder coupled between the output terminal of the sixth amplifier and the reference voltage, wherein a tap of the third resistor ladder is coupled to the output terminal of the fifth amplifier.

[0021] In some embodiments of the present disclosure, the first regulation circuit also includes a first resistor ladder coupled between the output terminal of the first power transistor and a reference voltage, wherein a tap of the first resistor ladder is coupled to the output terminal of the first amplifier; the second regulation circuit also includes a second resistor ladder coupled between the output terminal of the second power transistor and the reference voltage, wherein a tap of the second resistor ladder is coupled to the output terminal of the third amplifier; and the third regulation circuit also includes a third resistor ladder coupled between the output terminal of the third power transistor and the reference voltage, wherein a tap of the third resistor ladder is coupled to the output terminal of the fifth amplifier.

[0022] In some embodiments of the present disclosure, a control terminal of a first power transistor is coupled to a first soft start voltage, a control terminal of a second power transistor is coupled to a second soft start voltage, and a control terminal of a third power transistor is coupled to a third soft start voltage; a first regulation circuit includes a first amplifier, an input terminal of which is coupled to receive a first voltage and a third voltage, the first amplifier being configured to sink current from an output terminal thereof when the first voltage is greater than the third voltage, and to source current to an output terminal thereof when the first voltage is less than the third voltage, wherein an output terminal of the first amplifier is coupled to drive a control terminal of the first power transistor; a second regulation circuit includes a second amplifier, an input terminal of which is coupled to receive a first voltage and a third voltage, A first amplifier is coupled to receive a second voltage and a first voltage, the second amplifier is configured to sink current from its output terminal when the second voltage is greater than the first voltage, and to source current to its output terminal when the second voltage is less than the first voltage, wherein the output terminal of the second amplifier is coupled to drive the control terminal of the second power transistor; and a third regulation circuit includes a third amplifier, whose input terminal is coupled to receive the third voltage and the second voltage, the third amplifier is configured to sink current from its output terminal when the third voltage is greater than the second voltage, and to source current to its output terminal when the third voltage is less than the second voltage, wherein the output terminal of the third amplifier is coupled to drive the control terminal of the third power transistor.

[0023] In some embodiments of the present disclosure, the electronic device also includes: a first resistor, located in the first integrated circuit and coupled to receive a first sensing current, so that a first voltage formed across the first resistor represents the output current of the first power transistor; a second resistor, located in the second integrated circuit and coupled to receive a second sensing current, so that a second voltage formed across the second resistor represents the output current of the second power transistor; and a third resistor, located in the third integrated circuit and coupled to receive a third sensing current, so that a third voltage formed across the third resistor represents the output current of the third power transistor.

[0024] In some embodiments of the present disclosure, a first regulation circuit includes: a first amplifier, whose input terminal is coupled to receive a first voltage and a third voltage, the first amplifier being configured to source a current to its output terminal when the first voltage is greater than the third voltage, and to sink a current from its output terminal when the first voltage is less than the third voltage; and a second amplifier, whose input terminal is coupled to receive a soft start voltage and a voltage generated at an output terminal of the first amplifier, wherein an output terminal of the second amplifier is coupled to drive a control terminal of a first power transistor; and a second regulation circuit includes: a third amplifier, whose input terminal is coupled to receive a second voltage and the first voltage, the third amplifier being configured to source a current to its output terminal when the second voltage is greater than the first voltage, and to sink a current from its output terminal when the second voltage is less than the third voltage. The third amplifier comprises a first amplifier and a second amplifier, wherein the first amplifier is configured to receive the soft start voltage and the second voltage, the second amplifier is configured to sink current from its output terminal when the third voltage is greater than the second voltage, and sink current from its output terminal when the third voltage is less than the second voltage; and a fourth amplifier, whose input terminal is coupled to receive the soft start voltage and the voltage generated at the output terminal of the third amplifier, wherein the output terminal of the fourth amplifier is coupled to drive the control terminal of the second power transistor; the third regulation circuit comprises: a fifth amplifier, whose input terminal is coupled to receive the third voltage and the second voltage, the fifth amplifier being configured to source current to its output terminal when the third voltage is greater than the second voltage, and sink current from its output terminal when the third voltage is less than the second voltage; and a sixth amplifier, whose input terminal is coupled to receive the soft start voltage and the voltage generated at the output terminal of the fifth amplifier, wherein the output terminal of the fourth amplifier is coupled to drive the control terminal of the third power transistor.

[0025] Yet another aspect of the present disclosure provides an electronic device, comprising: an input voltage node and a load node; and a plurality of integrated circuits, each integrated circuit comprising: a power transistor connected between the input voltage node and the load node; and a regulation circuit configured to generate at least one sensing current representing an output current of the power transistor; wherein each regulation circuit is configured to cause its corresponding power transistor to reduce its output current when the sensing current generated by it is greater than a value derived from at least one of the sensing currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits; wherein each regulation circuit is configured to cause its corresponding power transistor to increase its output current when the sensing current generated by it is less than a value derived from at least one of the sensing currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits.

[0026] In some embodiments of the present disclosure, a value derived from at least one of the sensing currents generated by the regulation circuits of other integrated circuits of the plurality of integrated circuits is based on an average value of the sensing currents generated by the regulation circuits of other integrated circuits of the plurality of integrated circuits.

[0027] In some embodiments of the present disclosure, a value derived from at least one of the sensing currents generated by regulation circuits of other integrated circuits of the plurality of integrated circuits is based on one of the sensing currents generated by one of the regulation circuits of other integrated circuits of the plurality of integrated circuits.

[0028] In some embodiments of the present disclosure, the multiple integrated circuits are arranged in a daisy-chain relationship, so that each regulation circuit except the regulation circuit of the first integrated circuit in the daisy chain compares its associated sensing current with the sensing current generated by the regulation circuit of the immediately preceding integrated circuit in the daisy chain, and so that the regulation circuit of the first integrated circuit compares its associated sensing current with the sensing current generated by the regulation circuit of the last integrated circuit in the daisy chain.

[0029] In some embodiments of the present disclosure, each regulation circuit includes an amplifier configured to directly compare its associated sense current with a value derived from at least one of the sense currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits, and to drive the gate of its corresponding power transistor based on the comparison.

[0030] In some embodiments of the present disclosure, each regulation circuit includes a first amplifier configured to drive the gate of its corresponding power transistor, and wherein the regulation circuit is further configured to sink or source current from an input terminal of the first amplifier in response to a comparison between its associated sense current and a value derived from at least one of the sense currents generated by the regulation circuits of other integrated circuits of the plurality of integrated circuits.

[0031] In some embodiments of the present disclosure, each regulation circuit also includes a second amplifier, which is configured to perform a comparison between its associated sensing current and a value derived from at least one of the sensing currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits, and to sink or source current from an input terminal of the first amplifier based on the comparison.

[0032] The present disclosure provides an improved current balancing scheme to provide safe and correct operation for multiple parallel-connected power ICs when they are expected to operate in saturation mode for a period of time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a block diagram of a prior art electronic device including two power ICs powered in parallel.

[0034] Figure 2 is a schematic diagram of an electronic device including multiple power ICs powered in parallel, with load balancing circuitry to ensure that current through the power ICs is balanced, as disclosed herein.

[0035] Figure 3 yes Figure 2 A graph of the voltage and current values ​​of the device during operation.

[0036] Figure 4 yes Figure 2 A graph of voltage and current values ​​of a device during operation when a load step occurs.

[0037] Figure 5 is with Figure 2 A similar alternative embodiment, but with the individual and shared resistors located on-chip rather than externally.

[0038] Figure 6 is with Figure 2 A similar alternative embodiment, but with the feedback resistor connected between the output node and ground instead of between the gate node and ground.

[0039] Figure 7 is with Figure 2 A similar alternative embodiment, but the op amp has been removed and a soft start ramp is generated at the gate during startup as the average of a constant current and capacitance.

[0040] Figure 8 is a schematic diagram of an electronic device including multiple power ICs powered in parallel with a daisy-chain load balancing circuit to ensure that current through the power ICs is balanced, as disclosed herein.

[0041] Fig. 9 is with Figure 8 A similar alternative embodiment, but with the independent resistors on-chip rather than external.

[0042] Fig.10 is with Figure 8 A similar alternative embodiment, but with the feedback resistor connected between the output node and ground instead of between the gate node and ground.

[0043] Fig.11 is with Figure 8 A similar alternative embodiment, but the op amp has been removed and a soft start ramp is generated at the gate during startup as the average of a constant current and capacitance. DETAILED DESCRIPTION

[0044] The following disclosure enables those skilled in the art to make and use the subject matter described herein. Without departing from the spirit and scope of the present disclosure, the general principles outlined in the present disclosure may be applied to embodiments and applications other than those described in detail above. It is not intended to limit the present disclosure to the embodiments shown, but to give it the widest scope consistent with the principles and features disclosed or suggested herein.

[0045] Please note that in the following description, any resistor or resistance mentioned is not a simple electrical lead between two points. Therefore, any resistor or resistance connected between two points will have a higher resistance than the lead between those two points. Therefore, such a resistor or resistance cannot be interpreted as a lead, and the lead in the prior art reference cannot be interpreted as a resistor in the present disclosure. Similarly, any capacitor or capacitance mentioned is not a parasitic element. Therefore, such a capacitor or capacitance cannot be interpreted as a parasitic capacitance, and the parasitic capacitance in the prior art reference cannot be interpreted as a capacitor in the present disclosure. Moreover, any inductor or inductance mentioned is not a parasitic element. Therefore, such an inductor or inductance cannot be interpreted as a parasitic inductance, and the parasitic inductance in the prior art reference cannot be interpreted as an inductor in the present disclosure.

[0046] Moreover, unless otherwise expressly stated, any resistor present may have the same resistance as one or more other resistors present, or it may have a different resistance. Similarly, unless otherwise expressly stated, any capacitor present may have the same capacitance as one or more other capacitors present, or it may have a different capacitance. Furthermore, unless otherwise expressly stated, any current source present may generate an output current equal to the output current generated by one or more other current sources present, or it may generate an output current having a different value.

[0047] Now in this article reference Figure 2 An electronic device 20 including a first power integrated circuit (IC) 21 and a second power IC (31) is described.

[0048] The first power IC 21 includes an n-channel MOS T1, whose drain is connected to an input node to receive an input voltage Vin, whose source is connected to a load (represented as a resistor Rload), and whose gate is controlled by the output of an operational amplifier 23. The amplifier 23 is powered between the output of a charge pump 24 that boosts the input voltage Vin and ground, whose non-inverting input terminal is connected to a soft-start capacitor Css, and whose inverting input terminal is connected to a node N1. A current source 27 that generates a current Iss is connected between Vdd and the non-inverting input terminal of the amplifier 23, and a switch S1 is connected between the non-inverting input terminal of the amplifier 23 and ground. The switch S1 is controlled by the inversion of a control signal Von provided by an inverter 25. A resistor Rtop1 is connected between the output of the amplifier 23 and the node N1, and a resistor Rbot1 is connected between the node N1 and ground. The output of the operational transconductance amplifier 22 is connected to the node N1, its non-inverting input terminal is connected to the node N2, and its inverting input terminal is connected to the node N3. An independent resistor Rind1 (outside the first power IC 21 and associated with the first power IC 21) is connected between the node N2 and the ground. The current sensing circuit 26 senses the current Iout1 originating from the source of the MOS transistor T1, sources a first sensing current Isns1 to the node N2 based on the sensed current Iout1, and sources a second sensing current Isns2 to the node N3 based on the sensed current Iout1. The sensing current Isns1 is equal to Isns2. The resistor Rcom (outside all power ICs) is connected between the node N3 and the ground.

[0049] The second power IC 31 includes an n-channel MOS T2, whose drain is connected to the input node to receive the input voltage Vin, whose source is connected to the load (represented as a resistor Rload), and whose gate is controlled by the output of the operational amplifier 33. The amplifier 33 is powered between the output of the charge pump 34 that boosts the input voltage Vin and the ground, its non-inverting input terminal is connected to the soft start capacitor Css, and its inverting input terminal is connected to the node N4. A current source 37 that generates a current Iss is connected between Vdd and the non-inverting input terminal of the amplifier 33, and a switch S2 is connected between the non-inverting input terminal of the amplifier 33 and the ground. The switch S2 is controlled by the inversion of the control signal Von provided by the inverter 35. The resistor Rtop2 is connected between the output of the amplifier 33 and the node N4, and the resistor Rbot2 is connected between the node N4 and the ground. The output of the operational transconductance amplifier 32 is connected to the node N4, its non-inverting input terminal is connected to the node N5, and its inverting input terminal is connected to the node N6. Resistor Rind2 (external to and associated with the second power IC 31) is connected between node N5 and ground. Current sensing circuit 36 ​​senses current Iout2 originating from the source of MOS transistor T2, sources a third sensing current Isns3 to node N5 based on current Iout2, and sources a fourth sensing current Isns4 to node N6 based on current Iout2. Sense current Isns3 is equal to Isns4.

[0050] It should be understood that there may be any number of power ICs (e.g., 3, 4, 5, etc.) connected in parallel with power ICs 21 and 31, each having the same arrangement as power ICs 21 and 31. For ease of description and brevity, two power ICs 21 and 31 are shown and described herein. Independent resistors Rind1 and Rind2 have equal resistances (e.g., Rind), and the resistance of Rcom is equal to Rind / N, where N is the number of power ICs connected in parallel.

[0051] Now attach reference Figure 3 MOS transistors T1 and T2 act as source followers in a linear mode of operation, with their output voltages following their input voltages with approximately unity gain. Initially, the electronic device 20 is off, as reflected by the input voltage Vin, the output voltage Vout, and the gate voltages of MOS T1 and T2 being zero at time t0. To avoid excessive inrush current and protect the components of the power ICs 21 and 31, a "soft start" of transistors T1 and T2 is performed starting at time t1 (and eventually ending at time t2).

[0052] The soft start begins with the assertion of the control signal Von, turning off the switches S1 and S2, with the result that the soft start current Iss output by the current sources 27 and 37 charges the soft start capacitor Css, thereby forming and increasing the soft start voltage Vss across the soft start capacitor Css. At this time, the feedback voltage Fbk1 formed at the non-inverting terminal will be less than the soft start voltage Vss, so the operational amplifier 23 increases its output voltage, which is the gate voltage Vgate1 applied to the gate of the MOS transistor T1; similarly, the feedback voltage Fbk2 formed at the non-inverting terminal of the operational amplifier 33 will be less than the soft start voltage Vss, so the operational amplifier 33 increases its output voltage, which is the gate voltage Vgate2 applied to the gate of the MOS transistor T2. As the soft start current Iss continues to charge the soft start capacitor Css, the soft start voltage Vss continues to increase, and the operational amplifiers 23 and 33 then increase the gate voltages Vgate1 and Vgate2 accordingly.

[0053] The effect of this operation is that the gate voltages Vgate1 and Vgate2 ramp up between times t1 and t2, where the MOS transistors T1 and T2 operate in a saturated mode of operation. The output currents Iout1 and Iout2 ramp up accordingly between times t1 and t2. During the soft start period between times t1 and t2, since the transistors T1 and T2 operate in a saturated state, there may be concerns about thermal runaway due to mismatched characteristics between the power ICs 21 and 31. Current balancing is performed to reduce or eliminate this risk.

[0054] Current balancing is performed as follows. In the power IC 21, the current sensing circuit 26 senses the output current Iout1 originating from the MOS transistor T1, and generates two sensing currents Isns1 and Isns2 representing the output current Iout1 and being equal to each other. The current Isns1 flows through the independent resistor Rind1 associated with the power IC 21, thereby generating a voltage Vind1. Similarly, in the power IC 22, the current sensing circuit 36 ​​senses the output current Iout2 originating from the MOS transistor T2, and generates two sensing currents Isns3 and Isns4 representing the output current Iout2 and being equal to each other. The current Isns3 flows through the independent resistor Rind2 associated with the power IC 31, thereby generating a voltage Vind2. Both the current Isns2 and Isns4 flow to the ground through the common resistor Rcom, thereby generating a voltage Vcom representing the average value of the output currents Iout1 and Iout2.

[0055] Since the resistance of the independent resistors Rind1 and Rind2 is equal (eg, Rind), and the resistance of Rcom is equal to Rind / 2, then Rcom=Rind / 2, and the voltage across Rcom will be:

[0056]

[0057] The voltage Vind1 across Rind1 representing the output current Iout1 will be:

[0058] Vind1=Isns1×Rind1=Isns1×Rind

[0059] The voltage Vind2 across Rind2 representing the output current Iout2 will be:

[0060] Vind2=Isns3×Rind2=Isns3×Rind

[0061] Ideally, the power ICs 21 and 31 source their equal output currents Iout1 and Iout2, so ideally, the sense currents Isns1, Isns2, Isns3 and Isns4 are equal. This means that ideally, the voltages across Rind1, Rind2 and Rcom are equal.

[0062] In the power IC 21, if the voltage Vind1 (representing Iout1) is greater than the voltage Vcom (representing the average value of Iout1 and Iout2), the OTA 22 sources a current to the node N1, thereby increasing the voltage at the inverting input terminal of the operational amplifier 23, thereby reducing the rate of rise of the output voltage Vgate1, and thereby reducing the rate of rise of the output current Iout1. Conversely, if the voltage Vind1 is less than the voltage Vcom, the OTA 22 reduces the current to the node N1 (or sinks the current from the node N1), thereby reducing the voltage at the inverting input terminal of the operational amplifier 23, thereby increasing the rate of rise of the output voltage Vgate1, and thereby increasing the rate of rise of the output current Iout1. Therefore, in summary, the arrangement of the OTA 22 operates so that if Isns1 (representing Iout1) is greater than (Isns2+Isns4) / 2, then Iout1 decreases, but if Isns1 is less than (Isns2+Isns4) / 2, then Iout1 increases.

[0063] In the power IC 31, if the voltage Vind2 (representing Iout2) is greater than the voltage Vcom (representing the average of Iout1 and Iout2), the OTA 32 sources a current to the node N4, thereby increasing the voltage at the inverting input terminal of the operational amplifier 33, thereby reducing the rate of rise of the output voltage Vgate2, and thereby reducing the rate of rise of the output current Iout2. On the contrary, if the voltage Vind2 is less than the voltage Vcom, the OTA 32 reduces the current to the node N4 (or sinks the current from the node N4), thereby reducing the voltage at the inverting input terminal of the operational amplifier 33, thereby increasing the rate of rise of the output voltage Vgate2, and thereby increasing the rate of rise of the output current Iout2. Therefore, in summary, the arrangement of the OTA 32 operates so that if Isns3 (representing Iout2) is greater than the average current from all power ICs, then Iout2 decreases, but if Isns3 is less than the average current from all power ICs, then Iout2 increases.

[0064] With this current balancing operation, the output currents Iout1 and Iout2 are almost identical during the soft start phase between time t1 and t2, as shown in FIG. Figure 3 Observed in.

[0065] At time t2, Vin and Vout become equal and steady-state operation sets in. In steady-state, op amp 23 enters an open loop and stops affecting Vgate, and thus transistors T1 and T2 enter a linear mode of operation and there is no longer a concern for thermal runaway.

[0066] Figure 4 A similar operation example is shown in FIG, but during soft start, a load step occurs at time t1.5 between times t1 and t2. In the specific example shown, at time t1.5, the resistance Rload of the load suddenly increases, but as Figure 4 As can be observed in Figure 1, no visible step occurs in the output voltage Vout due to the load step. This indicates that load balancing does not affect Vout.

[0067] exist Figure 2 In the above example of , the independent resistors Rind1 and Rind2 are located outside the power ICs 21 and 31, as is the common resistor Rcom. In some applications, it may not be desirable to use external resistors. Figure 5The embodiment of the electronic device 20' shown in the FIG lacks an external resistor. Instead of an independent resistor Rind1 outside the power IC 21', a resistor Rs11 inside the power IC 21' is connected between the non-inverting input terminal of the OTA 22 and ground, and instead of an independent resistor Rind2 outside the power IC 31', a resistor Rs21 is connected between the non-inverting input terminal of the OTA 32 and ground. Instead of a single common resistor, the power IC 21' includes a resistor Rs12 connected between the inverting input terminal of the OTA 22 and ground, the power IC 31' includes a resistor Rs22 connected between the inverting input terminal of the OTA 32 and ground, and these resistors Rs12 and Rs22 are connected in parallel to each other. The resistances of the resistors Rs11, Rs21, Rs12 and Rs22 are equal.

[0068] The operations in this example are as shown above. Figure 2 This is done in which the resistors Rs11 and Rs21 correspond in operation to the individual resistors Rind1 and Rind2 and the parallel resistors R12 and R22 correspond in operation to the common resistor Rcom.

[0069] In another exemplary embodiment, the independent resistors Rind1, Rind2 and the common resistor Rcom maintain their Figure 2 , but the feedback points of operational amplifiers 23 and 33 are changed, as shown in FIG. Figure 6 As shown in . Here, in power IC 21", resistors Rtop1 and Rbot1 are connected in series between the source of MOS T1 and the ground, and the inverting input terminal of operational amplifier 23 is connected to a tap between Rtop1 and Rbot1. Similarly, in power IC 31", resistors Rtop2 and Rbot2 are connected in series between the source of MOST2 and the ground, and the inverting input terminal of operational amplifier 33 is connected to a tap between Rtop2 and Rbot2.

[0070] The operation of this embodiment is essentially the same as Figure 2 The embodiment of is the same as that of except that, by taking feedback from the sources of MOS transistors T1 and T2, the regulation performed by op amps 23 and 33 is based on the source voltages of T1 and T2 rather than their gate voltages. This can produce a more accurate slow start because the gate-to-source voltages of T1 and T2 are now tightly controlled. Regardless, the operation of current balancing remains unchanged.

[0071] exist Figure 7 In another exemplary embodiment shown in FIG, the independent resistors Rind1, Rind2 and the common resistor Rcom retain their Figure 2, but the operational amplifiers 23 and 33 are removed from the power ICs 21'" and 31'"'. Instead, in the power IC 21'"', the current source 27 is connected between the charge pump 24 and the gate of MOS T1, the switch S1 is connected between the gate of MOS T1 and ground, and the output of the OTA 22 is connected to the gate of MOS T1. In addition, outside the power IC 21'"', the soft-start capacitor Cs1 is connected between the gate of MOS T1 and ground. Similarly, in the power IC 31'"', the current source 37 is connected between the charge pump 34 and the gate of MOS T2, the switch S2 is connected between the gate of MOS T2 and ground, and the output of the OTA 32 is connected to the gate of MOS T2. In addition, outside the power IC 31'"', the soft-start capacitor Cs2 is connected between the gate of MOS T2 and ground. It is further noted that here, the polarity of the input terminals of OTA 22 and 32 is reversed; the inverting input terminal of OTA 22 is coupled to receive voltage Vind1 and the non-inverting input terminal of OTA 22 is coupled to receive voltage Vcom, while the inverting input terminal of OTA 32 is coupled to receive voltage Vind2 and the non-inverting input terminal of OTA 32 is coupled to receive voltage Vcom.

[0072] The operation of this embodiment proceeds as follows. At startup, once the input voltage Vin reaches its steady-state value, the signal Von is asserted, thereby turning off switches S1 and S2. As a result, the soft-start current Iss begins to charge the soft-start capacitors Cs1 and Cs2 to the soft-start voltages Vss1 and Vss2. Here, the soft-start voltages Vss1 and Vss2 act as gate voltages Vgate1 and Vgate2, so when the soft-start voltages Vss1 and Vss2 ramp up, the gate voltages Vgate1 and Vgate2 ramp up.

[0073] and Figure 2As in the above-described embodiment, the current sensing circuits 26 and 36 compare the voltages Vind1 and Vind2 formed across the independent resistors Rind1 and Rind2 with the voltage Vcom formed across the common resistor Rcom. However, here, if Vind1 (representing the output current Iout1) is greater than Vcom, then the amplifier 22 reduces its output current to the node N1 (or sinks current from the node N1), thereby reducing the ramp rate of the gate voltage Vgate1; if Vind1 is less than Vcom, then the amplifier 22 increases its output current to the node N1, thereby increasing the ramp rate of the gate voltage Vgate1. Similarly, if Vind2 (representing the output current Iout2) is greater than Vcom, then the amplifier 32 reduces its output current to the node N4 (or sinks current from the node N4), thereby reducing the ramp rate of the gate voltage Vgate2; if Vind2 is less than Vcom, then the amplifier 32 increases its output current to the node N4, thereby increasing the ramp rate of the gate voltage Vgate2. Therefore, the gate voltages Vgate1 and Vgate2 track each other during the soft start, and the output currents Iout1 and Iout2 also track each other during the soft start. Therefore, this embodiment actually performs the same current balancing as described above.

[0074] By daisy-chaining the power ICs together, it is possible to completely remove the common resistor Rcom, such as Figure 8 As shown in . Recall from above that there can be any number of power ICs in the configuration shown above. Figure 8 In the example device 120 of FIG. 1 , three power ICs 121, 131, and 141 are shown, but any number of power ICs so arranged may be present. As described above, the common resistor has been removed, but the power ICs 121, 131, and 141 themselves are identical to those described above with reference to FIG. 1 , except for the connection to the inverting input terminal of the OTA 122, 132, 142. Figure 2 Note that the soft-start capacitor Css connected in parallel between the non-inverting input terminals of the amplifiers 123, 133, and 143 and ground may represent different individual independent soft-start capacitors connected between the non-inverting input terminals of each of the amplifiers 123, 133, and 143 and ground, respectively.

[0075] The connection arrangement for OTAs 122, 132, and 142 is as follows. The non-inverting input terminal of OTA 122 is connected to node N2 to receive the voltage Vind1 formed across the independent resistor Rind1, and the inverting input terminal of OTA 122 is connected to node N8 to receive the voltage Vind3 formed across the independent resistor Rind3. The non-inverting input terminal of OTA 132 is connected to node N5 to receive the voltage Vind2 formed across the independent resistor Rind2, and the inverting input terminal of OTA 132 is connected to node N2 to receive the voltage Vind1 formed across the independent resistor Rind1. The non-inverting input terminal of OTA 142 is connected to node N8 to receive the voltage Vind3 formed across the independent resistor Rind3, and the inverting input terminal of OTA 142 is connected to node N5 to receive the voltage Vind2 formed across the independent resistor Rind2.

[0076] The operation is thus as follows. At the start of soft start and operation of the saturated transistors T1, T2, and T3, the signal Von is asserted to disconnect the switches S1, S2, and S3, so that the current Iss begins to charge the soft start capacitor Css and begins to ramp up the soft start voltage Vss. Therefore, at this time, Vss is greater than the voltage at the nodes N1, N4, and N7, so the operational amplifiers 123, 133, and 143 begin to ramp up the values ​​of the gate voltages Vgate1, Vgate2, and Vgate3, thereby ramping up the values ​​of the output currents Iout1, Iout2, and Iout3 until the output voltage Vout becomes equal to the input voltage Vin and the transistors T1, T2, and T3 begin to operate in a steady state in a linear mode.

[0077] During the soft start operation, current balancing is performed as follows. In the power IC 121, if the independent voltage Vind1 (representing the current Iout1) is greater than the independent voltage Vind3 (representing the current Iout3), the OTA 122 sources a current to the node N1, thereby applying a positive bias voltage at the inverting input terminal of the operational amplifier 123, thereby reducing the voltage Vgate1 (or reducing its slope when it is ramped up); on the contrary, if the independent voltage Vind1 is less than the independent voltage Vind3, the OTA 122 sinks a current from the node N1, thereby applying a negative bias voltage at the inverting input terminal of the operational amplifier 123, thereby increasing the voltage Vgate1 (or increasing its slope when it is ramped up).

[0078] In the power IC 131, if the independent voltage Vind2 (representing the current Iout2) is greater than the independent voltage Vind1 (representing the current Iout1), then the OTA 132 sources current to the node N4, thereby applying a positive bias at the inverting input terminal of the operational amplifier 133, thereby reducing the voltage Vgate2 (or reducing its slope when it ramps upward); conversely, if the independent voltage Vind2 is less than the independent voltage Vind1, then the OTA 132 absorbs current from the node N4, thereby applying a negative bias at the inverting input terminal of the operational amplifier 133, thereby increasing the voltage Vgate2 (or increasing its slope when it ramps upward).

[0079] In the power IC 141, if the independent voltage Vind3 (representing the current Iout3) is greater than the independent voltage Vind2 (representing the current Iout2), then the OTA 142 sources current to the node N7, thereby applying a positive bias voltage at the inverting input terminal of the operational amplifier 143, thereby reducing the voltage Vgate3 (or reducing its slope when it ramps upward); conversely, if the independent voltage Vind3 is less than the independent voltage Vind2, then the OTA 142 absorbs current from the node N7, thereby applying a negative bias voltage at the inverting input terminal of the operational amplifier 143, thereby increasing the voltage Vgate3 (or increasing its slope when it ramps upward).

[0080] Through this action, power IC 121 adjusts its output current Iout1 to be equal to output current Iout3, power IC 131 adjusts its output current Iout2 to be equal to output current Iout1, and power IC 141 adjusts its output current Iout3 to be equal to output current Iout2. As a result, output currents Iout1, Iout2 and Iout3 are equal, and Vgate1, Vgate2 and Vgate3 are also equal.

[0081] In another daisy chain configuration, external independent resistors Rind1, Rind2 and Rind3 may instead be located within their associated power ICs 121, 131 and 141, as shown in FIG. Fig. 9 Operation and Figure 8 The configuration is the same.

[0082] exist Fig.10 In yet another daisy chain configuration shown in , resistors Rtop1 and Rbot1 are connected in series between the source of transistor T1 and ground, resistors Rtop2 and Rbot2 are connected in series between the source of transistor T2 and ground, and resistors Rtop3 and Rbot3 are connected in series between the source of transistor T3 and ground.

[0083] The operation of this embodiment is essentially the same as Figure 8 The embodiment of is the same as that of except that, by taking feedback from the sources of MOS transistors T1, T2 and T3, the regulation performed by operational amplifiers 123, 133 and 143 is based on the source voltages of T1, T2 and T3 rather than their gate voltages. This can produce a more accurate slow start because the gate-to-source voltages of T1, T2 and T3 are now tightly controlled. Regardless, the operation of current balancing remains unchanged.

[0084] exist Fig.11 In another example embodiment shown in FIG, the independent resistors Rind1, Rind2 and Rind3 retain their Figure 8 , but the operational amplifiers 123, 133 and 143 are removed from the power ICs 121'", 131' and 141'. Instead, in the power IC 121'", the current source 127 is connected between the charge pump 124 and the gate of MOS T1, the switch S1 is connected between the gate of MOS T1 and ground, and the output of OTA 122 is connected to the gate of MOS T1. The soft start capacitor Cs1 located outside the power IC 121'" is connected between the gate of MOS T1 and ground. Similarly, in the power IC 131'", the current source 137 is connected between the charge pump 134 and the gate of MOS T2, the switch S2 is connected between the gate of MOS T2 and ground, and the output of OTA 132 is connected to the gate of MOS T2. The soft start capacitor Cs2 located outside the power IC 131'' is connected between the gate of MOST2 and the ground. In the power IC 141'', the current source 147 is connected between the charge pump 144 and the gate of MOS T3, the switch S3 is connected between the gate of MOS T3 and the ground, and the output end of the OTA 142 is connected to the gate of MOS T3. The soft start capacitor Cs3 located outside the power IC 141'' is connected between the gate of MOS T3 and the ground.

[0085] The operation of this embodiment proceeds as follows. At startup, once the input voltage Vin reaches its steady-state value, the signal Von is asserted, thereby turning off the switches S1, S2, and S3. As a result, the soft-start current Iss begins to charge the soft-start capacitors Cs1, Cs2, and Cs3 to the soft-start voltages Vss1, Vss2, and Vss3. Here, the soft-start voltages Vss1, Vss2, and Vss3 act as gate voltages Vgate1, Vgate2, and Vgate3, so that the soft-start voltages Vss1, Vss2, and Vss3 ramp up, and the gate voltages Vgate1, Vgate2, and Vgate3 ramp up.

[0086] and Figure 8As in the above-described embodiment, the current sensing circuits 126, 136, and 146 compare the voltages Vind1, Vind2, and Vind3 with the voltages Vind3, Vind1, and Vind2. If Vind1 (representing the output current Iout1) is greater than Vind3, the amplifier 123 reduces its output current to the node N1, thereby reducing the ramp rate of the gate voltage Vgate1; if Vind1 is less than Vind3, the amplifier 122 sources a current to the node N1, thereby increasing the ramp rate of the gate voltage Vgate1. If Vind2 (representing the output current Iout2) is greater than Vind1, the amplifier 132 reduces its output current to the node N4, thereby reducing the ramp rate of the gate voltage Vgate2; if Vind2 is less than Vind1, the amplifier 132 sources a current to the node N4, thereby increasing the ramp rate of the gate voltage Vgate2. If Vind3 (representing the output current Iout3) is greater than Vind2, then the amplifier 142 reduces its output current to the node N7, thereby reducing the ramp rate of the gate voltage Vgate3; if Vind3 is less than Vind2, then the amplifier 142 sources current to the node N7, thereby increasing the ramp rate of the gate voltage Vgate3.

[0087] Therefore, the gate voltages Vgate1, Vgate2 and Vgate3 track each other during the soft start, and the output currents Iout1, Iout2 and Iout3 also track each other during the soft start. Therefore, this embodiment actually performs the same current balancing as described above.

[0088] Broadly speaking, the electronic device disclosed herein is characterized by an input voltage node, a load node, and a plurality of integrated circuits. Each integrated circuit includes a power transistor connected between the input voltage node and the load node, and a regulating circuit that generates at least one sense current that represents an output current of the power transistor. The regulating circuit is designed to regulate the output current of their respective power transistors based on a value derived from a sense current generated by a regulating circuit of another integrated circuit in the device.

[0089] This derived value may be based on an average of the sense currents generated by the regulation circuits of the other integrated circuits or based on one of the sense currents generated by one of the regulation circuits of the other integrated circuits. The integrated circuits may be arranged in a daisy-chain relationship, allowing each regulation circuit except the first regulation circuit in the daisy-chain to compare its associated sense current with the sense current generated by the regulation circuit of the immediately preceding integrated circuit in the daisy-chain. The first regulation circuit in the daisy-chain compares its associated sense current with the sense current generated by the regulation circuit of the last integrated circuit in the daisy-chain.

[0090] In some configurations, each regulation circuit includes an amplifier that directly compares its associated sense current to the derived value and drives the gate of its corresponding power transistor based on the comparison.

[0091] In other configurations, each regulation circuit features a first amplifier that drives the gate of its corresponding power transistor, and the regulation circuit is designed to sink or source current from an input terminal of the first amplifier in response to a comparison between its associated sense current and a derived value. In this case, each regulation circuit includes a second amplifier that performs a comparison between its associated sense current and the derived value and sinks or sources current from an input terminal of the first amplifier based on the comparison.

[0092] Also disclosed herein is an electronic device characterized by an input voltage node, a load node, and two integrated circuits. The first integrated circuit includes a first power transistor connected between the input voltage node and the load node, and a first regulating circuit that generates first and second sensing currents representing an output current of the first power transistor. The second integrated circuit includes a second power transistor connected between the input voltage node and the load node, and a second regulating circuit that generates third and fourth sensing currents representing an output current of the second power transistor.

[0093] The first and second regulation circuits are designed to adjust the output currents of the first and second power transistors, respectively, based on a comparison of the first and third sense currents with an average value of the second and fourth sense currents. The device may also include an external resistor connected to the first, third, second, and fourth sense currents to generate a voltage representative of the output currents of the first and second power transistors and their average values.

[0094] The first and second regulation circuits may include a plurality of amplifiers whose inputs are coupled to receive various combinations of voltages and soft-start voltages. The amplifiers are designed to source or sink current from their outputs based on a comparison of the voltages. In some configurations, the first and second regulation circuits may include resistor ladders coupled between the outputs of the power transistors or amplifiers and the reference voltage. The taps of these resistor ladders are connected to the outputs of the corresponding amplifiers.

[0095] In another configuration, the device can have resistors located within the first and second integrated circuits, which are connected to receive the first, second, third and fourth sense currents. The second and fourth resistors are coupled in parallel, and the voltage across them represents the average of the output currents of the first and second power transistors. The first and second regulation circuits in this configuration also include a plurality of amplifiers whose inputs are coupled to receive various combinations of voltages and soft-start voltages, similar to the configurations described previously.

[0096] Further disclosed herein is an electronic device characterized by an input voltage node and a load node and three integrated circuits. The first integrated circuit includes a first power transistor connected between the input voltage node and the load node, and a first regulating circuit that generates a first sense current representative of an output current of the first power transistor. Similarly, the second and third integrated circuits each include a power transistor connected between the input voltage node and the load node, and a regulating circuit that generates a sense current representative of their respective output currents.

[0097] The regulating circuit has a specific configuration: when the first sensing current is greater than the third sensing current, the first regulating circuit causes the first power transistor to reduce its output current, and when the first sensing current is less than the third sensing current, the first power transistor increases its output current. The second regulating circuit operates in a similar manner, reducing or increasing the output current of the second power transistor based on the relationship between the second sensing current and the first sensing current. The third regulating circuit also performs the same operation, regulating the output current of the third power transistor based on the comparison between the third sensing current and the second sensing current.

[0098] In addition to the integrated circuit, the electronic device also includes external first, second and third resistors. These resistors receive their respective sense currents, and the voltage formed across them represents the output current of the corresponding power transistor. The first, second and third regulation circuits each include a pair of amplifiers with a specific configuration that helps drive the control terminal of their respective power transistors. These regulation circuits also include a resistor ladder coupled between the output of their respective amplifiers and a reference voltage.

[0099] The electronic device may also have a version in which the first, second and third resistors are located within their respective integrated circuits. In this configuration, the regulation circuit also features a pair of amplifiers, and retains similar functionality as previously described, driving the control terminals of their respective power transistors.

[0100] Obviously, modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0101] Although the present disclosure has been described using a limited number of embodiments, those skilled in the art having benefit of this disclosure may conceive other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may conceive embodiments that represent various combinations of the embodiments disclosed herein performed in various ways.

Claims

1. An electronic device, characterized in that include: Input voltage node and load node; A first integrated circuit comprising: A first power transistor connected between an input voltage node and a load node; and a first regulation circuit configured to generate a first sense current and a second sense current representative of an output current of the first power transistor; and A second integrated circuit comprising: A second power transistor connected between the input voltage node and the load node; and a second regulation circuit configured to generate a third sense current and a fourth sense current representative of an output current of the second power transistor; wherein the first regulating circuit is configured to cause the first power transistor to reduce its output current when the first sensing current is greater than an average of the second sensing current and the fourth sensing current; wherein the first regulating circuit is configured to cause the first power transistor to increase its output current when the first sensing current is less than an average of the second sensing current and the fourth sensing current; wherein the second regulating circuit is configured to cause the second power transistor to reduce its output current when the third sensing current is greater than an average of the second sensing current and the fourth sensing current; and The second regulating circuit is configured to cause the second power transistor to increase its output current when the third sensing current is less than an average value of the second sensing current and the fourth sensing current.

2. The electronic device according to claim 1, wherein: The electronic device further comprises: a first resistor external to the first integrated circuit and the second integrated circuit and coupled to receive the first sense current such that a first voltage developed across the first resistor represents an output current of the first power transistor; a second resistor external to the first integrated circuit and the second integrated circuit and coupled to receive the third sense current such that a second voltage developed across the second resistor represents an output current of the second power transistor; and A third resistor is located outside the first integrated circuit and the second integrated circuit and is coupled to receive the second sensing current and the fourth sensing current so that a third voltage formed across the third resistor represents an average of the output currents of the first power transistor and the second power transistor.

3. The electronic device according to claim 2, The first regulating circuit comprises: a first amplifier having an input terminal coupled to receive the first voltage and a third voltage, the first amplifier being configured to source current to its output terminal when the first voltage is greater than the third voltage and to sink current from its output terminal when the first voltage is less than the third voltage; as well as a second amplifier having an input coupled to receive the soft start voltage and a voltage generated at an output of the first amplifier, wherein an output of the second amplifier is coupled to drive a control terminal of the first power transistor; as well as The second regulating circuit comprises: a third amplifier having an input terminal coupled to receive the second voltage and a third voltage, the third amplifier being configured to source current to its output terminal when the second voltage is greater than the third voltage and to sink current from its output terminal when the second voltage is less than the third voltage; as well as A fourth amplifier has an input coupled to receive the soft start voltage and the voltage generated at the output of the third amplifier, wherein the output of the fourth amplifier is coupled to drive the control terminal of the second power transistor.

4. The electronic device according to claim 3, wherein the first conditioning circuit further comprises a first resistor ladder coupled between an output of the second amplifier and a reference voltage, wherein a tap of the first resistor ladder is coupled to the output of the first amplifier; and The second regulation circuit further includes a second resistor ladder coupled between the output terminal of the fourth amplifier and a reference voltage, wherein a tap of the second resistor ladder is coupled to the output terminal of the third amplifier.

5. The electronic device according to claim 3, wherein the first regulation circuit further comprises a first resistor ladder coupled between an output terminal of the first power transistor and a reference voltage, wherein a tap of the first resistor ladder is coupled to an output terminal of the first amplifier; and The second regulation circuit further includes a second resistor ladder coupled between an output terminal of the second power transistor and a reference voltage, wherein a tap of the second resistor ladder is coupled to an output terminal of the third amplifier.

6. The electronic device according to claim 2, wherein a control terminal of the first power transistor is coupled to a first soft start voltage and a control terminal of the second power transistor is coupled to a second soft start voltage; wherein the first regulation circuit includes a first amplifier having an input terminal coupled to receive a first voltage and a third voltage, the first amplifier being configured to sink current from an output terminal thereof when the first voltage is greater than the third voltage and to source current to an output terminal thereof when the first voltage is less than the third voltage, wherein an output terminal of the first amplifier is coupled to drive a control terminal of a first power transistor; as well as The second regulation circuit includes a second amplifier whose input terminal is coupled to receive the second voltage and the third voltage, the second amplifier is configured to sink current from its output terminal when the second voltage is greater than the third voltage, and to source current to its output terminal when the second voltage is less than the third voltage, wherein the output terminal of the second amplifier is coupled to drive the control terminal of the second power transistor.

7. The electronic device according to claim 1, wherein: The electronic device further comprises: a first resistor located within the first integrated circuit and coupled to receive the first sense current such that a first voltage developed across the first resistor represents an output current of the first power transistor; a second resistor located within the first integrated circuit and coupled to receive a second sensing current; a third resistor located within the second integrated circuit and coupled to receive the third sense current such that a second voltage developed across the second resistor represents an output current of the second power transistor; a fourth resistor located within the second integrated circuit and coupled to receive a fourth sensing current; The second resistor and the fourth resistor are coupled in parallel, so that a third voltage formed across the second resistor and the fourth resistor represents an average value of the output currents of the first power transistor and the second power transistor.

8. The electronic device according to claim 7, The first regulating circuit comprises: a first amplifier having an input terminal coupled to receive the first voltage and a third voltage, the first amplifier being configured to source current to its output terminal when the first voltage is greater than the third voltage and to sink current from its output terminal when the first voltage is less than the third voltage; as well as a second amplifier having an input coupled to receive the soft start voltage and a voltage generated at an output of the first amplifier, wherein an output of the second amplifier is coupled to drive a control terminal of the first power transistor; as well as The second regulating circuit comprises: a third amplifier having an input terminal coupled to receive the second voltage and a third voltage, the third amplifier being configured to source current to its output terminal when the second voltage is greater than the third voltage and to sink current from its output terminal when the second voltage is less than the third voltage; as well as A fourth amplifier has an input coupled to receive the soft start voltage and the voltage generated at the output of the third amplifier, wherein the output of the fourth amplifier is coupled to drive the control terminal of the second power transistor.

9. An electronic device, characterized in that include: Input voltage node and load node; A first integrated circuit comprising: A first power transistor connected between an input voltage node and a load node; and a first regulation circuit configured to generate a first sense current representative of an output current of a first power transistor; and A second integrated circuit comprising: A second power transistor connected between the input voltage node and the load node; and a second regulation circuit configured to generate a second sense current representative of an output current of a second power transistor; and The third integrated circuit comprises: A third power transistor connected between the input voltage node and the load node; and a third regulation circuit configured to generate a third sense current representative of an output current of a third power transistor; wherein the first regulating circuit is configured to cause the first power transistor to reduce its output current when the first sensing current is greater than the third sensing current; wherein the first regulating circuit is configured to cause the first power transistor to increase its output current when the first sensing current is less than the third sensing current; wherein the second regulating circuit is configured to cause the second power transistor to reduce its output current when the second sensing current is greater than the first sensing current; wherein the second regulating circuit is configured to cause the second power transistor to increase its output current when the second sensing current is less than the first sensing current; wherein the third regulating circuit is configured to cause the third power transistor to reduce its output current when the third sensing current is greater than the second sensing current; and The third regulating circuit is configured to enable the third power transistor to increase its output current when the third sensing current is less than the second sensing current.

10. The electronic device according to claim 9, characterized in that: The electronic device further comprises: a first resistor external to the first integrated circuit, the second integrated circuit, and the third integrated circuit and coupled to receive the first sense current such that a first voltage developed across the first resistor represents an output current of the first power transistor; a second resistor external to the first integrated circuit, the second integrated circuit, and the third integrated circuit and coupled to receive the second sense current such that a second voltage developed across the second resistor represents an output current of the second power transistor; and A third resistor is located outside the first integrated circuit, the second integrated circuit, and the third integrated circuit and is coupled to receive the third sense current such that a third voltage developed across the third resistor represents an output current of the third power transistor.

11. The electronic device according to claim 10, The first regulating circuit comprises: a first amplifier having an input terminal coupled to receive the first voltage and a third voltage, the first amplifier being configured to source current to its output terminal when the first voltage is greater than the third voltage and to sink current from its output terminal when the first voltage is less than the third voltage; as well as a second amplifier having an input coupled to receive the soft start voltage and a voltage generated at an output of the first amplifier, wherein an output of the second amplifier is coupled to drive a control terminal of the first power transistor; as well as The second regulating circuit comprises: a third amplifier having an input terminal coupled to receive the second voltage and the first voltage, the third amplifier being configured to source current to its output terminal when the second voltage is greater than the first voltage and to sink current from its output terminal when the second voltage is less than the first voltage; and a fourth amplifier having an input coupled to receive the soft start voltage and the voltage generated at the output of the third amplifier, wherein the output of the fourth amplifier is coupled to drive the control terminal of the second power transistor; The third regulating circuit comprises: a fifth amplifier having an input terminal coupled to receive the third voltage and the second voltage, the fifth amplifier being configured to source current to its output terminal when the third voltage is greater than the second voltage and to sink current from its output terminal when the third voltage is less than the second voltage; and A sixth amplifier has an input coupled to receive the soft start voltage and the voltage generated at the output of the fifth amplifier, wherein the output of the fourth amplifier is coupled to drive the control terminal of the third power transistor.

12. The electronic device according to claim 11, wherein the first conditioning circuit further comprises a first resistor ladder coupled between the output of the second amplifier and a reference voltage, wherein a tap of the first resistor ladder is coupled to the output of the first amplifier; wherein the second conditioning circuit further comprises a second resistor ladder coupled between the output of the fourth amplifier and the reference voltage, wherein a tap of the second resistor ladder is coupled to the output of the third amplifier; and The third regulation circuit further includes a third resistor ladder coupled between the output terminal of the sixth amplifier and a reference voltage, wherein a tap of the third resistor ladder is coupled to the output terminal of the fifth amplifier.

13. The electronic device according to claim 11, wherein the first regulation circuit further comprises a first resistor ladder coupled between an output terminal of the first power transistor and a reference voltage, wherein a tap of the first resistor ladder is coupled to an output terminal of the first amplifier; wherein the second regulation circuit further comprises a second resistor ladder coupled between an output terminal of the second power transistor and a reference voltage, wherein a tap of the second resistor ladder is coupled to an output terminal of the third amplifier; and The third regulating circuit further includes a third resistor ladder coupled between the output terminal of the third power transistor and a reference voltage, wherein a tap of the third resistor ladder is coupled to the output terminal of the fifth amplifier.

14. The electronic device according to claim 10, wherein a control terminal of the first power transistor is coupled to a first soft start voltage, a control terminal of the second power transistor is coupled to a second soft start voltage, and a control terminal of the third power transistor is coupled to a third soft start voltage; wherein the first regulation circuit includes a first amplifier having an input terminal coupled to receive a first voltage and a third voltage, the first amplifier being configured to sink current from an output terminal thereof when the first voltage is greater than the third voltage and to source current to an output terminal thereof when the first voltage is less than the third voltage, wherein an output terminal of the first amplifier is coupled to drive a control terminal of a first power transistor; wherein the second regulation circuit includes a second amplifier having an input terminal coupled to receive the second voltage and the first voltage, the second amplifier being configured to sink current from its output terminal when the second voltage is greater than the first voltage and to source current to its output terminal when the second voltage is less than the first voltage, wherein the output terminal of the second amplifier is coupled to drive a control terminal of the second power transistor; as well as The third regulation circuit includes a third amplifier, whose input terminal is coupled to receive a third voltage and a second voltage, and the third amplifier is configured to sink current from its output terminal when the third voltage is greater than the second voltage, and to source current to its output terminal when the third voltage is less than the second voltage, wherein the output terminal of the third amplifier is coupled to drive the control terminal of the third power transistor.

15. The electronic device according to claim 9, characterized in that: The electronic device further comprises: a first resistor located within the first integrated circuit and coupled to receive the first sense current such that a first voltage developed across the first resistor represents an output current of the first power transistor; a second resistor within the second integrated circuit and coupled to receive the second sense current such that a second voltage developed across the second resistor represents an output current of the second power transistor; and A third resistor is located within the third integrated circuit and is coupled to receive the third sensing current such that a third voltage developed across the third resistor represents the output current of the third power transistor.

16. The electronic device according to claim 15, The first regulating circuit comprises: a first amplifier having an input terminal coupled to receive the first voltage and a third voltage, the first amplifier being configured to source current to its output terminal when the first voltage is greater than the third voltage and to sink current from its output terminal when the first voltage is less than the third voltage; as well as a second amplifier having an input coupled to receive the soft start voltage and a voltage generated at an output of the first amplifier, wherein an output of the second amplifier is coupled to drive a control terminal of the first power transistor; as well as The second regulating circuit comprises: a third amplifier having an input terminal coupled to receive the second voltage and the first voltage, the third amplifier being configured to source current to its output terminal when the second voltage is greater than the first voltage and to sink current from its output terminal when the second voltage is less than the first voltage; and a fourth amplifier having an input coupled to receive the soft start voltage and the voltage generated at the output of the third amplifier, wherein the output of the fourth amplifier is coupled to drive the control terminal of the second power transistor; The third regulating circuit comprises: a fifth amplifier having an input terminal coupled to receive the third voltage and the second voltage, the fifth amplifier being configured to source current to its output terminal when the third voltage is greater than the second voltage and to sink current from its output terminal when the third voltage is less than the second voltage; and A sixth amplifier has an input coupled to receive the soft start voltage and the voltage generated at the output of the fifth amplifier, wherein the output of the fourth amplifier is coupled to drive the control terminal of the third power transistor.

17. An electronic device, characterized in that include: Input voltage node and load node; as well as A plurality of integrated circuits, each integrated circuit comprising: a power transistor connected between an input voltage node and a load node; and a regulation circuit configured to generate at least one sense current representative of an output current of the power transistor; wherein each regulation circuit is configured to cause its corresponding power transistor to reduce its output current when the sense current generated by it is greater than a value derived from at least one of the sense currents generated by the regulation circuits of other integrated circuits of the plurality of integrated circuits; Each regulation circuit is configured to cause its corresponding power transistor to increase its output current when the sense current generated by it is less than a value derived from at least one of the sense currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits.

18. An electronic device as described in claim 17, wherein the value derived from at least one of the sensing currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits is based on an average value of the sensing currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits.

19. An electronic device as described in claim 17, wherein the value derived from at least one of the sensing currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits is based on one of the sensing currents generated by one of the regulation circuits of other integrated circuits in the plurality of integrated circuits.

20. An electronic device as described in claim 17, wherein the multiple integrated circuits are arranged in a daisy-chain relationship, so that each regulation circuit except the regulation circuit of the first integrated circuit in the daisy chain compares its associated sensing current with the sensing current generated by the regulation circuit of the integrated circuit immediately preceding the daisy chain, and so that the regulation circuit of the first integrated circuit compares its associated sensing current with the sensing current generated by the regulation circuit of the last integrated circuit in the daisy chain.

21. An electronic device as described in claim 17, wherein each regulation circuit includes an amplifier configured to directly compare its associated sense current with a value derived from at least one of the sense currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits, and to drive the gate of its corresponding power transistor based on the comparison.

22. An electronic device as described in claim 17, wherein each regulation circuit includes a first amplifier configured to drive the gate of its corresponding power transistor, and wherein the regulation circuit is further configured to sink or source current from an input terminal of the first amplifier in response to a comparison between its associated sense current and a value derived from at least one of the sense currents generated by the regulation circuits of other integrated circuits in the plurality of integrated circuits.

23. An electronic device as described in claim 22, wherein each regulation circuit further includes a second amplifier, the second amplifier being configured to perform a comparison between its associated sensing current and a value derived from at least one of the sensing currents generated by the regulation circuits of other integrated circuits of the plurality of integrated circuits, and to sink or source current from an input terminal of the first amplifier based on the comparison.

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