Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a substrate body, a plurality of sub-pixels, a plurality of data lines, a plurality of first contact pads, a plurality of second contact pads, a plurality of connecting lines, an organic protective layer and an inorganic protective layer. The organic protective layer is provided with at least one groove; the inorganic protection layer is located on the side, away from the substrate, of the organic protection layer and covers the at least one groove, and the inorganic protection layer is in direct contact with at least one connecting line in the multiple connecting lines through the at least one groove. According to the display substrate and the display device, the grooving design of the organic protection layer is adopted, the size of the organic protection layer located in the first frame area is reduced, the situation that the continuous and large-area organic protection layer is divided into a plurality of units is avoided, and meanwhile the grooves can directly isolate water vapor.

Description

Technical Field

[0001] The utility model relates to the field of display equipment, in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device. According to different driving modes, OLED can be divided into two types: passive matrix drive (PM) type and active matrix drive (AM) type. AMOLED is a current-driven device that uses independent thin-film transistors (TFT) to control each sub-pixel. Each sub-pixel can be driven to emit light continuously and independently.

[0003] In order to ensure that the AMOLED display panel can display normally under various complex conditions, we will conduct reliability tests on the panel in various environments, such as high pressure, high temperature, high humidity, etc. At present, the stability of the film structure of the AMOLED display panel is not ideal, and there are reliability issues. Utility Model Content

[0004] The embodiments of the utility model provide a display substrate and a display device. By setting a groove in the organic protective layer in the first frame area, the diffusion of water vapor can be directly blocked, and a large area of ​​continuous organic protective layer is avoided, so that water vapor is not easy to diffuse upward and affect the stability of the film layer.

[0005] At least one embodiment of the present disclosure provides a display substrate, including a base substrate, the base substrate including a display area and a first frame area located at at least one side of the display area, the first frame area including a first binding area and a second binding area, the second binding area being located at a side of the first binding area away from the display area;

[0006] A plurality of sub-pixels are located on one side of the base substrate and in the display area;

[0007] A plurality of data lines are located in the display area and the first frame area, and the plurality of data lines are electrically connected to the plurality of sub-pixels;

[0008] a plurality of first contact pads, located in the first binding area, the plurality of first contact pads being configured to be bound to a driving chip, the plurality of first contact pads comprising at least one row of first input contact pads and at least one row of first output contact pads, the at least one row of first input contact pads being located on a side of the at least one row of first output contact pads away from the display area, the plurality of data lines being electrically connected to the at least one row of first output contact pads;

[0009] A plurality of second contact pads, located in the second binding area, and the plurality of second contact pads are configured to be bound to the circuit board;

[0010] a plurality of connection lines located between the at least one row of first input contact pads and the plurality of second contact pads, the plurality of connection lines being configured to connect the at least one row of first input contact pads and the plurality of second contact pads;

[0011] An organic protective layer, located on a side of the plurality of connection lines away from the base substrate, the organic protective layer being provided with at least one groove, the groove penetrating the organic protective layer in a direction perpendicular to the base substrate;

[0012] The inorganic protective layer is located on a side of the organic protective layer away from the base substrate and covers the at least one groove. The inorganic protective layer is in direct contact with at least one connecting line among the plurality of connecting lines through the at least one groove.

[0013] In some exemplary embodiments, an extension direction of the at least one groove intersects an extension direction of the plurality of connection lines, and an orthographic projection of the at least one groove on the substrate overlaps an orthographic projection of the plurality of connection lines on the substrate;

[0014] The inorganic protection layer is in direct contact with the plurality of connection lines through the at least one groove.

[0015] In some exemplary embodiments, the at least one groove includes a first groove and a second groove, and the second groove is located on a side of the first groove away from the display area.

[0016] In some exemplary embodiments, the organic protective layer includes a plurality of protective units, the plurality of protective units are located in the first border area and are arranged sequentially in a direction away from the display area, and the at least one groove is configured to separate two adjacent protective units among the plurality of protective units.

[0017] In some exemplary embodiments, at least one of the plurality of protection units includes a first body, a surface of the first body close to the groove is an inclined surface, and the inclined surface is inclined toward one side of the groove.

[0018] In some exemplary embodiments, the slope angle of the inclined surface is set to α, 5°≤α≤45°.

[0019] In some exemplary embodiments, the inclined surface is configured as an arc-shaped surface, and the arc-shaped surface is configured to protrude toward a side away from the base substrate.

[0020] In some exemplary embodiments, at least one of the protection units further includes a second body, the first body is located on a side of the second body close to the groove, and a thickness of the first body is less than or equal to a thickness of the second body.

[0021] In some exemplary embodiments, the first input contact pad and the second contact pad are arranged in one-to-one correspondence and are connected via one of the connecting lines; or,

[0022] One of the first input contact pads is connected to a plurality of the second contact pads via one of the connecting lines; or,

[0023] A plurality of the first input contact pads are connected to one of the second contact pads via one of the connecting lines; or,

[0024] A plurality of the first input contact pads are connected to a plurality of the second contact pads via one of the connecting lines.

[0025] In some exemplary embodiments, at least one of the plurality of connection lines comprises a first metal line and a second metal line, the second metal line is located on a side of the first metal line away from the substrate, and the first metal line and the second metal line are in direct contact and electrically connected.

[0026] In some exemplary embodiments, the display substrate includes a circuit structure layer and a light emitting structure layer which are sequentially arranged in a direction away from the base substrate;

[0027] At least one sub-pixel among the plurality of sub-pixels comprises a pixel circuit, a first switching electrode and a light-emitting element, wherein the pixel circuit and the first switching electrode are located in the circuit structure layer, the light-emitting element is located in the light-emitting structure layer, and the pixel circuit is electrically connected to the light-emitting element through the first switching electrode;

[0028] The circuit structure layer further includes a first flat layer and a second flat layer, wherein the first flat layer is located on a side of the first switching electrode close to the base substrate, and the second flat layer is located on a side of the first switching electrode away from the base substrate;

[0029] The organic protection layer and the second planar layer are located on the same layer and are made of the same material.

[0030] In some exemplary embodiments, the display substrate further comprises a touch control structure layer located on a side of the light emitting structure layer away from the base substrate, the touch control structure layer comprising a first touch control conductive layer, a touch control interlayer insulating layer and a second touch control conductive layer sequentially arranged away from the base substrate;

[0031] The inorganic protection layer and the touch control interlayer insulating layer are located on the same layer.

[0032] In some exemplary embodiments, the pixel circuit includes a transistor, the transistor includes an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and the first transfer electrode is located on a side of the source and the drain away from the substrate;

[0033] The connection line includes a first metal line and a second metal line that are stacked, the first metal line and the source or the drain are located in the same layer, and the second metal line and the first transfer electrode are located in the same layer.

[0034] In some exemplary embodiments, at least one sub-pixel among the plurality of sub-pixels comprises a second switching electrode, and the first switching electrode is located on a side of the second switching electrode close to the base substrate;

[0035] The connecting wire includes a first metal wire and a second metal wire which are stacked, the first metal wire and the first switching electrode are located in the same layer, and the second metal wire and the second switching electrode are located in the same layer.

[0036] At least one embodiment of the present disclosure provides a display device including the above-mentioned display substrate.

[0037] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide a further understanding of the technical solution of the utility model and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the utility model and do not constitute a limitation on the technical solution of the utility model.

[0039] Figure 1 is a structural schematic diagram of a display device;

[0040] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0041] Figure 3 for Figure 2 AA section diagram in FIG.

[0042] Figure 4 is a schematic diagram of a display substrate of this exemplary embodiment;

[0043] Figure 5 for Figure 4 BB section diagram in FIG.

[0044] Figure 6 for Figure 4 A local enlarged schematic diagram of point C in FIG.

[0045] Figure 7 for Figure 5 A partial enlarged schematic diagram of point D in the middle.

[0046] Description of reference numerals:

[0047] 10-substrate substrate; 20-circuit structure layer; 30-light emitting structure layer;

[0048] 40-encapsulation structure layer; 50-touch structure layer; 60-color filter layer;

[0049] 101-a first gate insulating layer; 102-a second gate insulating layer; 103-an interlayer insulating layer;

[0050] 104-passivation layer; 105-first flat layer; 106-second flat layer;

[0051] 107-third planar layer; 21-thin film transistor; 210-active layer;

[0052] 211-source; 212-drain; 213-gate;

[0053] 2100-channel region; 2101-first region; 2102-second region;

[0054] 22-capacitor; 221-first electrode plate; 222-second electrode plate;

[0055] 231-first switching electrode; 232-second switching electrode; 232-second switching electrode;

[0056] 301-first electrode; 302-organic light-emitting layer; 303-second electrode;

[0057] 304-pixel definition layer; 401-first encapsulation layer; 402-second encapsulation layer;

[0058] 403 - third encapsulation layer; 501 - touch buffer layer; 502 - touch interlayer insulation layer;

[0059] 511 - first touch conductive layer; 512 - second touch conductive layer; 601 - color film buffer layer;

[0060] 602-color film protection layer; 610-black matrix; 611-light filtering unit;

[0061] 24-data line; 25-first contact pad; 251-first input contact pad;

[0062] 252-first output contact pad; 26-second contact pad; 27-connecting line;

[0063] 271-first metal wire; 272-second metal wire; 28-groove;

[0064] 281-first groove; 282-second groove; 29-organic protective layer;

[0065] 291-protection unit; 292-first body; 293-second body;

[0066] 294-first protection unit; 295-second protection unit; 296-third protection unit;

[0067] 297- inclined surface; 31- inorganic protective layer; 108- semiconductor layer;

[0068] 109 - a first gate metal layer; 110 - a second gate metal layer; 111 - a first source-drain metal layer;

[0069] 112 - a second source-drain metal layer; 113 - a third source-drain metal layer. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0071] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0072] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0073] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0074] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0075] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0076] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0077] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0078] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0079] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0080] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0081] The term "about" in the embodiments of the present disclosure means that the limits are not strictly defined and a numerical value within the range of process and measurement errors is allowed.

[0082] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to the scan signal line, the light emitting signal line and the data signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of unit lines, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0083] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the light-emitting signal line, and the data signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0084] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0085] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0086] Figure 3 for Figure 2 Schematic diagram of the AA section in . Figure 3 The structure of a sub-pixel in the display area is used as an example for illustration. In this example, the same type of multiple transistors in the pixel circuit is used as an example for illustration. For example, multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or all use oxide thin-film transistors. In other examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. In addition, this example takes the display panel integrating a mutual capacitance touch structure to form a flexible multi-layer covered surface (Flexible Multi-Layer On Cell, FMLOC for short) structure as an example for illustration.

[0087] In some exemplary embodiments, Figure 3As shown, in the direction perpendicular to the display panel, the display area of ​​the display panel may include: a base substrate 10, and a circuit structure layer 20, a light emitting structure layer 30, a packaging structure layer 40, a touch structure layer 50 and a color filter layer 60 sequentially arranged on the base substrate 10. The circuit structure layer 20 may include at least: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 30 may include at least: a light emitting element of a plurality of sub-pixels.

[0088] In some exemplary embodiments, Figure 3 As shown, the circuit structure layer 20 in the display area may include: a semiconductor layer 108, a first gate metal layer 109, a second gate metal layer 110, a first source-drain metal layer 111, a second source-drain metal layer 112, and a third source-drain metal layer 113, which are arranged on the base substrate 10. The first gate metal layer 109, the second gate metal layer 110, the first source-drain metal layer 111, the second source-drain metal layer 112, and the third source-drain metal layer 113 are stacked in sequence in a direction away from the base substrate 10. A first gate insulating layer 101 may be provided between the semiconductor layer 108 and the first gate metal layer 109, a second gate insulating layer 102 may be provided between the first gate metal layer 109 and the second gate metal layer 110, an interlayer insulating layer 103 may be provided between the second gate metal layer 110 and the first source-drain metal layer 111, a passivation layer 104 and a first flat layer 105 may be provided between the first source-drain metal layer 111 and the second source-drain metal layer 112, a second flat layer 106 may be provided between the second source-drain metal layer 112 and the third source-drain metal layer 113, and a third flat layer 107 may be provided on the side of the third source-drain metal layer 113 away from the base substrate 10. The first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103 and the passivation layer 104 may be inorganic insulating layers, and the first flat layer 105, the second flat layer 106 and the third flat layer 107 may be organic insulating layers. However, this embodiment is not limited thereto. In other examples, a buffer layer may be provided on the side of the semiconductor layer 108 close to the base substrate 10, and the buffer layer may prevent harmful substances in the base from invading the interior of the display panel, and may also increase the adhesion of the film layer in the display panel on the base substrate 10. In other examples, a bottom shielding metal layer (BSM) may be provided on the side of the buffer layer close to the base substrate 10, and the bottom shielding metal layer may be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to prevent external light from affecting the performance of the thin film transistor. In other examples, the passivation layer may be omitted between the first source-drain metal layer 111 and the second source-drain metal layer 112, and only the first planar layer may be provided between the first source-drain metal layer 111 and the second source-drain metal layer 112.

[0089] In some exemplary embodiments, Figure 3 As shown, the semiconductor layer 108 in the display area may include at least: an active layer 210 of a thin film transistor 21. The active layer 210 of the thin film transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer 109 may include at least: a gate electrode 213 of the thin film transistor 21, and a first electrode plate 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10. The second gate metal layer 110 may include at least: a second electrode plate 222 of the capacitor 22. The orthographic projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may overlap. The first source-drain metal layer 111 may include at least: a source electrode 211 and a drain electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer 112 may include at least: a first transfer electrode 231. The first transfer electrode 231 can be electrically connected to the drain 212 of the thin film transistor 21 of the pixel circuit through the third pixel via hole opened in the passivation layer 104 and the first flat layer 105. The third source-drain metal layer 113 can include at least: a second transfer electrode 232. The second transfer electrode 232 can be electrically connected to the first transfer electrode 231 located in the second source-drain metal layer 112 through the fourth pixel via hole opened in the second flat layer 106. The second transfer electrode 232 can be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through the fifth pixel via hole opened in the third flat layer 107. In this example, the electrical connection between the pixel circuit and the light-emitting element can be realized through the first transfer electrode 231 and the second transfer electrode 232.

[0090] In some examples, the gate line of the display area can be located in the first gate metal layer 109, the data line of the display area can be located in the second source-drain metal layer 112 or the third source-drain metal layer 113, and the high-potential power line of the display area can be located in at least one of the second source-drain metal layer 112 and the third source-drain metal layer 113. This embodiment is not limited to this. The circuit structure layer of this example can include three source-drain metal layers, which can avoid arranging more wiring in a single source-drain metal layer, thereby facilitating the realization of a narrow frame structure.

[0091] In some exemplary embodiments, Figure 3 As shown, the light emitting structure layer 30 may include: a pixel definition layer 304 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 301, an organic light emitting layer 302 and a second electrode 303. The first electrode 301 of the light emitting element may be an anode, and the first electrode 301 may be disposed on the third flat layer 107, and electrically connected to the second transfer electrode 232 through a fifth pixel via hole provided in the third flat layer 107. The pixel definition layer 304 is disposed on the first electrode 301 and the third flat layer 107, and the pixel definition layer 304 may be provided with a plurality of pixel openings, and one pixel opening may expose at least part of the surface of a corresponding first electrode 301. At least part of the organic light emitting layer 302 may be disposed in one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light emitting layer 302 and connected to the organic light emitting layer 302. The organic light emitting layer 302 may emit light of corresponding colors under the drive of the first electrode 301 and the second electrode 303. An isolation column layer may be further disposed on a side of the pixel definition layer 304 away from the base substrate 10 , and the isolation column layer may include a plurality of isolation columns (PS).

[0092] In some exemplary embodiments, the organic light-emitting layer 302 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0093] In some exemplary embodiments, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, Fine Metal Mask) or an open mask (Open Mask), or by inkjet technology.

[0094] In some exemplary embodiments, Figure 3 As shown, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked. Among them, the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, the second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 may be arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0095] In some exemplary embodiments, Figure 3 As shown, the touch structure layer 50 may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512 arranged in sequence. The touch buffer layer 501 may be an inorganic insulating layer, and the touch interlayer insulating layer 502 may be an inorganic insulating layer or an organic insulating layer. In this example, by setting the touch interlayer insulating layer 502 as an organic insulating layer, the crack problem generated in the reliability test of the display panel (such as the crack problem generated in the anti-arch test of the foldable display panel) can be improved, thereby improving the anti-bending ability of the display panel, which is conducive to improving the product yield and competitiveness of the display panel.

[0096] At present, the border area in the display substrate usually has a large and continuous organic protective layer. The continuous organic protective layer leads to a high film thickness and a large area of ​​the organic protective layer. The film thickness of the organic protective layer is the size of the organic protective layer in the direction perpendicular to the substrate. The applicant found that when performing high temperature and high humidity tests, when water vapor invades the organic protective layer, due to the continuity of the organic protective layer and the high film thickness, it is difficult for the water vapor to diffuse around, resulting in continuous upward diffusion of water vapor. Upward diffusion refers to the diffusion of water vapor to the side away from the substrate, affecting the stability of the film structure, thereby affecting the test results and causing reliability issues.

[0097] Figure 4 is a schematic diagram of a display substrate of this exemplary embodiment, Figure 5 for Figure 4 BB cross-section diagram, Figure 6 for Figure 4 The partial enlarged schematic diagram of point C in FIG. 1 shows a display substrate according to the exemplary embodiment. Figures 4 to 6As shown, the display substrate may include a base substrate 10, a plurality of sub-pixels Pxij, a plurality of data lines 24, a plurality of first contact pads 25, a plurality of second contact pads 26, a plurality of connection lines 27, an organic protective layer 29 and an inorganic protective layer 31. The base substrate 10 may include a display area AA and a first frame area B1 located at least on one side of the display area AA, the first frame area B1 may include a first binding area B3 and a second binding area B4, and the second binding area B4 may be located on a side of the first binding area B3 away from the display area AA. The plurality of sub-pixels Pxij are located on one side of the base substrate 10 and in the display area AA, the plurality of data lines 24 may be located in the display area AA and the first frame area B1, and the plurality of data lines 24 may be electrically connected to the plurality of sub-pixels Pxij. A plurality of first contact pads 25 may be located in the first binding region B3, and the plurality of first contact pads 25 may be configured to be bound to a driving chip (not shown in the figure). The plurality of first contact pads 25 may include at least one row of first input contact pads 251 and at least one row of first output contact pads 252. The at least one row of first input contact pads 251 may be located on a side of the at least one row of first output contact pads 252 away from the display area AA, and the plurality of data lines 24 are electrically connected to the at least one row of first output contact pads 252. A plurality of second contact pads 26 may be located in the second binding region B4, and the plurality of second contact pads 26 may be configured to be bound to a circuit board (not shown in the figure). A plurality of connecting wires 27 may be located between the at least one row of first input contact pads 251 and the plurality of second contact pads 26, and the plurality of connecting wires 27 may be for connecting the at least one row of first input contact pads 251 and the plurality of second contact pads 26. An organic protective layer 29 may be located on a side of the plurality of connecting wires 27 away from the base substrate 10, and the organic protective layer 29 is provided with at least one groove 28, and the groove 28 may penetrate the organic protective layer 29 in a direction perpendicular to the base substrate. The inorganic protective layer 31 may be located on a side of the organic protective layer 29 away from the base substrate 10 and cover at least one groove 28, and the inorganic protective layer 31 is in direct contact with at least one connecting line 27 of the plurality of connecting lines 27 through at least one groove 28. Thus, the display substrate of this example can directly block the diffusion of water vapor by providing the groove 28 in the organic protective layer 29 in the first frame area B1, and can also reduce the thickness of the organic protective layer 29, avoiding a large area of ​​continuous organic protective layer, making it difficult for water vapor to diffuse upwards and affect the stability of the organic protective layer 29, and avoiding the peeling of the organic protective layer 29 and the inorganic protective layer 31.

[0098] In some exemplary embodiments, Figures 4 to 6As shown, the base substrate 10 may include a display area AA and a frame area BB located around the display area AA. The frame area BB may include a first frame area B1 located on one side of the display area AA and a second frame area B2 located on the other sides of the display area AA. For example, the first frame area B1 may include a lower frame of the array substrate, and the second frame area B2 includes an upper frame, a left frame, and a right frame of the display substrate. The first border area B1 is located on one side of the display area AA in the first direction (Y direction), and the first direction (Y direction) is parallel to the base substrate 10. The first border area B1 may include a first binding area B3 and a second binding area B4. The second binding area B4 may be located on the side of the first binding area B3 away from the display area AA in the first direction (Y direction). The first binding area B3 may be a chip binding area, and the second binding area B4 may be a circuit board binding area. The driver chip (Display driver IC, DIC for short) can be bound to the first binding area B3 on the display substrate through a COP (Chip On Pi) process, and the flexible printed circuit (Flexible Printed Circuit, FPC for short) can be bound to the second binding area B4 on the display substrate through a FOP (FPC On COPBonding) process.

[0099] In some exemplary embodiments, Figures 4 to 6 As shown, the base substrate 10 can be a flexible substrate, which can be but is not limited to one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0100] In some exemplary embodiments, Figures 4 to 6 As shown, the plurality of first contact pads 25 may include at least one row of first input contact pads 251 and at least one row of first output contact pads 252, and the at least one row of first input contact pads 251 may be located on the side of the at least one row of first output contact pads 252 away from the display area AA. In this example, the plurality of first output contact pads 252 may be arranged in three rows, and the plurality of first output contact pads 252 in one row are arranged at intervals along the second direction (X direction), the second direction (X direction) is perpendicular to the first direction (Y direction), and the second direction (X direction) is parallel to the base substrate 10; the plurality of data lines 24 extend from the display area AA to the first binding area B3 and are electrically connected to the plurality of first output contact pads 252. In this example, the plurality of first input contact pads 251 may be arranged in one row, and the plurality of first input contact pads 251 in one row are arranged at intervals along the second direction (X direction). In this example, there are a plurality of second contact pads 26, and the plurality of second contact pads 26 may be arranged in one row, and the plurality of second contact pads 26 in one row are arranged at intervals along the second direction (X direction).

[0101] In some exemplary embodiments, Figures 4 to 6 As shown, a plurality of connection lines 27 may be located between the first input contact pads 251 and the second contact pads 26, and the plurality of connection lines 27 may be connected to at least one row of the first input contact pads 251 and a plurality of the second contact pads 26. In this example, the number of the first input contact pads 251 and the second contact pads 26 is the same, and a one-to-one correspondence may be formed, and the corresponding first input contact pads 251 and the second contact pads 26 are connected through a connection line 27, that is, one end of the connection line 27 is connected to a first input contact pad 251, and the other end of the connection line 27 is connected to a corresponding second contact pad 26. For example, the number of the first input contact pads 251, the second contact pads 26 and the connection lines 27 are all a, and the two ends of each connection line 27 are respectively connected to a first input contact pad 251 and a second contact pad 26. But not limited to this, for example, a first input contact pad 251 can be connected to multiple second contact pads 26 via a connecting line 27; for another example, multiple first input contact pads 251 can be connected to one second contact pad 26 via a connecting line 27; for another example, multiple first input contact pads 251 can be connected to multiple second contact pads 26 via a connecting line 27.

[0102] Figure 7 for Figure 5 In the partially enlarged schematic diagram at D in the middle, in some exemplary embodiments, as Figure 3 , Figure 5 , Figure 6 and Figure 7As shown, at least one of the plurality of connection lines 27 includes a first metal line 271 and a second metal line 272, the second metal line 272 is located on a side of the first metal line 271 away from the base substrate 10, and the first metal line 271 and the second metal line 272 are in direct contact and electrically connected. The display substrate may include a circuit structure layer 20 and a light emitting structure layer 30 sequentially arranged in a direction away from the base substrate 10, and the sub-pixel Pxij includes a pixel circuit, a first transfer electrode 231, a second transfer electrode 232 and a light emitting element, wherein the pixel circuit, the first transfer electrode 231 and the second transfer electrode 232 may be located in the circuit structure layer 20, the light emitting element is located in the light emitting structure layer 30, the pixel circuit is electrically connected to the light emitting element through the first transfer electrode 231 and the second transfer electrode 232, and the first transfer electrode 231 is located on a side of the second transfer electrode 232 close to the base substrate 10. The pixel circuit includes a thin film transistor 21, which includes an active layer 210, a gate 213 located on a side of the active layer 210 away from the substrate 10, and a source 211 and a drain 212 located on a side of the gate 213 away from the substrate 10, and a first transfer electrode 231 located on a side of the source 211 and the drain 212 away from the substrate 10. The first metal line 271 can be located in the same layer as the source 211 and the drain 212, that is, both are located in the first source-drain metal layer 111, and the first metal line 271 can be made of the same material as the source 211 and the drain 212; the second metal line 272 can be located in the same layer as the first transfer electrode 231, that is, both are located in the second source-drain metal layer 112, and the second metal line 272 can be made of the same material as the first transfer electrode 231.

[0103] In some exemplary embodiments, Figure 3 , Figure 5 , Figure 6 and Figure 7As shown, at least one of the plurality of connection lines 27 includes a first metal line 271 and a second metal line 272, the second metal line 272 is located on a side of the first metal line 271 away from the base substrate 10, and the first metal line 271 and the second metal line 272 are in direct contact and electrically connected. The display substrate may include a circuit structure layer 20 and a light emitting structure layer 30 sequentially arranged in a direction away from the base substrate 10, and the sub-pixel Pxij includes a pixel circuit, a first transfer electrode 231, a second transfer electrode 232 and a light emitting element, wherein the first transfer electrode 231 and the second transfer electrode 232 may be located in the circuit structure layer 20, the light emitting element is located in the light emitting structure layer 30, the pixel circuit is electrically connected to the light emitting element through the first transfer electrode 231 and the second transfer electrode 232, and the first transfer electrode 231 is located on a side of the second transfer electrode 232 close to the base substrate 10. The first metal wire 271 and the first transfer electrode 231 are located in the same layer, that is, both are located in the second source-drain metal layer 112, and the first metal wire 271 can be made of the same material as the first transfer electrode 231; the second metal wire 272 and the second transfer electrode 232 are located in the same layer, that is, both are located in the third source-drain metal layer 113, and the second metal wire 272 and the second transfer electrode 232 are made of the same material.

[0104] In some exemplary embodiments, the first metal wire 271 may be located in the same layer as the source 211 and the drain 212, that is, both are in the first source-drain metal layer 111, and the first metal wire 271 may be made of the same material as the source 211 and the drain 212; the second metal wire 272 and the second transfer electrode 232 are located in the same layer, that is, both are in the third source-drain metal layer 113, and the second metal wire 272 and the second transfer electrode 232 are made of the same material.

[0105] In some exemplary embodiments, at least one connecting line 27 among the multiple connecting lines 27 includes a first metal line 271 and a second metal line 272, and the first metal line 271 and the second metal line 272 may be located at any two layers of the first gate metal layer 109, the second gate metal layer 110, the first source-drain metal layer 111, the second source-drain metal layer 112 and the third source-drain metal layer 113.

[0106] In some exemplary embodiments, Figures 3 to 6As shown, the sub-pixel Pxij includes a pixel circuit, a first switching electrode 231, a second switching electrode 232 and a light-emitting element. The pixel circuit is electrically connected to the light-emitting element through the first switching electrode 231 and the second switching electrode 232. The circuit structure layer 20 also includes a first flat layer 105, a second flat layer 106 and a third flat layer 107. The first flat layer 105 is located on a side of the first switching electrode 231 close to the base substrate 10, the second flat layer 106 is located on a side of the first switching electrode 231 away from the base substrate 10, and the third flat layer 107 is located on a side of the second switching electrode 232 away from the base substrate 10. The pixel circuit is electrically connected to the first switching electrode 231 through a via hole in the first flat layer 105, the first switching electrode 231 is electrically connected to the second switching electrode 232 through a via hole in the second flat layer 106, and the second switching electrode 232 is electrically connected to the anode (first electrode 301) of the light-emitting element through a via hole in the third flat layer 107. In this example, the organic protection layer 29 may be located at the same layer as the second planar layer 106 and may be made of the same material, but is not limited thereto. For example, the organic protection layer 29 may be located at the same layer as the third planar layer 107 and may be made of the same material.

[0107] In some exemplary embodiments, Figure 5 and Figure 7 As shown, the groove depth direction of the groove 28 is consistent with the third direction, the third direction is perpendicular to the base substrate 10, the groove 28 penetrates the organic protective layer 29 in the third direction, the notch of the groove 28 is located at the end of the groove 28 away from the base substrate 10, and the bottom of the groove 28 is located at the end of the organic protective layer 29 close to the base substrate 10, so that the groove 28 can extend to the end of the connecting line 27 away from the base substrate 10 in the third direction, exposing the connecting line 27.

[0108] In some exemplary embodiments, Figure 5 and Figure 7As shown, there may be a plurality of grooves 28, and the grooves 28 may be long strip grooves extending along a straight line, but are not limited thereto. For example, the grooves 28 may be circular grooves, diamond grooves, fan-shaped grooves, etc. In this example, a plurality of grooves 28 are long strip grooves extending along a straight line and are parallel to each other. The grooves 28 are arranged to extend along the second direction (X direction), and the second direction (X direction) may be arranged to intersect with the first direction (Y direction), and the second direction (X direction) is parallel to the substrate 10. In this example, the second direction (X direction) is perpendicular to the first direction (Y direction), that is, the extension direction of the grooves 28 is perpendicular to the first direction (Y direction), but are not limited thereto. For example, the plurality of grooves 28 are not parallel, but the plurality of grooves 28 do not cross, and for another example, the plurality of grooves 28 are parallel to each other, and the grooves 28 are arranged to extend along the second direction (X direction), and the second direction (X direction) and the first direction (Y direction) intersect, but the second direction (X direction) and the first direction (Y direction) are not perpendicular. The groove 28 extending along the second direction (X direction) may intersect all the connection lines 27, so that the projection of the groove 28 on the base substrate 10 overlaps with the projection of all the connection lines 27 on the base substrate 10. In this example, the number of the grooves 28 may be two, and the two grooves 28 are arranged at intervals in the first direction (Y direction). The two grooves 28 may divide the organic protection layer 29 located in the first border area B1 into three protection units 291, but it is not limited thereto. For example, the number of the grooves 28 may be one, and the organic protection layer 29 located in the first border area B1 may be divided into two protection units 291; for another example, the number of the grooves 28 may be three, and the organic protection layer 29 located in the first border area B1 may be divided into four protection units 291; the number of the grooves 28 may be five, and the organic protection layer 29 located in the first border area B1 may be divided into six protection units 291.

[0109] In some exemplary embodiments, Figure 5 and Figure 7 As shown, at least one protection unit 291 may include a first body 292, and the surface of the first body 292 close to the groove 28 is an inclined surface 297, and the inclined surface 297 is inclined toward the side away from the groove 28 in the first direction (Y direction), and the inclined surface 297 constitutes the groove side wall of the groove 28. Therefore, the groove 28 can have a large opening at one end and a small opening at the other end, and the size of the groove bottom of the groove 28 (i.e., the end of the groove 28 close to the base substrate 10 in the third direction) in the first direction is smaller than the size of the groove opening of the groove 28 (i.e., the end of the groove 28 away from the base substrate 10 in the third direction) in the first direction, forming a trumpet-shaped groove, and the third direction is perpendicular to the base substrate 10.

[0110] In some exemplary embodiments, Figure 5 and Figure 7As shown, the inclined surface 297 is set to an arcuate surface, and the arcuate surface is set to protrude toward a side away from the base substrate 10. The slope angle of the inclined surface 297 is set to α, where 5°≤α≤45°. Since the inclined surface 297 is an arcuate surface, the slope angles of various positions on the inclined surface 297 are different. The slope angle of the inclined surface 297 in this example can be the angle between the tangent line of a point on the inclined surface 297 and the plane parallel to the base substrate 10. For example, the slope angle of point A on the inclined surface 297 is α1, the tangent of the inclined surface 297 passing through point A is L1, and the angle between the tangent L1 and the plane parallel to the substrate 10 is α1; for another example, the slope angle of point B on the inclined surface 297 is α2, the tangent of the inclined surface 297 passing through point B is L2, and the angle between the tangent L2 and the plane parallel to the substrate 10 is α2; the slope angle of point C on the inclined surface 297 is α3, the tangent of the inclined surface 297 passing through point C is L3, and the angle between the tangent L3 and the plane parallel to the substrate 10 is α3; wherein the angles of α1, α2 and α3 are all within the range of 5° to 45°, so that the slope angle of the inclined surface 297 is relatively small.

[0111] In some exemplary embodiments, Figure 5 and Figure 7 As shown, at least one protection unit 291 may further include a second body 293, a first body 292 is located on one side of the second body 293 close to the groove 28 in the first direction (Y direction), and the first body 292 and the second body 293 are made of the same material. The thickness of the first body 292 is the dimension of the first body 292 in the third direction, and the thickness of the second body 293 is the dimension of the second body 293 in the third direction, wherein the thickness of the first body 292 is greater than or equal to the thickness of the second body 293, and the ratio of the maximum dimension of the second body 293 in the third direction to the maximum dimension of the first body 292 in the third direction may be 1 to 1.5.

[0112] In some exemplary embodiments, Figure 5 and Figure 7As shown, the three protection units 291 include a first protection unit 294, a second protection unit 295 and a third protection unit 296, wherein the first protection unit 294, the second protection unit 295 and the third protection unit 296 are arranged in sequence in the first direction (Y direction). A groove 28 is provided between the first protection unit 294 and the second protection unit 295, and between the second protection unit 295 and the third protection unit 296, so that the first protection unit 294 and the second protection unit 295 are separated, and the second protection unit 295 and the third protection unit 296 are separated. The two grooves 28 include a first groove 281 and a second groove 282, wherein the first groove 281 is located between the second protection unit 295 and the third protection unit 296, and the second groove 282 is located between the first protection unit 294 and the second protection unit 295, and the second groove 282 is located on the side of the first groove 281 away from the display area. The first protection unit 294 is located at a side of the second protection unit 295 away from the display area AA, the third protection unit 296 is located at a side of the second protection unit 295 close to the display area AA, the first protection unit 294 includes a second body 293 and two first bodies 292 respectively located on both sides of the second body 293, the second protection unit 13 also includes a second body 293 and two first bodies 292 respectively located on both sides of the second body 293, and the third protection unit 296 includes a first body 292, so that the groove 8 is clamped by the two first bodies 292. The two grooves 28, the plurality of first bodies 292 and the plurality of second bodies 293 in the organic protection layer 29 in the frame area can be arranged in sequence according to a first order, and the first order can be the first body 292, the groove 28, the first body 292, the second body 293, the first body 292, the groove 28, the first body 292, the second body 293 and the first body 292 arranged in sequence in the first direction (Y direction).

[0113] In some exemplary embodiments, Figure 5 and Figure 7As shown, the organic protective layer 29 can be formed by a half-tone process (HalfTone Technology), that is, after forming the connecting line 27, a layer of insulating film can be covered on the connecting line 27 and the base substrate 10, and then the groove 28 and the inclined surface 297 are formed by the half-tone process (Half Tone Technology). Half-tone technology (Half Tone Technology) is a key technology used in a display device, which can control the exposure degree of the photoresist (PR) by using a semi-transparent area. It improves the picture quality and color performance by accurately controlling the exposure and etching process. Therefore, the display substrate of this example adopts the groove design of the organic protective layer 29 (that is, the groove 28 is set), reduces the volume of the organic protective layer 29, and avoids the continuous and large area of ​​the organic protective layer 29, and is divided into multiple units. At the same time, the groove 28 can also directly isolate water vapor. Secondly, the inclined surface is formed at the edge of the protective unit by the half-tone process, so as to form a smaller average film thickness of the protective unit and a smaller slope angle of the first body, so as to avoid uneven stress caused by excessive slope angle, which causes the film layer to detach. When water vapor invades, the setting of the groove 28 can directly block the diffusion of water vapor and prevent the water vapor from being transmitted along the first direction (Y direction). At the same time, during high temperature and high humidity testing, the edge of the protection unit with a thinner thickness and a smaller slope angle will also drive the invading water vapor to diffuse upward while being more likely to diffuse to the surroundings (towards the first direction or the second direction) rather than just diffusing upward, thereby ensuring the stability of the membrane structure.

[0114] In some exemplary embodiments, Figure 3 , Figure 5 and Figure 7 As shown, the display substrate includes a touch structure layer 50 located on the side of the light emitting structure layer 30 away from the base substrate 10, and the touch structure layer 50 may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502 and a second touch conductive layer 512 arranged in sequence. The inorganic protective layer 31 may be located in the same layer as the touch interlayer insulating layer 502 and have the same material. The groove 28 extends in a direction perpendicular to the base substrate 10 (the third direction) to the surface of the connecting line 27 away from the base substrate 10, so that the surface of the connecting line 27 away from the base substrate 10 is partially exposed due to the setting of the groove 28. The inorganic protective layer 31 covers the surface of the organic protective layer 29 away from the base substrate 10, and the inorganic protective layer 31 also covers the exposed portion of the connecting line 27 due to the setting of the groove 28, so that the inorganic protective layer 29 covers the groove 28, and the inorganic protective layer 29 is in direct contact with the connecting line 27 through the groove 28.

[0115] In some exemplary embodiments, a display device may include the above-mentioned display substrate. In some exemplary embodiments, the display device is a product with an image display function, such as a display, a television, a billboard, a digital photo frame, a telephone, a mobile phone, a digital camera, a portable camcorder, a navigator, a home appliance, or a device with a display function. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned display device.

[0116] In the above embodiment, the display substrate of this example adopts the groove design of the organic protective layer 29 (i.e., the groove 28 is provided) to reduce the volume of the organic protective layer 29 in the frame area, and avoids the continuous and large-area organic protective layer 29, and is divided into multiple units. An inorganic protective layer 29 is provided on the side of the groove 28 and the organic protective layer 29 away from the base substrate 10, so that the inorganic protective layer 29 is in direct contact with the connecting line 27, and the inorganic protective layer 31 is formed to cut off the organic protective layer 29, thereby cutting off the path of water vapor transmission and directly isolating water vapor. Secondly, an inclined surface is formed at the edge of the protective unit by a halftone process, thereby forming a smaller average film thickness of the protective unit and a smaller slope angle of the first body, avoiding uneven stress caused by excessive slope angle, causing the film layer to detach. At the same time, during the high temperature and high humidity test, because the groove design of the organic protective layer 29 is used, combined with the smaller thickness and slope angle of the film layer, the invading water vapor can diffuse to the surroundings, greatly reducing the water vapor diffusing upward, and reducing the impact of water vapor on the film layer structure.

[0117] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A display substrate, characterized in that: The substrate includes a display area and a first frame area located at at least one side of the display area, the first frame area includes a first binding area and a second binding area, and the second binding area is located at a side of the first binding area away from the display area; A plurality of sub-pixels are located on one side of the base substrate and in the display area; A plurality of data lines are located in the display area and the first frame area, and the plurality of data lines are electrically connected to the plurality of sub-pixels; a plurality of first contact pads, located in the first binding area, the plurality of first contact pads being configured to be bound to a driving chip, the plurality of first contact pads comprising at least one row of first input contact pads and at least one row of first output contact pads, the at least one row of first input contact pads being located on a side of the at least one row of first output contact pads away from the display area, the plurality of data lines being electrically connected to the at least one row of first output contact pads; A plurality of second contact pads, located in the second binding area, and the plurality of second contact pads are configured to be bound to the circuit board; a plurality of connection lines located between the at least one row of first input contact pads and the plurality of second contact pads, the plurality of connection lines being configured to connect the at least one row of first input contact pads and the plurality of second contact pads; An organic protective layer, located on a side of the plurality of connection lines away from the base substrate, the organic protective layer being provided with at least one groove, the groove penetrating the organic protective layer in a direction perpendicular to the base substrate; The inorganic protective layer is located on a side of the organic protective layer away from the base substrate and covers the at least one groove. The inorganic protective layer is in direct contact with at least one connecting line among the plurality of connecting lines through the at least one groove.

2. The display substrate according to claim 1, characterized in that: An extension direction of the at least one groove intersects with an extension direction of the plurality of connection lines, and an orthographic projection of the at least one groove on the base substrate overlaps with an orthographic projection of the plurality of connection lines on the base substrate; The inorganic protection layer is in direct contact with the plurality of connection lines through the at least one groove.

3. The display substrate according to claim 2, characterized in that: The at least one groove includes a first groove and a second groove, wherein the second groove is located at a side of the first groove away from the display area.

4. The display substrate according to claim 2, characterized in that: The organic protection layer includes a plurality of protection units, the plurality of protection units are located in the first frame area and are arranged sequentially in a direction away from the display area, and the at least one groove is configured to separate the plurality of protection units.

5. The display substrate according to claim 4, characterized in that: At least one of the plurality of protection units includes a first body, a surface of the first body close to the groove is an inclined surface, and the inclined surface is inclined toward one side of the groove.

6. The display substrate according to claim 5, characterized in that: The slope angle of the inclined surface is set to α, 5°≤α≤45°.

7. The display substrate according to claim 5, characterized in that: The inclined surface is configured as an arc-shaped surface, and the arc-shaped surface is configured to protrude toward a side away from the base substrate.

8. The display substrate according to claim 5, characterized in that: At least one of the protection units further includes a second body, the first body is located on a side of the second body close to the groove, and a thickness of the first body is less than or equal to a thickness of the second body.

9. The display substrate according to claim 1, characterized in that: The first input contact pad and the second contact pad are arranged in one-to-one correspondence and connected via one of the connecting lines; or, One of the first input contact pads is connected to a plurality of the second contact pads via one of the connecting lines; or, A plurality of the first input contact pads are connected to one of the second contact pads via one of the connecting lines; or, A plurality of the first input contact pads are connected to a plurality of the second contact pads via one of the connecting lines.

10. The display substrate according to claim 1, characterized in that: At least one connection line among the plurality of connection lines includes a first metal line and a second metal line, the second metal line is located on a side of the first metal line away from the substrate, and the first metal line and the second metal line are in direct contact and electrically connected.

11. The display substrate according to claim 1, characterized in that: The display substrate comprises a circuit structure layer and a light emitting structure layer which are sequentially arranged in a direction away from the base substrate; At least one sub-pixel among the plurality of sub-pixels comprises a pixel circuit, a first switching electrode and a light-emitting element, wherein the pixel circuit and the first switching electrode are located in the circuit structure layer, the light-emitting element is located in the light-emitting structure layer, and the pixel circuit is electrically connected to the light-emitting element through the first switching electrode; The circuit structure layer further includes a first flat layer and a second flat layer, wherein the first flat layer is located on a side of the first switching electrode close to the base substrate, and the second flat layer is located on a side of the first switching electrode away from the base substrate; The organic protection layer and the second planar layer are located on the same layer and are made of the same material.

12. The display substrate according to claim 11, characterized in that: The display substrate further comprises a touch control structure layer located on a side of the light emitting structure layer away from the base substrate, wherein the touch control structure layer comprises a first touch control conductive layer, a touch control interlayer insulating layer and a second touch control conductive layer which are sequentially arranged away from the base substrate; The inorganic protection layer and the touch control interlayer insulating layer are located on the same layer.

13. The display substrate according to claim 11, characterized in that: The pixel circuit includes a transistor, the transistor includes an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and the first transfer electrode is located on a side of the source and the drain away from the substrate; The connection line includes a first metal line and a second metal line which are stacked, the first metal line and the source or the drain are located in the same layer, and the second metal line and the first transfer electrode are located in the same layer.

14. The display substrate according to claim 11, characterized in that: At least one sub-pixel among the plurality of sub-pixels comprises a second switching electrode, and the first switching electrode is located on a side of the second switching electrode close to the base substrate; The connecting wire includes a first metal wire and a second metal wire which are stacked, the first metal wire and the first switching electrode are located in the same layer, and the second metal wire and the second switching electrode are located in the same layer.

15. A display device, characterized in that: It comprises the display substrate as claimed in any one of claims 1 to 14.

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