Bus system

Abstract

The utility model provides a bus system, which comprises a multiplexing interface, a bus, a frequency detection module and a driving module, and the multiplexing interface has a predetermined communication mode. According to the utility model, the clock frequency of the first clock signal transmitted on the bus is detected by arranging the frequency detection module, and the corresponding first setting signal is output according to the clock frequency of the first clock signal, so that the multiplexing interface enters a predetermined communication mode. According to the utility model, no extra interface or pin needs to be arranged to input a corresponding instruction so as to drive the multiplexing interface to enter a predetermined communication mode, and the chip resource design is saved. In addition, the arrangement of the frequency detection module can also ensure that the multiplexing interface autonomously enters a predetermined communication mode.

Description

Technical Field

[0001] The utility model relates to the technical field of communication, in particular to a bus system. Background Art

[0002] I2C (Inter-Integrated Circuit) is a serial communication bus standard that uses two wires (clock line and data line) to transmit data. This communication mode allows data transfer and control between two devices. The clock line is controlled by the host and is used to synchronize data transmission, while the data line is used to transmit the actual data. I2C is a half-duplex communication mode, which means that only one device can send a signal on the data line at the same time.

[0003] In the prior art, an additional interface or pin is usually required to input corresponding control instructions so that the functional interface enters or exits the I2C mode, which increases the chip resource design cost. In addition, the functional interface cannot autonomously enter the I2C mode by inputting control instructions. Utility Model Content

[0004] The utility model aims to provide a bus system to solve the problem that the device in the prior art needs an additional interface to input I2C control instructions, which increases chip design resources and the prior art cannot enter the I2C mode autonomously.

[0005] In order to solve the above technical problems, the utility model provides a bus system, which includes:

[0006] a multiplexing interface having a predetermined communication mode;

[0007] A bus connected to the multiplexing interface, wherein the working mode of the bus is adapted to the predetermined communication mode;

[0008] A frequency detection module connected to the bus, the frequency detection module being used to detect a clock frequency of a first clock signal transmitted on the bus;

[0009] A driving module connected to the multiplexing interface and the frequency detection module, the driving module is used to output a first setting signal adapted to the clock frequency, the first setting signal is used to enable the multiplexing interface to enter the predetermined communication mode.

[0010] Optionally, the bus system also includes a register and a controller, the register is connected to the controller, the controller is connected to the multiplexing interface and the driving module, and the controller is used to drive the driving module to flip the first set signal to a second set signal, and the second set signal enables the multiplexing interface to exit the predetermined communication mode.

[0011] Optionally, the first set signal is one of a high level and a low level, and the second set signal is the other of a high level and a low level.

[0012] Optionally, the predetermined communication mode includes an I2C mode, and the bus includes a serial data line and a serial clock line.

[0013] Optionally, at least one of the serial data line and the serial clock line transmits the first clock signal.

[0014] Optionally, the clock frequency is greater than the operating frequency of the multiplexing interface.

[0015] Optionally, the driving module is used to output the first setting signal when the clock frequency of the first clock signal is greater than or equal to a frequency setting value.

[0016] Optionally, the frequency detection module includes:

[0017] a signal input device connected to the bus, the signal input device being used to filter out the first clock signal;

[0018] A first counter connected to the signal input device, the first counter is used to count pulses of the first clock signal, and the first counter is used to drive the driving module to output the first setting signal when the counted number of pulses is greater than or equal to a first threshold.

[0019] Optionally, the frequency detection module further includes a second counter connected to the first counter, the second counter being used to count pulses of the second clock signal, and the second counter being used to reset when the counted number of pulses is greater than or equal to a second threshold, and to drive the first counter to reset;

[0020] A product of a period of the first clock signal and the first threshold is smaller than a product of a period of the second clock signal and the second threshold.

[0021] Optionally, the driving module includes an RS trigger.

[0022] In summary, in the bus system provided by the utility model, the bus system includes a multiplexing interface, a bus, a frequency detection module and a driving module, the multiplexing interface has a predetermined communication mode; the working mode of the bus is adapted to the predetermined communication mode, and the bus is used to transmit a first clock signal; the frequency detection module is used to detect the clock frequency of the first clock signal; the driving module connected to the multiplexing interface and the frequency detection module, the driving module is used to output a first setting signal adapted to the clock frequency of the first clock signal, and the first setting signal is used to enable the multiplexing interface to enter a predetermined communication mode. The predetermined communication mode includes an I2C mode. In this way, the utility model detects the clock frequency of the first clock signal transmitted on the bus by setting a frequency detection module, and outputs a corresponding first setting signal according to the clock frequency of the first clock signal, so that the multiplexing interface enters a predetermined communication mode. Compared with the prior art, the utility model does not need to set an additional interface or pin to input a corresponding instruction to drive the multiplexing interface to enter a predetermined communication mode, saving chip resource design. In addition, the setting of the frequency detection module can also ensure that the multiplexing interface can autonomously enter a predetermined communication mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Those skilled in the art should understand that the drawings provided are for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0024] Figure 1 is a schematic diagram of a bus system according to an embodiment of the utility model;

[0025] Figure 2 It is a schematic diagram of a frequency detection module according to an embodiment of the present utility model.

[0026] In the attached figure:

[0027] 10-multiplexing interface; 20-driving module; 30-frequency detection module; 31-signal input device; 32-first counter; 33-second counter; 40-register; 50-controller. DETAILED DESCRIPTION

[0028] In order to make the purpose, advantages and features of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0029] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which not only include the endpoints, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element may be in any orientation such as inside, outside, above, below or on one side of another element, unless otherwise clearly indicated in the content. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] Figure 1 Schematic diagram of a bus system according to an embodiment of the present utility model. Figure 1As shown, an embodiment of the utility model schematically provides a bus system, and the bus system includes a multiplexing interface 10, a bus, a frequency detection module 30 and a driving module 20. The multiplexing interface 10 has a communication mode of multiple interfaces, that is, multiplexing of multiple interfaces, for example, the multiplexing interface 10 has a communication mode of an IO interface and a communication mode of an I2C interface. Further, one of the communication modes of the multiplexing interface 10 is used as a predetermined communication mode, for example, the I2C mode is used as a predetermined communication mode. The bus is connected to the multiplexing interface 10, and the working mode of the bus is adapted to the predetermined communication mode, for example, the predetermined communication mode is the I2C mode, and the working mode of the bus is adapted to the I2C communication mode, thereby realizing I2C communication. It can be understood by those skilled in the art that when the predetermined communication mode is the I2C mode, the bus includes a serial data line SDA and a serial clock line SCL. In addition to transmitting signals or data adapted to the predetermined communication mode, the bus also transmits a first clock signal Clk1, and when the predetermined communication mode is the I2C mode, at least one of the serial data line SDA and the serial clock line SCL transmits the first clock signal Clk1. The frequency detection module 30 is connected to the bus, and the frequency detection module 30 is used to detect the clock frequency of the first clock signal Clk1. The driving module 20 is connected to the multiplexing interface 10 and the frequency detection module 30, and the driving module 20 outputs a signal SEN to the multiplexing interface 10. The driving module 20 is used to output a first set signal adapted to the clock frequency of the first clock signal Clk1 (that is, the signal SEN at this time is a first set signal), and the first set signal is used to enable the multiplexing interface 10 to enter the predetermined communication mode. In one embodiment, the driving module 20 includes an RS trigger. In one embodiment, the driving module 20 is used to output a first setting signal adapted to the clock frequency of the first clock signal Clk1. It can be understood that the driving module 20 outputs the first setting signal when the clock frequency of the first clock signal Clk1 is greater than or equal to the frequency setting value.

[0031] It should be noted that the clock frequency of the first clock signal Clk1 is greater than the operating frequency of the multiplexing interface 10, that is, the clock frequency of the first clock signal Clk1 needs to be greater than the operating frequency of the multiplexing interface 10 operating under the common interface function, so that the frequency detection module 30 can accurately screen out the first clock signal Clk1 transmitted on the bus. Exemplarily, the operating frequency of the multiplexing interface 10 is 0 to 100 MHz, the frequency in the predetermined communication mode is 0 to 1 MHz, and the clock frequency of the first clock signal Clk1 is greater than 100 MHz, so the frequency setting value can be set to be greater than 100 MHz.

[0032] Thus, the utility model detects the clock frequency of the first clock signal Clk1 transmitted on the bus by setting the frequency detection module 30, and outputs the corresponding first setting signal according to the clock frequency of the first clock signal Clk1, so that the multiplexing interface 10 enters the predetermined communication mode. Compared with the prior art, the utility model does not need to set additional interfaces or pins to input corresponding instructions to drive the multiplexing interface 10 to enter the predetermined communication mode, saving chip resource design. In addition, the setting of the frequency detection module 30 can also ensure that the multiplexing interface 10 enters the predetermined communication mode autonomously.

[0033] Furthermore, the bus system also includes a register 40 and a controller 50, the register 40 is connected to the controller 50, the controller 50 is connected to the multiplexing interface 10 and the driving module 20, and the controller 50 is used to drive the driving module 20 to flip the first set signal to the second set signal (that is, the signal SEN at this time is the second set signal), and the second set signal enables the multiplexing interface 10 to exit the predetermined communication mode. The register 40 reads and writes the data transmitted by the bus. When the data reading and writing is completed, the controller 50 can send an exit instruction (QUIT) to the driving module 20, thereby enabling the driving module 20 to flip the first set signal to the second set signal.

[0034] Exemplarily, the first setting signal is one of a high level and a low level, and the second setting signal is the other of a high level and a low level.

[0035] Figure 2 FIG. 1 is a schematic diagram of a frequency detection module according to an embodiment of the present invention. Figure 2 The frequency detection module 30 includes a signal input device 31 and a first counter 32. The signal input device 31 is connected to the bus and is used to filter out the first clock signal Clk1. The first counter 32 is connected to the signal input device 31 and is used to count the pulses of the first clock signal Clk1. The first counter 32 is used to drive the driving module 20 to output a first set signal when the counted number of pulses is greater than or equal to a first threshold.

[0036] Furthermore, the frequency detection module 30 further includes a second counter 33 connected to the first counter 32, the second counter 33 is used to count the pulses of the second clock signal Clk2, and the second counter 33 is used to reset when the counted number of pulses is greater than or equal to the second threshold value, and to drive the first counter 32 to reset. The first counter 32 and the second counter 33 start working at the same time, the second clock signal Clk2 is used as a reference clock, and the second counter 33 is set to reset the first counter 32, so that the first counter 32 can be reset after the counted number of pulses reaches or exceeds the first threshold value, and the next counting work can be started. It should be noted that the product of the period of the first clock signal Clk1 and the first threshold is smaller than the product of the period of the second clock signal Clk2 and the second threshold, so as to ensure that when the pulse count of the first counter 32 reaches the first threshold, the pulse count of the second counter 33 has not reached the second threshold, so that the first counter 32 can normally drive the driving module 20 to output the first set signal. Otherwise, the pulse count of the first counter 32 has not reached the first threshold, and the pulse count of the second counter 33 has reached the second threshold, causing the second counter 33 to reset the first counter 32 in advance, and then the first counter 32 will never be able to drive the driving module 20 to output the first set signal.

[0037] Although the utility model is disclosed as above with preferred embodiments, the above embodiments are not intended to limit the utility model. For any technician familiar with the art, without departing from the scope of the technical solution of the utility model, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the utility model, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model still falls within the scope of protection of the technical solution of the utility model.

Claims

1. A bus system, characterized in that: include: a multiplexing interface having a predetermined communication mode; A bus connected to the multiplexing interface, wherein the working mode of the bus is adapted to the predetermined communication mode; A frequency detection module connected to the bus, the frequency detection module being used to detect a clock frequency of a first clock signal transmitted on the bus; A driving module connected to the multiplexing interface and the frequency detection module, the driving module is used to output a first setting signal adapted to the clock frequency of the first clock signal, and the first setting signal is used to enable the multiplexing interface to enter the predetermined communication mode.

2. The bus system according to claim 1, characterized in that: The bus system also includes a controller, which is connected to the multiplexing interface and the driving module. The controller is used to drive the driving module to flip the first set signal into a second set signal, and the second set signal enables the multiplexing interface to exit the predetermined communication mode.

3. The bus system according to claim 2, characterized in that: The first setting signal is one of a high level and a low level, and the second setting signal is the other of a high level and a low level.

4. The bus system according to claim 1, characterized in that: The predetermined communication mode includes an I2C mode, and the bus includes a serial data line and a serial clock line.

5. The bus system according to claim 4, characterized in that: At least one of the serial data line and the serial clock line transmits the first clock signal.

6. The bus system according to claim 1, characterized in that: The clock frequency is greater than the operating frequency of the multiplexing interface.

7. The bus system according to claim 1, characterized in that: The driving module is used to output the first setting signal when the clock frequency of the first clock signal is greater than or equal to a frequency setting value.

8. The bus system according to claim 7, characterized in that: The frequency detection module comprises: a signal input device connected to the bus, the signal input device being used to filter out the first clock signal; A first counter connected to the signal input device, the first counter is used to count pulses of the first clock signal, and the first counter is used to drive the driving module to output the first setting signal when the counted number of pulses is greater than or equal to a first threshold.

9. The bus system according to claim 8, characterized in that: The frequency detection module further includes a second counter connected to the first counter, the second counter being used to count pulses of the second clock signal, and the second counter being used to reset when the counted number of pulses is greater than or equal to a second threshold value, and driving the first counter to reset; A product of a period of the first clock signal and the first threshold is smaller than a product of a period of the second clock signal and the second threshold.

10. The bus system according to claim 1, characterized in that: The driving module includes an RS trigger.

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