Array substrate and display device

Abstract

The utility model provides an array substrate and a display device. The array substrate comprises pixels, a plurality of first data lines, a plurality of second data lines, a gate drive circuit and a plurality of scanning lines, wherein the pixels are arranged on a substrate in an array mode. The plurality of first data lines are respectively connected with odd-numbered rows of pixels in each column of pixels; the plurality of second data lines are respectively connected with even-numbered rows of pixels in each column of pixels; the gate driving circuit comprises an output end connected with each row of pixel group, each scanning line is connected with the odd-numbered row of pixels and the even-numbered row of pixels in the corresponding row of pixel group, and the scanning lines are further connected with the output end of the corresponding gate driving circuit. Therefore, the number of pixels on each data line can be reduced, and the voltage drop of the data line is reduced. And the number of output ends of the gate drive circuit can be reduced, so that the charging time of each row of pixels is prolonged under the same resolution.

Description

Technical Field

[0001] The utility model relates to the technical field of display, in particular to an array substrate and a display device. Background Art

[0002] With the development of economy, people are pursuing higher and higher specifications of display products, and higher and higher resolution has become the basic specification requirement for the development of future display products. However, with the improvement of resolution, especially the increasing vertical resolution of the display screen, some liquid crystal display (LCD) products have the problem of insufficient charging during design, which affects the trend of display products to develop towards high resolution. At present, conventional LCD products, especially the low-cost A-si display products, cannot meet customers' demand for high resolution, so customers need to use high-cost process technology products to meet future development trends.

[0003] Therefore, how to increase the pixel charging time under the requirement of high resolution is a technical problem that needs to be solved urgently by those skilled in the art. Utility Model Content

[0004] In order to solve the above problems, the utility model inventor found the cause of the problem through research and development and formed a solution.

[0005] In a first aspect, the utility model provides an array substrate, the array substrate comprising:

[0006] Pixels arranged in an array on a substrate;

[0007] A plurality of first data lines are respectively connected to the odd-numbered rows of pixels in each column of pixels arranged in the array;

[0008] A plurality of second data lines are respectively connected to the even-numbered rows of pixels in each column of pixels arranged in the array;

[0009] A gate drive circuit, comprising an output terminal connected to each row pixel group; wherein each row pixel group comprises a row of odd-numbered row pixels and a row of even-numbered row pixels;

[0010] A scan line connected to the row of odd-numbered pixels and the row of even-numbered pixels in each row pixel group, wherein the scan line is also connected to an output end of the corresponding gate drive circuit.

[0011] Furthermore, in the array substrate described above, the row of odd-numbered pixels and the row of even-numbered pixels are two adjacent rows of pixels.

[0012] Furthermore, in the above array substrate, the first data line and the second data line are respectively located on both sides of a corresponding column of pixels.

[0013] Furthermore, in the array substrate described above, the scan line includes a first scan line shared by the row of odd-numbered pixels and the row of even-numbered pixels;

[0014] The first scanning line is connected to an output end of the corresponding gate driving circuit.

[0015] Further, in the array substrate described above, the scan lines include a second scan line corresponding to the row of odd-numbered pixels, and a third scan line corresponding to the row of even-numbered pixels;

[0016] All the second scan lines and the third scan lines are respectively connected to the output ends of the corresponding gate driving circuits.

[0017] Furthermore, in the above-mentioned array substrate, one end of the scan line is connected to the output end of the corresponding gate driving circuit.

[0018] Furthermore, in the above-mentioned array substrate, both ends of the scanning line are connected to the output ends of the corresponding gate driving circuit.

[0019] Furthermore, the array substrate described above further includes:

[0020] Display area;

[0021] a first binding area located on one side of the display area and a second binding area located on the other side of the display area;

[0022] Wherein, a first source driving circuit is arranged in the first binding area, and a second source driving circuit is arranged in the second binding area;

[0023] Some of the data lines consisting of the multiple first data lines and the multiple second data lines extend to the first binding area and are connected to the first source driving circuit; another part of the data lines extends to the second binding area and is connected to the second source driving circuit.

[0024] Furthermore, in the array substrate described above, the plurality of first data lines extend to the first binding area and are connected to the first source driving circuit;

[0025] The plurality of second data lines extend to the second binding region and are connected to the second source driving circuit.

[0026] In a second aspect, the utility model provides a display device, which includes any one of the array substrates described above.

[0027] The above one or more technical solutions of the utility model have at least one or more of the following beneficial effects:

[0028] When implementing the technical solution of the utility model, the number of pixels on each data line is reduced by connecting the odd-numbered rows of pixels and the even-numbered rows of pixels in each column of pixels to their respective data lines, thereby reducing the voltage drop of the data lines. In addition, a row of odd-numbered rows of pixels and a row of even-numbered rows of pixels are divided into the same row of pixel groups, and each row of pixel groups is connected to the output end of the corresponding gate drive circuit, thereby reducing the number of output ends of the gate drive circuit, thereby increasing the charging time of each row of pixels at the same resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] With reference to the accompanying drawings, the disclosure of the present invention will become easier to understand. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In addition, similar numbers in the drawings are used to represent similar components, where:

[0030] Figure 1 It is a schematic diagram of the structure of an array substrate in a high frame rate LCD product;

[0031] Figure 2 is a structural schematic diagram of a first array substrate provided according to an embodiment of the utility model;

[0032] Figure 3 is a structural schematic diagram of a second array substrate provided according to an embodiment of the utility model;

[0033] Figure 4 is a structural schematic diagram of a third array substrate provided according to an embodiment of the utility model;

[0034] Figure 5 It is a structural schematic diagram of a fourth array substrate provided according to an embodiment of the utility model. DETAILED DESCRIPTION

[0035] In order to make the above-mentioned purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the utility model. However, the utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the utility model, so the utility model is not limited by the specific embodiments disclosed below.

[0036] In the description of the present utility model, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, in the present utility model, unless otherwise clearly specified and defined, the terms "connected", "connected", and the like should be understood in a broad sense. For example, it can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to the specific circumstances.

[0037] In the description of the present invention, it should be understood that the terms "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0038] Figure 1 This is a schematic diagram of the structure of an array substrate in a high frame rate LCD product. Figure 1 As shown, the array substrate includes pixels P arranged in an array on a substrate (such as M rows and N columns), a gate driving circuit (not shown in the figure), a data line connected to each column of pixels P, and a scan line connected to each row. Each data line is denoted as Si, i=1, 2...N, and each scan line is also connected to the gate driving circuit respectively, wherein the output end of the gate driving circuit corresponding to each scan line is denoted as Gj, j=1, 2...M. However, due to the excessively high gate scanning frequency of this array substrate, the opening time of the thin-film transistor (TFT) in the pixel P is shortened, resulting in insufficient charging. As the specifications of LCD products become larger and larger, the insufficient charging phenomenon becomes more and more serious, requiring customers to use high-cost process technology products to meet future development trends. For example, for Figure 1 In terms of the arrangement, taking a product with a resolution of 1920RGB*3840 and a refresh rate of 60HZ as an example, its theoretical charging time is 4.34us. In the design of the array substrate, 5760 data lines are required, and the gate drive circuit needs to have 3840 output terminals to provide scanning signals to the gate of each row of pixels.

[0039] Therefore, in order to achieve high resolution at a lower cost and increase the charging time of the pixel P, the utility model provides the following technical solutions:

[0040] Figure 2 is a schematic structural diagram of a first array substrate provided according to an embodiment of the utility model, such as Figure 2 As shown, the array substrate of this embodiment includes pixels P arranged in an array on a substrate, a plurality of first data lines, a plurality of second data lines, a gate driving circuit and a plurality of scanning lines.

[0041] In a specific implementation process, the array of pixels P may include M rows of pixels P and N columns of pixels P. The odd rows of pixels in each column of pixels P may be connected to the corresponding first data lines, and the even rows of pixels in each column of pixels P may be connected to the corresponding second data lines. Each first data line may be denoted as Sm, where m=1, 3, 5...2N-1, and each second data line may be denoted as Sn, where n=2, 4, 6...2N. That is, two data lines are set for each column of pixels P, respectively. Figure 1 The data lines in the array are doubled, and each data line connects half of the pixels P in each column of pixels P. In this way, the number of pixels P on each data line is relatively small, and the voltage drop of each data line is also reduced, thereby making the light emission of each pixel P relatively uniform.

[0042] For M rows of pixels P, any row of odd-numbered pixels and any row of even-numbered pixels can be divided into a row of pixel groups. In this embodiment, a row of odd-numbered pixels and a row of even-numbered pixels are taken as two adjacent rows of pixels P as an example for explanation. Among them, a row of odd-numbered pixels and a row of even-numbered pixels in each row of pixel groups are connected to corresponding scan lines, and the corresponding scan lines of each row of pixel groups are connected to the output end of the corresponding gate drive circuit, wherein the output end of the gate drive circuit corresponding to each row of pixel groups can be recorded as Gk, k = 1, 2, 3 ... M / 2. Among them, Figure 2 The single-sided driving is used as an example for explanation, that is, only one end of the scanning line is connected to the output end of the gate driving circuit.

[0043] Through the layout of the above scanning lines, the output terminal of the gate drive circuit is relative to Figure 1 The solution is halved, and one output end of the gate drive circuit can refresh two rows of pixels P. Taking the product with 1920RGB*3840 resolution and 60HZ refresh rate as an example, Figure 2 After the structure is adopted, the theoretical charging time is 8.68us. In the design of the array substrate, 11520 data lines (2N) are required, and 1920 output ends of the gate drive circuit are required (M / 2). In other words, at the same refresh rate, the charging time is extended by half. On the contrary, if the technical solution of the utility model is adopted under the same charging time, the refresh rate can be doubled.

[0044] In the array substrate of this embodiment, the number of pixels P on each data line is reduced by connecting the odd-numbered rows of pixels and the even-numbered rows of pixels in each column of pixels P to their respective data lines, thereby reducing the voltage drop of the data lines. In addition, a row of odd-numbered rows of pixels and a row of even-numbered rows of pixels are divided into the same row of pixel groups, and each row of pixel groups is connected to the output end of the corresponding gate driving circuit, thereby reducing the number of output ends of the gate driving circuit, thereby increasing the charging time of each row of pixels P at the same resolution.

[0045] In a specific implementation process, Figure 2 As shown, the first data line and the second data line are respectively located on both sides of the corresponding column pixel P, such as the first data line is located on the left side of the corresponding column pixel P, and the second data line is located on the right side of the column pixel P, and this arrangement is performed for each column pixel P in turn, to obtain Figure 2 In this way, the layout of the data lines can be relatively simplified.

[0046] like Figure 2 As shown, Figure 2 In the example, a first scan line is shared by a row of odd-numbered pixels and a row of even-numbered pixels in each row pixel group, and the first scan line is connected to the output terminal of the corresponding gate driving circuit. For example, the first first scan line is connected to the first output terminal G1 of the gate driving circuit, the second first scan line is connected to the first output terminal G2 of the gate driving circuit, and so on, the M / 2th first scan line is connected to the first output terminal G(M / 2) of the gate driving circuit.

[0047] Figure 3 is a schematic structural diagram of a second array substrate provided according to an embodiment of the utility model, such as Figure 3 As shown, combined with Figure 2 It can be seen that Figure 3 The embodiment shown and Figure 2 The difference between the embodiments shown is that the array substrate drives the pixels P in a left-right odd-even alternating driving mode, that is, both ends of the scanning line are connected to the output ends of the corresponding gate driving circuit. Figure 2 The relevant records will not be repeated here.

[0048] Figure 4 is a schematic structural diagram of a third array substrate provided according to an embodiment of the utility model. Figure 4 As shown, combined with Figure 2 It can be seen that Figure 4 The embodiment shown and Figure 2The difference between the illustrated embodiments is that the row of odd-numbered pixels and the row of even-numbered pixels in each row pixel group have respective connected scan lines, and the respective scan lines are respectively connected to the output terminals of the corresponding gate drive circuits. That is, the scan lines include the second scan lines corresponding to the row of odd-numbered pixels and the third scan lines corresponding to the row of even-numbered pixels; all the second scan lines and the third scan lines are respectively connected to the output terminals of the corresponding gate drive circuits. That is, the first second scan line and the first third scan line are both connected to the first output terminal G1 of the gate drive circuit, the second second scan line and the second third scan line are both connected to the first output terminal G2 of the gate drive circuit, and so on, the M / 2th second scan line and the M / 2th third scan line are both connected to the first output terminal G(M / 2) of the gate drive circuit. For other related content, please refer to Figure 2 The relevant records will not be repeated here.

[0049] Figure 5 is a schematic structural diagram of a fourth array substrate provided according to an embodiment of the utility model, such as Figure 5 As shown, combined with Figure 4 It can be seen that Figure 5 The embodiment shown and Figure 4 The difference between the embodiments shown is that the array substrate drives the pixels P in a left-right odd-even alternating driving mode, that is, both ends of the scanning line are connected to the output ends of the corresponding gate driving circuit. Figure 4 The relevant records will not be repeated here.

[0050] In a specific implementation process, Figures 2 to 5 As shown, the array substrate further includes a display area AA, a first binding area B1, and a second binding area B2. The first binding area B1 is located on one side of the display area AA, and the second binding area B2 is located on the other side of the display area AA. A first source driving circuit (not shown in the figure) is disposed in the first binding area B1, and a second source driving circuit (not shown in the figure) is disposed in the second binding area B2.

[0051] In a specific implementation process, part of all the data lines consisting of the plurality of first data lines and the plurality of second data lines are extended to the first binding area B1 to be connected to the first source drive circuit; another part of all the data lines are extended to the second binding area B2 to be connected to the second source drive circuit. That is to say, since the number of data lines is doubled, setting the binding area only on one side of the display area AA may not meet the connection requirements of the data lines. Therefore, the first binding area B1 and the second binding area B2 can be respectively set on the opposite sides of the display area AA, so that part of the data lines in all the scan lines can be extended to the first binding area B1 to be connected to the first source drive circuit, and another part of the data lines in all the data lines can be extended to the second binding area B2 to be connected to the second source drive circuit. In this embodiment, the plurality of first data lines can be extended to the first binding area B1 to be connected to the first source drive circuit; and the plurality of second data lines can be extended to the second binding area B2 to be connected to the second source drive circuit.

[0052] Furthermore, the utility model also provides an array display device, which includes the array substrate of the above embodiment.

[0053] So far, the technical solution of the present invention has been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: include: Pixels arranged in an array on a substrate; A plurality of first data lines are respectively connected to the odd-numbered rows of pixels in each column of pixels arranged in the array; A plurality of second data lines are respectively connected to the even-numbered rows of pixels in each column of pixels arranged in the array; A gate drive circuit, comprising an output terminal connected to each row pixel group; wherein each row pixel group comprises a row of odd-numbered row pixels and a row of even-numbered row pixels; A scan line connected to the row of odd-numbered pixels and the row of even-numbered pixels in each row pixel group, wherein the scan line is also connected to an output end of the corresponding gate drive circuit.

2. The array substrate according to claim 1, characterized in that: The row of odd-numbered pixels and the row of even-numbered pixels are two adjacent rows of pixels.

3. The array substrate according to claim 2, characterized in that: The first data line and the second data line are respectively located at two sides of a corresponding column of pixels.

4. The array substrate according to claim 1, characterized in that: The scan line comprises a first scan line shared by the row of odd-numbered pixels and the row of even-numbered pixels; The first scanning line is connected to an output end of the corresponding gate driving circuit.

5. The array substrate according to claim 1, characterized in that: The scan lines include a second scan line corresponding to the row of odd-numbered pixels, and a third scan line corresponding to the row of even-numbered pixels; All the second scan lines and the third scan lines are respectively connected to the output ends of the corresponding gate driving circuits.

6. The array substrate according to claim 1, characterized in that: One end of the scanning line is connected to the output end of the corresponding gate driving circuit.

7. The array substrate according to claim 1, characterized in that: Both ends of the scanning line are connected to the output ends of the corresponding gate driving circuit.

8. The array substrate according to claim 1, characterized in that: Also includes: Display area; a first binding area located on one side of the display area and a second binding area located on the other side of the display area; Wherein, a first source driving circuit is arranged in the first binding area, and a second source driving circuit is arranged in the second binding area; Some of the data lines consisting of the multiple first data lines and the multiple second data lines extend to the first binding area and are connected to the first source driving circuit; another part of the data lines extends to the second binding area and is connected to the second source driving circuit.

9. The array substrate according to claim 8, characterized in that: The plurality of first data lines extend to the first binding area and are connected to the first source driving circuit; The plurality of second data lines extend to the second binding region and are connected to the second source driving circuit.

10. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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