Display device for vehicle and vehicle including the same

Abstract

A display device for a vehicle and a vehicle including the same are provided. A display device for a vehicle includes a substrate; a light emitting element layer disposed on the substrate and including a pixel electrode, an organic layer, and a common electrode; a pixel defining layer disposed on the substrate and including a plurality of openings exposing portions of the pixel electrode; an encapsulation layer disposed on the light emitting element layer; a metal oxide layer disposed on or in the encapsulation layer and overlapping the pixel defining layer; a light blocking layer disposed on and overlapping the metal oxide layer; and a color filter layer disposed on the light blocking layer and the encapsulation layer.

Description

Technical Field

[0001] Embodiments relate to a display device for a vehicle and a vehicle including the display device. Background Art

[0002] As the information society develops, the demand for display devices for displaying images increases in various forms. The display device may be a flat panel display such as a liquid crystal display, a field emission display, or a light-emitting display device. The light-emitting display device may include an organic light-emitting diode display device including an organic light-emitting diode element as a light-emitting element or an inorganic light-emitting diode display device including an inorganic light-emitting diode element such as a light-emitting diode (LED) as a light-emitting element.

[0003] A display device for a vehicle may include a polarizing plate for preventing outgassing of an organic film inside the display device due to ultraviolet rays incident from the outside. The polarizing plate may be attached to the outer surface of the display device, but the manufacturing cost and time required to attach the polarizing plate may reduce productivity. Therefore, research on a display device for a vehicle that can omit the polarizing plate is being conducted. Utility Model Content

[0004] Embodiments provide a display device for a vehicle capable of omitting a polarizing plate and blocking ultraviolet rays and a vehicle including the display device.

[0005] However, the embodiments of the present disclosure are not limited to those described herein. The above and other embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0006] According to one aspect of the present disclosure, a display device for a vehicle may include a substrate; a light-emitting element layer arranged on the substrate and including a pixel electrode, an organic layer and a common electrode; a pixel defining layer arranged on the substrate and including a plurality of openings exposing portions of the pixel electrode; an encapsulation layer arranged on the light-emitting element layer; a metal oxide layer arranged on or in the encapsulation layer and overlapping with the pixel defining layer; a light-blocking layer arranged on the metal oxide layer and overlapping with the metal oxide layer; and a color filter layer arranged on the light-blocking layer and the encapsulation layer.

[0007] In an implementation, the metal oxide layer may contact an upper surface of the encapsulation layer and a lower surface of the light blocking layer.

[0008] In an embodiment, the metal oxide layer may include at least one of titanium oxide, zinc oxide, and tantalum oxide.

[0009] In an embodiment, the metal oxide layer may have a thickness of about 10 nm to about 10000 nm.

[0010] In an embodiment, the metal oxide layer may include a plurality of opening holes overlapping the plurality of openings of the pixel defining layer.

[0011] In an embodiment, a size of each of the plurality of opening holes of the metal oxide layer and a size of each of the plurality of openings of the pixel defining layer may be substantially the same as each other.

[0012] In an embodiment, a size of each of the plurality of opening holes of the metal oxide layer may be larger than a size of each of the plurality of openings of the pixel defining layer, and a width of the metal oxide layer may be smaller than a width of the pixel defining layer.

[0013] In an implementation, a side surface of the metal oxide layer may be disposed inwardly of a side surface of the light blocking layer, and the light blocking layer may cover an upper surface and a side surface of the metal oxide layer.

[0014] In an embodiment, the light blocking layer may include a plurality of holes overlapping the plurality of openings of the pixel defining layer, and a size of each of the plurality of opening holes of the metal oxide layer may be greater than a size of each of the plurality of holes of the light blocking layer.

[0015] In an embodiment, the light blocking layer may include a plurality of holes overlapping the plurality of openings of the pixel defining layer, and a size of each of the plurality of opening holes of the metal oxide layer may be smaller than a size of each of the plurality of holes of the light blocking layer.

[0016] In an implementation, a side surface of the metal oxide layer may protrude outwardly than a side surface of the light blocking layer, and a width of the metal oxide layer may be greater than a width of the light blocking layer.

[0017] In an embodiment, the light blocking layer may include a plurality of holes overlapping the plurality of openings of the pixel defining layer, and a size of each of the plurality of opening holes of the metal oxide layer and a size of each of the plurality of holes of the light blocking layer may be substantially the same as each other.

[0018] In an embodiment, a side surface of the metal oxide layer may be aligned with a side surface of the light blocking layer.

[0019] In an embodiment, the pixel defining layer may include a plurality of pixel openings arranged between adjacent pixel electrodes, and the light blocking layer may include a plurality of pattern openings overlapping the plurality of pixel openings.

[0020] In an embodiment, a side of the metal oxide layer may be aligned with a side of the pixel defining layer, and a width of the metal oxide layer and a width of the pixel defining layer may be substantially the same as each other.

[0021] According to one aspect of the present disclosure, a vehicle including an instrument panel and a display device for the vehicle arranged on the instrument panel to display information may be provided. The display device may include a substrate; a light emitting element layer arranged on the substrate and including a pixel electrode, an organic layer and a common electrode; a pixel defining layer arranged on the substrate and including a plurality of openings exposing portions of the pixel electrode; an encapsulation layer arranged on the light emitting element layer; a metal oxide layer arranged in or on the encapsulation layer and overlapping the pixel defining layer; a light blocking layer arranged on the encapsulation layer and overlapping the metal oxide layer; and a color filter layer arranged on the light blocking layer and the encapsulation layer.

[0022] In an embodiment, the encapsulation layer may include a first encapsulation layer disposed on the light emitting element layer, a second encapsulation layer disposed on the first encapsulation layer, and a third encapsulation layer disposed on the second encapsulation layer.

[0023] In an embodiment, the metal oxide layer may be disposed between the second encapsulation layer and the third encapsulation layer.

[0024] In an embodiment, the metal oxide layer may be disposed between the first encapsulation layer and the second encapsulation layer.

[0025] In an embodiment, the metal oxide layer may include at least one of titanium oxide, zinc oxide, and tantalum oxide.

[0026] According to the display device for a vehicle and the vehicle including the display device according to the embodiment, by arranging the metal oxide layer that absorbs light in the ultraviolet wavelength band between the encapsulation layer and the light-blocking layer, it is possible to reduce the light in the ultraviolet wavelength band incident from the outside to reach the pixel defining layer. Accordingly, it is possible to reduce the degradation of the organic layer and the oxidation of the common electrode caused by the outgassing of the pixel defining layer, thereby reducing pixel shrinkage.

[0027] However, the effects of the embodiments are not limited to the effects described herein. The above and other effects of the embodiments will become more apparent to those skilled in the art by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 is a schematic perspective view showing a display device according to an embodiment;

[0030] Figure 2 Observed from the side Figure 1 A schematic cross-sectional view of a display device;

[0031] Figure 3is a schematic plan view showing a display layer of a display device according to an embodiment;

[0032] Figure 4 is a schematic plan view showing a display area of ​​a display panel according to an embodiment;

[0033] Figure 5 yes Figure 4 An enlarged schematic plan view of region A;

[0034] Figure 6 is along Figure 5 A schematic cross-sectional view taken along line X1-X1';

[0035] Figure 7 is a schematic diagram showing an incident path of external light;

[0036] Figure 8 is a schematic plan view showing a pixel according to an embodiment;

[0037] Fig. 9 is along Figure 8 A schematic cross-sectional view taken along line X2-X2';

[0038] Fig.10 is a schematic plan view showing a pixel according to an embodiment;

[0039] Fig.11 is along Fig.10 A schematic cross-sectional view taken along line X3-X3';

[0040] Fig.12 is a schematic cross-sectional view showing a display device according to an embodiment;

[0041] Fig.13 is a schematic cross-sectional view showing a display device according to an embodiment;

[0042] Fig.14 is a schematic cross-sectional view showing each light emitting region of a display device according to an embodiment;

[0043] Fig.15 is a schematic plan view showing each light emitting region of a display device according to an embodiment;

[0044] Fig.16 is along Fig.15 A schematic cross-sectional view taken along line X4-X4';

[0045] Fig.17 is a schematic cross-sectional view showing a portion of a pixel opening of a display device according to an embodiment; and

[0046] Fig.18is a schematic diagram in a case where the display device according to the embodiment is applied to a vehicle. DETAILED DESCRIPTION

[0047] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the utility model. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive and do not limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0048] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the present invention.

[0049] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material performance, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, performances, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiment can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. Moreover, similar reference numerals represent similar elements.

[0050] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or coupled to, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical and / or fluid connection with or without intervening elements. In addition, the DR1 axis, DR2 axis, and DR3 axis are not limited to the three axes of a rectangular coordinate system (such as the X-axis, the Y-axis, and the Z-axis), and may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis, and the z-axis), and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be interpreted as meaning only A, only B, or any combination of A and B. Moreover, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0052] Spatially relative terms, such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the term "below" is able to encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0053] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include plural forms. In addition, the terms "comprise", "comprising", "include" and / or "including" when used in this specification specify the existence of stated features, wholes, steps, operations, elements, parts and / or groups thereof, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than terms of degree, and thus, are used to take into account the inherent deviations in measured values, calculated values ​​and / or provided values ​​recognized by those of ordinary skill in the art.

[0054] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the zones, but rather will include deviations in shape resulting from, for example, manufacturing. In this manner, the zones illustrated in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and thus are not necessarily intended to be limiting.

[0055] As is customary in the art, in terms of functional blocks, units and / or modules, some embodiments are described and shown in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally, they can be driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and processors that perform other functions (e.g., one or more programmed microprocessors and associated circuits). Moreover, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present invention.

[0056] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0057] Figure 1 is a schematic perspective view showing a display device according to an embodiment.

[0058] Reference Figure 1 , the display device 10 may display a moving image or a still image. The display device 10 may refer to any electronic device including a display screen. For example, the display device 10 may include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigator (e.g., a vehicle navigator), a game console, a digital camera, a video camera, a vehicle dashboard, etc. In the present description, the display device 10 may be a display device for a vehicle provided in a vehicle, but the embodiment is not limited thereto.

[0059] Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. Hereinafter, an example in which an organic light emitting diode display device is used as a display device is shown, but the embodiment is not limited thereto and may also be applied to other display devices as long as the same technical concept can be applied thereto.

[0060] The shape of the display device 10 may be variously changed. For example, the display device 10 may have a shape similar to a quadrilateral having sides in the first direction DR1 and sides in the second direction DR2. A corner where the sides in the first direction DR1 and the sides in the second direction DR2 meet may be rounded to have a curvature, but the embodiment is not limited thereto and may also be formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral and may be formed similar to other polygons, a circle, or an ellipse.

[0061] The display device 10 may include a display area DA and a non-display area NDA. The display area DA is an area in which an image is displayed, and the non-display area NDA is an area in which an image is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may generally occupy a central portion of the display device 10.

[0062] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see Figure 2 ).

[0063] The display panel 100 may include a main area MA and a sub area SBA.

[0064] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA arranged around the display area DA. The display area DA may emit light from a light-emitting area or an opening area. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining a light-emitting area or an opening area, and a self-luminous element.

[0065] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but the embodiment is not limited thereto.

[0066] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver supplying a gate signal to a gate line and a fan-out line connecting the display driver 200 and the display area DA.

[0067] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that is bendable, foldable, curlable, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In another example, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0068] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power supply voltage to a power supply line, and may supply a gate control signal to a gate driver. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be arranged in a sub-region SBA, and may overlap with the main region MA in a thickness direction by bending of the sub-region SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0069] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be connected (e.g., electrically connected) to the pad portion of the display panel 100. The circuit board 300 may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip on film.

[0070] Figure 2 Observed from the side Figure 1 Schematic cross-sectional view of a display device.

[0071] Reference Figure 2 , the display panel 100 may include a display layer DU and a color filter layer CFL. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0072] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that is bendable, foldable, rollable, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the embodiment is not limited thereto. In another example, the substrate SUB may include a glass material or a metal material.

[0073] The thin film transistor layer TFTL may be arranged on the substrate SUB. The thin film transistor layer TFTL may include a thin film transistor forming a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 and the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0074] The thin film transistor layer TFTL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, gate line, data line, and power line of each of the pixels of the thin film transistor layer TFTL may be arranged in the display area DA. The gate control line and the fan-out line of the thin film transistor layer TFTL may be arranged in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be arranged in the sub-area SBA.

[0075] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element including a first electrode, a second electrode and a light emitting layer to emit light and a pixel defining layer defining a pixel. The light emitting element of the light emitting element layer EML may be disposed in the display area DA.

[0076] In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light emitting layer to emit light.

[0077] In another example, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0078] The encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0079] The color filter layer CFL may be arranged on the encapsulation layer TFEL. The color filter layer CFL may include a color filter corresponding to each of the light emitting regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of light introduced (or transmitted) from the outside of the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer CFL may prevent color distortion caused by reflection of external light.

[0080] Since the color filter layer CFL is directly disposed on the encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the display device 10 may have a relatively small thickness.

[0081] Figure 3 is a schematic plan view showing a display layer of a display device according to an embodiment.

[0082] Reference Figure 3 , the display layer DU may include a display area DA and a non-display area NDA.

[0083] The display area DA may be disposed at a central portion of the display panel 100. Pixels PX, gate lines GL, data lines DL, and power lines VL may be disposed in the display area DA. Each of the pixels PX may be defined as a minimum unit that emits light.

[0084] The gate lines GL may supply the pixels PX with gate signals received from the gate driver 210. The gate lines GL may extend in a first direction DR1, and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1.

[0085] The data lines DL may supply the pixels PX with data voltages received from the display driver 200. The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0086] The power lines VL may supply a power voltage received from the display driver 200 to the pixels PX. For example, the power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. The power lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0087] The non-display area NDA may surround the display area DA. The gate driver 210, the fan-out lines FOL, and the gate control lines GCL may be arranged in the non-display area NDA. The gate driver 210 may generate gate signals based on the gate control signals and may sequentially supply the gate signals to the gate lines GL according to a set order.

[0088] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the data line DL.

[0089] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0090] The sub-area SBA may include the display driver 200 and the pad area PA.

[0091] The display driver 200 may be used to drive the display panel 100 (see Figure 2 ) is output to the fan-out line FOL. The display driver 200 may supply a data voltage to the data line DL through the fan-out line FOL. The data voltage may be supplied to the pixel PX and may control the brightness of the pixel PX. The display driver 200 may supply a gate control signal to the gate driver 210 through the gate control line GCL.

[0092] The pad area PA may be arranged at an edge portion of the sub-area SBA. The pad area PA may be electrically connected to the circuit board 300 by using a material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP). The pad area PA may include a display pad portion DP. The display pad portion DP may be connected to a graphics system through the circuit board 300. The display pad portion DP may be connected to the circuit board 300 to receive digital video data, and the digital video data may be supplied to the display driver 200.

[0093] Figure 4 is a schematic plan view showing a display area of ​​a display panel according to an embodiment.

[0094] Reference Figure 4 , the display panel 100 may include pixels PX arranged in the first direction DR1 and the second direction DR2. Each of the pixels PX may have a planar shape such as a rectangle, a square, or a rhombus. For example, as shown in the drawings, each of the pixels PX may have a planar shape such as a square. However, each of the pixels PX is not limited thereto, and may have various shapes such as other polygons, circles, and ellipses in a plan view.

[0095] Some of the pixels PX may emit a first light, others of the pixels PX may emit a second light, and the remaining pixels PX may emit a third light. For example, the first light may be light in a blue wavelength band, the second light may be light in a red wavelength band, and the third light may be light in a green wavelength band. The red wavelength band may be a wavelength band of about 600 nm to about 750 nm, the green wavelength band may be a wavelength band of about 480 nm to about 560 nm, and the blue wavelength band may be a wavelength band of about 370 nm to about 460 nm, but the embodiment is not limited thereto. In some embodiments, some of the pixels PX may also emit white light.

[0096] Each of the pixels PX may include at least one of an organic light emitting element including an organic material, an inorganic light emitting element including an inorganic semiconductor, a quantum dot light emitting element including a quantum dot light emitting layer, and a micro light emitting diode (LED) as a light emitting element emitting light. Hereinafter, it is mainly described that each of the pixels PX includes an organic light emitting element, but the embodiment is not limited thereto.

[0097] Figure 5 yes Figure 4 An enlarged schematic plan view of region A of FIG. Figure 6 is along Figure 5 A cross-sectional view taken along line X1-X1'. Figure 7 is a schematic diagram showing the incident path of external light.

[0098] and Figure 2 Refer to Figure 5 , Figure 6 and Figure 7 , the display panel 100 of the display device 10 may include a display layer DU and a color filter layer CFL. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL. The display panel 100 may include a metal oxide layer USL on the encapsulation layer TFEL and a light blocking layer BM arranged on the metal oxide layer USL. Color filters CF1, CF2, and CF3 of the color filter layer CFL may be arranged on the light blocking layer BM.

[0099] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that is bendable, foldable, rollable, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the embodiment is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0100] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0101] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing penetration of air or moisture. For example, the first buffer layer BF1 may include inorganic films that are alternately stacked.

[0102] The lower metal layer BML may be disposed on the first buffer layer BF1. The lower metal layer BML may prevent light incident from below from being incident on the semiconductor layer ACT of the thin film transistor TFT. The lower metal layer BML may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0103] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing penetration of air or moisture. For example, the second buffer layer BF2 may include inorganic films alternately stacked.

[0104] The thin film transistor TFT may be arranged on the second buffer layer BF2 and may form a pixel circuit of each pixel. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0105] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may have conductivity to form a source electrode SE and a drain electrode DE.

[0106] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT via the gate insulating layer GI.

[0107] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2, and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 penetrates (or passes).

[0108] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 penetrates (or passes). The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0109] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0110] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 penetrates (or passes). The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0111] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may connect (e.g., electrically connect) the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0112] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 penetrates (or passes).

[0113] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may connect (eg, electrically connect) the first connection electrode CNE1 and the pixel electrode AE ​​of the light emitting element ED to each other. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 and contact the first connection electrode CNE1.

[0114] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include a contact hole through which the pixel electrode AE ​​of the light emitting element ED penetrates (or passes).

[0115] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include a pixel electrode AE, an organic layer EL, and a common electrode CE.

[0116] The pixel electrode AE ​​may be disposed on the second passivation layer PAS2. The pixel electrode AE ​​may overlap any one of the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL. The pixel electrode AE ​​may be connected (eg, electrically connected) to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0117] The organic layer EL may be disposed on the pixel electrode AE. For example, the organic layer EL may be an organic light emitting layer made of an organic material, but the embodiment is not limited thereto. In the case where the organic layer EL corresponds to the organic light emitting layer, when the thin film transistor TFT applies a specific voltage to the pixel electrode AE ​​of the light emitting element ED and the common electrode CE of the light emitting element ED receives a common voltage or a cathode voltage, each of holes and electrons may move to the organic layer EL through the hole transport layer and the electron transport layer, and the holes and electrons may be recombined with each other in the organic layer EL to emit light.

[0118] The common electrode CE may be arranged on the organic layer EL. For example, the common electrode CE may be implemented in the form of an electrode that is common to all pixels rather than being divided for each pixel. The common electrode CE may be arranged on the organic layer EL in the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, and may be arranged on the pixel defining layer PDL in areas other than the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0119] The common electrode CE may receive a common voltage or a low potential voltage. In the case where the pixel electrode AE ​​receives a voltage corresponding to the data voltage and the common electrode CE receives a low potential voltage, the organic layer EL may emit light due to a potential difference formed between the pixel electrode AE ​​and the common electrode CE.

[0120] The pixel defining layer PDL may include openings OPE1, OPE2, and OPE3, and may be disposed on the second passivation layer PAS2 and portions of the pixel electrode AE. The pixel defining layer PDL may include first openings OPE1, second openings OPE2, and third openings OPE3, and each of the openings OPE1, OPE2, and OPE3 may expose a portion of the pixel electrode AE.

[0121] Each of the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL may define a first light emitting area EA1, a second light emitting area EA2, and a third light emitting area EA3. For example, the first light emitting area EA1 may be defined by the first opening OPE1 of the pixel defining layer PDL, the second light emitting area EA2 may be defined by the second opening OPE2 of the pixel defining layer PDL, and the third light emitting area EA3 may be defined by the third opening OPE3 of the pixel defining layer PDL.

[0122] In an embodiment, the areas or sizes of the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 may be the same as each other. In another example, the areas or sizes of the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 may be different from each other. For example, the area of ​​the first light-emitting area EA1 may be larger than the area of ​​each of the second light-emitting area EA2 and the third light-emitting area EA3, and the area of ​​the second light-emitting area EA2 may be larger than the area of ​​the third light-emitting area EA3. The areas of the light-emitting areas EA1, EA2, and EA3 may vary according to the sizes of the openings OPE1, OPE2, and OPE3 formed in the pixel defining layer PDL. The intensity of light emitted from the light-emitting areas EA1, EA2, and EA3 may vary according to the areas of the light-emitting areas EA1, EA2, and EA3, and the color of the picture displayed on the display device 10 may be controlled by adjusting the areas of the light-emitting areas EA1, EA2, and EA3.

[0123] The pixel defining layer PDL may separate and insulate the pixel electrodes AE of the light emitting element ED from each other. The pixel defining layer PDL may include a light absorbing material to prevent light reflection. For example, the pixel defining layer PDL may include a polyimide (PI)-based binder and a mixture in which a red pigment, a green pigment, and a blue pigment are mixed. In another example, the pixel defining layer PDL may include a cardo-based binder resin and a mixture of a lactam black pigment and a blue pigment. In another example, the pixel defining layer PDL may include carbon black.

[0124] The encapsulation layer TFEL may be disposed on the common electrode CE to cover the light emitting element ED. The encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust.

[0125] In an embodiment, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed therebetween may be an organic encapsulation layer.

[0126] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0127] The second encapsulation layer TFE2 may include a polymer-based material. Examples of polymer-based materials may include acrylic resins, epoxy resins, polyimide, polyethylene, etc. For example, the organic encapsulation layer may include acrylic resins, such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0128] The light blocking layer BM may be arranged on the encapsulation layer TFEL. The light blocking layer BM may include holes OPT1, OPT2, and OPT3 arranged to overlap with the light emitting areas EA1, EA2, and EA3. For example, the first hole OPT1 may overlap with the first light emitting area EA1 or the first opening OPE1. The second hole OPT2 may overlap with the second light emitting area EA2 or the second opening OPE2, and the third hole OPT3 may overlap with the third light emitting area EA3 or the third opening OPE3. The area or size of the corresponding holes OPT1, OPT2, and OPT3 may be larger than the area or size of the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL. Because the holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be larger than the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL, the light emitted from the light emitting areas EA1, EA2, and EA3 may be visually recognized by the user not only from the front side of the display device 10 but also from the side surface thereof.

[0129] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the embodiment is not limited thereto. The light blocking layer BM may prevent color mixing caused by the transmission of visible light between the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, thereby improving the color reproduction rate of the display device 10.

[0130] The color filters CF1, CF2, and CF3 of the color filter layer CFL may be arranged on the light blocking layer BM. Different color filters CF1, CF2, and CF3 may be arranged to correspond to different light emitting areas EA1, EA2, and EA3 or openings OPE1, OPE2, and OPE3 and holes OPT1, OPT2, and OPT3 of the light blocking layer BM, respectively. The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 arranged to correspond to different light emitting areas EA1, EA2, and EA3, respectively. For example, the first color filter CF1 may be arranged to correspond to the first light emitting area EA1, the second color filter CF2 may be arranged to correspond to the second light emitting area EA2, and the third color filter CF3 may be arranged to correspond to the third light emitting area EA3. The first color filter CF1 may be arranged in the first hole OPT1 of the light blocking layer BM, the second color filter CF2 may be arranged in the second hole OPT2 of the light blocking layer BM, and the third color filter CF3 may be arranged in the third hole OPT3 of the light blocking layer BM. Each of the color filters CF1, CF2, and CF3 may have an area larger than that of the holes OPT1, OPT2, and OPT3 of the light blocking layer BM in a plan view, and some of the color filters CF1, CF2, and CF3 may be arranged (e.g., directly arranged) on the light blocking layer BM.

[0131] The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment that absorbs light in a wavelength band other than a specific wavelength band, and may be arranged to correspond to the color of light emitted from the light emitting areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a blue color filter that overlaps with the first light emitting area EA1 and transmits only a blue first light. The second color filter CF2 may be a red color filter that overlaps with the second light emitting area EA2 and transmits only a red second light, and the third color filter CF3 may be a green color filter that overlaps with the third light emitting area EA3 and transmits only a green third light.

[0132] The planarization layer OC may be disposed on the color filters CF1, CF2, and CF3 to planarize the upper end portions of the color filters CF1, CF2, and CF3. The planarization layer OC may be a colorless light-transmitting layer having no color in the visible light wavelength band. For example, the planarization layer OC may include a colorless light-transmitting organic material such as an acrylic-based resin.

[0133] According to an embodiment, the color filters CF1, CF2, and CF3 of the display device 10 may overlap with other color filters CF1, CF2, and CF3 adjacent thereto on the light-blocking layer BM. The color filters CF1, CF2, and CF3 arranged on the light-blocking layer BM may be arranged so that two color filters CF1, CF2, and CF3 adjacent to each other cover (e.g., completely cover) the light-blocking layer BM. Two color filters CF1, CF2, and CF3 adjacent to each other may partially overlap each other on the light-blocking layer BM. The overlap of the color filters CF1, CF2, and CF3 may reduce the reflection of external light by the light-blocking layer BM, and the overlapping arrangement of the color filters CF1, CF2, and CF3 may be designed to further reduce external light reflection.

[0134] In the display device 10, the first color filter CF1 and the second color filter CF2 adjacent to each other may overlap each other on the light blocking layer BM, and the second color filter CF2 and the third color filter CF3 may also overlap each other on the light blocking layer BM. The first color filter CF1 and the third color filter CF3 adjacent to each other may also overlap each other on the light blocking layer BM.

[0135] According to an embodiment, the metal oxide layer USL may be arranged between the encapsulation layer TFEL and the light blocking layer BM. The metal oxide layer USL may block (e.g., reflect or absorb) light in the ultraviolet wavelength band incident from the outside. In the case where the pixel defining layer PDL arranged in the light emitting element layer EML is exposed to light in the ultraviolet wavelength band, outgassing may occur through a chemical reaction. Since the pixel defining layer PDL is in direct contact with the pixel electrode AE, the organic layer EL, and the common electrode CE, the gas generated from the pixel defining layer PDL may directly affect the organic layer EL and the common electrode CE. For example, the gas discharged from the pixel defining layer PDL may degrade the organic layer EL and oxidize the common electrode CE. Accordingly, a problem of pixel shrinkage in which the area of ​​each of the light emitting areas EA1, EA2, and EA3 is reduced may occur.

[0136] In an embodiment, since the metal oxide layer USL capable of blocking light in the ultraviolet wavelength band is disposed between the encapsulation layer TFEL and the light blocking layer BM, the occurrence of pixel shrinkage may be reduced by preventing outgassing of the pixel defining layer PDL.

[0137] The metal oxide layer USL may be arranged (e.g., directly arranged) on the encapsulation layer TFEL. The lower surface of the metal oxide layer USL may be in contact with the upper surface of the encapsulation layer TFEL, and may be in direct contact with the upper surface of the third encapsulation layer TFE3 of the encapsulation layer TFEL. For example, the metal oxide layer USL may be arranged (e.g., directly arranged) on the lower surface of the light-blocking layer BM. The upper surface of the metal oxide layer USL may be in direct contact with the lower surface of the light-blocking layer BM. In the case where the metal oxide layer USL is arranged on the lower side of the light-blocking layer BM, light incident from the outside may be reflected by the metal oxide layer USL and absorbed into the light-blocking layer BM. Accordingly, degradation of visibility due to reflection of external light may be prevented.

[0138] The metal oxide layer USL may block (e.g., reflect or absorb) light in an ultraviolet wavelength band incident from the outside. The metal oxide layer USL may include a metal oxide capable of blocking light in the ultraviolet wavelength band. For example, the metal oxide layer USL may include at least one of titanium oxide, zinc oxide, and tantalum oxide. The metal oxide layer USL may have a thickness of about 10 nm to about 10000 nm to effectively block light in the ultraviolet wavelength band. In the case where the thickness of the metal oxide layer USL is about 10 nm or more, the metal oxide layer USL may have excellent properties of blocking light in the ultraviolet wavelength band, and in the case where the thickness of the metal oxide layer USL is about 10000 nm or less, the metal oxide layer USL may prevent an increase in the blocking rate of light in the visible light wavelength band.

[0139] The metal oxide layer USL may include opening holes OPU1, OPU2, and OPU3 arranged to overlap with the light emitting areas EA1, EA2, and EA3. For example, the first opening hole OPU1 may overlap with the first light emitting area EA1 or the first opening OPE1. The second opening hole OPU2 may overlap with the second light emitting area EA2 or the second opening OPE2, and the third opening hole OPU3 may overlap with the third light emitting area EA3 or the third opening OPE3.

[0140] The area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be the same as the area or size of the light emitting areas EA1, EA2 and EA3 or the openings OPE1, OPE2 and OPE3. For example, the area or size of the first opening hole OPU1 may be the same as the area or size of the first light emitting area EA1 or the first opening OPE1, the area or size of the second opening hole OPU2 may be the same as the area or size of the second light emitting area EA2 or the second opening OPE2, and the area or size of the third opening hole OPU3 may be the same as the area or size of the third light emitting area EA3 or the third opening OPE3.

[0141] The side of the metal oxide layer USL may be aligned and matched with the side of the pixel defining layer PDL. For example, the side of the metal oxide layer USL in contact with the first opening hole OPU1 may be aligned and matched with the side of the pixel defining layer PDL in contact with the first opening OPE1. For example, the side of the metal oxide layer USL in contact with the second opening hole OPU2 may be aligned and matched with the side of the pixel defining layer PDL in contact with the second opening OPE2, and the side of the metal oxide layer USL in contact with the third opening hole OPU3 may be aligned and matched with the side of the pixel defining layer PDL in contact with the third opening OPE3.

[0142] The width W1 of the metal oxide layer USL may be the same as the width W2 of the pixel defining layer PDL. The width W1 of the metal oxide layer USL may refer to the distance between the first opening hole OPU1 and the second opening hole OPU2, the distance between the second opening hole OPU2 and the third opening hole OPU3, or the distance between the third opening hole OPU3 and the first opening hole OPU1. For example, the width W2 of the pixel defining layer PDL may refer to the distance between the first opening OPE1 and the second opening OPE2, the distance between the second opening OPE2 and the third opening OPE3, or the distance between the third opening OPE3 and the first opening OPE1. For example, the width W1 of the metal oxide layer USL between the first opening hole OPU1 and the second opening hole OPU2 may be the same as the width W2 of the pixel defining layer PDL between the first opening OPE1 and the second opening OPE2. For example, the width W1 of the metal oxide layer USL between the second opening hole OPU2 and the third opening hole OPU3 may be the same as the width W2 of the pixel defining layer PDL between the second opening OPE2 and the third opening OPE3, and the width W1 of the metal oxide layer USL between the third opening hole OPU3 and the first opening hole OPU1 may be the same as the width W2 of the pixel defining layer PDL between the third opening OPE3 and the first opening OPE1.

[0143] The area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be smaller than the area or size of the holes OPT1, OPT2 and OPT3 of the light blocking layer BM. For example, the area or size of the first opening hole OPU1 may be smaller than the area or size of the first hole OPT1, the area or size of the second opening hole OPU2 may be smaller than the area or size of the second hole OPT2, and the area or size of the third opening hole OPU3 may be smaller than the area or size of the third hole OPT3.

[0144] The side of the metal oxide layer USL may protrude outwards compared to the side of the light blocking layer BM. For example, the side of the metal oxide layer USL in contact with the first opening hole OPU1 may protrude outwards compared to the side of the light blocking layer BM in contact with the first hole OPT1. For example, the side of the metal oxide layer USL in contact with the second opening hole OPU2 may protrude outwards compared to the side of the light blocking layer BM in contact with the second hole OPT2, and the side of the metal oxide layer USL in contact with the third opening hole OPU3 may protrude outwards compared to the side of the light blocking layer BM in contact with the third hole OPT3.

[0145] The width W1 of the metal oxide layer USL may be greater than the width W3 of the light blocking layer BM. The width W3 of the light blocking layer BM may refer to the distance between the first hole OPT1 and the second hole OPT2, the distance between the second hole OPT2 and the third hole OPT3, or the distance between the third hole OPT3 and the first hole OPT1. For example, the width W1 of the metal oxide layer USL between the first opening hole OPU1 and the second opening hole OPU2 may be greater than the width W3 of the light blocking layer BM between the first hole OPT1 and the second hole OPT2. For example, the width W1 of the metal oxide layer USL between the second opening hole OPU2 and the third opening hole OPU3 may be greater than the width W3 of the light blocking layer BM between the second hole OPT2 and the third hole OPT3, and the width W1 of the metal oxide layer USL between the third opening hole OPU3 and the first opening hole OPU1 may be greater than the width W3 of the light blocking layer BM between the third hole OPT3 and the first hole OPT1.

[0146] As described above, in the display device 10 according to the embodiment, by arranging the metal oxide layer USL that absorbs light in the ultraviolet wavelength band between the encapsulation layer TFEL and the light blocking layer BM, light in the ultraviolet wavelength band incident from the outside can be blocked from reaching the pixel defining layer PDL. Accordingly, degradation of the organic layer EL and oxidation of the common electrode CE caused by outgassing of the pixel defining layer PDL can be prevented, thereby preventing the pixel shrinkage phenomenon.

[0147] Figure 8 is a schematic plan view showing a pixel according to another example. Fig. 9 is along Figure 8 Schematic cross-sectional view taken along line X2-X2'.

[0148] Reference Figure 8 and Fig. 9 , the implementation method is the same as above Figure 5 , Figure 6 and Figure 7The difference of the embodiment is that the width W1 of the metal oxide layer USL is the same as the width W3 of the light blocking layer BM and is smaller than the width W2 of the pixel defining layer PDL. Hereinafter, redundant descriptions identical or similar to the description of the above-mentioned embodiment will be omitted, and differences from the above-mentioned embodiment will be described.

[0149] The area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be larger than the area or size of the light emitting areas EA1, EA2 and EA3 or the openings OPE1, OPE2 and OPE3. For example, the area or size of the first opening hole OPU1 may be larger than the area or size of the first light emitting area EA1 or the first opening OPE1, the area or size of the second opening hole OPU2 may be larger than the area or size of the second light emitting area EA2 or the second opening OPE2, and the area or size of the third opening hole OPU3 may be larger than the area or size of the third light emitting area EA3 or the third opening OPE3.

[0150] The side of the metal oxide layer USL may be arranged inwardly compared to the side of the pixel defining layer PDL. For example, the side of the metal oxide layer USL in contact with the first opening hole OPU1 may be arranged inwardly compared to the side of the pixel defining layer PDL in contact with the first opening OPE1. For example, the side of the metal oxide layer USL in contact with the second opening hole OPU2 may be arranged inwardly compared to the side of the pixel defining layer PDL in contact with the second opening OPE2, and the side of the metal oxide layer USL in contact with the third opening hole OPU3 may be arranged inwardly compared to the side of the pixel defining layer PDL in contact with the third opening OPE3.

[0151] The width W1 of the metal oxide layer USL may be smaller than the width W2 of the pixel defining layer PDL. For example, the width W1 of the metal oxide layer USL between the first opening hole OPU1 and the second opening hole OPU2 may be smaller than the width W2 of the pixel defining layer PDL between the first opening OPE1 and the second opening OPE2. For example, the width W1 of the metal oxide layer USL between the second opening hole OPU2 and the third opening hole OPU3 may be smaller than the width W2 of the pixel defining layer PDL between the second opening OPE2 and the third opening OPE3, and the width W1 of the metal oxide layer USL between the third opening hole OPU3 and the first opening hole OPU1 may be smaller than the width W2 of the pixel defining layer PDL between the third opening OPE3 and the first opening OPE1.

[0152] The area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be the same as the area or size of the holes OPT1, OPT2 and OPT3 of the light blocking layer BM. For example, the area or size of the first opening hole OPU1 may be the same as the area or size of the first hole OPT1, the area or size of the second opening hole OPU2 may be the same as the area or size of the second hole OPT2, and the area or size of the third opening hole OPU3 may be the same as the area or size of the third hole OPT3.

[0153] The side of the metal oxide layer USL may be aligned and matched with the side of the light blocking layer BM. For example, the side of the metal oxide layer USL in contact with the first opening hole OPU1 may be aligned and matched with the side of the light blocking layer BM in contact with the first hole OPT1. For example, the side of the metal oxide layer USL in contact with the second opening hole OPU2 may be aligned and matched with the side of the light blocking layer BM in contact with the second hole OPT2, and the side of the metal oxide layer USL in contact with the third opening hole OPU3 may be aligned and matched with the side of the light blocking layer BM in contact with the third hole OPT3.

[0154] The width W1 of the metal oxide layer USL may be the same as the width W3 of the light blocking layer BM. For example, the width W1 of the metal oxide layer USL between the first opening hole OPU1 and the second opening hole OPU2 may be the same as the width W3 of the light blocking layer BM between the first hole OPT1 and the second hole OPT2. For example, the width W1 of the metal oxide layer USL between the second opening hole OPU2 and the third opening hole OPU3 may be the same as the width W3 of the light blocking layer BM between the second hole OPT2 and the third hole OPT3, and the width W1 of the metal oxide layer USL between the third opening hole OPU3 and the first opening hole OPU1 may be the same as the width W3 of the light blocking layer BM between the third hole OPT3 and the first hole OPT1.

[0155] As described above, in the display device 10 according to the embodiment, by arranging the metal oxide layer USL that absorbs light in the ultraviolet wavelength band between the encapsulation layer TFEL and the light blocking layer BM, it is possible to reduce the light in the ultraviolet wavelength band incident from the outside to reach the pixel defining layer PDL. Accordingly, it is possible to reduce the degradation of the organic layer EL and the oxidation of the common electrode CE caused by outgassing of the pixel defining layer PDL, thereby reducing the pixel shrinkage phenomenon.

[0156] Fig.10 is a schematic plan view showing a pixel according to an embodiment. Fig.11 is along Fig.10 A schematic cross-sectional view taken along line X3-X3'.

[0157] Reference Fig.10 and Fig.11 , the implementation method is the same as above Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The embodiment of the present invention is different in that the width W1 of the metal oxide layer USL is smaller than the width W3 of the light blocking layer BM and the width W2 of the pixel defining layer PDL. Hereinafter, redundant descriptions identical or similar to those of the above-described embodiment will be omitted, and differences from the above-described embodiment will be described.

[0158] The metal oxide layer USL may be disposed between the encapsulation layer TFEL and the light blocking layer BM. The metal oxide layer USL may be disposed between the third encapsulation layer TFE3 of the encapsulation layer TFEL and the light blocking layer BM. The light blocking layer BM may cover the metal oxide layer USL. For example, the light blocking layer BM may contact (for example, directly contact) the upper surface and the side surface of the metal oxide layer USL.

[0159] The area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be larger than the area or size of the light emitting areas EA1, EA2 and EA3 or the openings OPE1, OPE2 and OPE3. For example, the area or size of the first opening hole OPU1 may be larger than the area or size of the first light emitting area EA1 or the first opening OPE1, the area or size of the second opening hole OPU2 may be larger than the area or size of the second light emitting area EA2 or the second opening OPE2, and the area or size of the third opening hole OPU3 may be larger than the area or size of the third light emitting area EA3 or the third opening OPE3.

[0160] The side of the metal oxide layer USL may be arranged inwardly compared to the side of the pixel defining layer PDL. For example, the side of the metal oxide layer USL in contact with the first opening hole OPU1 may be arranged inwardly compared to the side of the pixel defining layer PDL in contact with the first opening OPE1. For example, the side of the metal oxide layer USL in contact with the second opening hole OPU2 may be arranged inwardly compared to the side of the pixel defining layer PDL in contact with the second opening OPE2, and the side of the metal oxide layer USL in contact with the third opening hole OPU3 may be arranged inwardly compared to the side of the pixel defining layer PDL in contact with the third opening OPE3.

[0161] The width W1 of the metal oxide layer USL may be smaller than the width W2 of the pixel defining layer PDL. For example, the width W1 of the metal oxide layer USL between the first opening hole OPU1 and the second opening hole OPU2 may be smaller than the width W2 of the pixel defining layer PDL between the first opening OPE1 and the second opening OPE2. For example, the width W1 of the metal oxide layer USL between the second opening hole OPU2 and the third opening hole OPU3 may be smaller than the width W2 of the pixel defining layer PDL between the second opening OPE2 and the third opening OPE3, and the width W1 of the metal oxide layer USL between the third opening hole OPU3 and the first opening hole OPU1 may be smaller than the width W2 of the pixel defining layer PDL between the third opening OPE3 and the first opening OPE1.

[0162] The area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be larger than the area or size of the holes OPT1, OPT2 and OPT3 of the light blocking layer BM. For example, the area or size of the first opening hole OPU1 may be larger than the area or size of the first hole OPT1, the area or size of the second opening hole OPU2 may be larger than the area or size of the second hole OPT2, and the area or size of the third opening hole OPU3 may be larger than the area or size of the third hole OPT3.

[0163] The side of the metal oxide layer USL may be arranged inwardly compared to the side of the light blocking layer BM. For example, the side of the metal oxide layer USL in contact with the first opening hole OPU1 may be arranged inwardly compared to the side of the light blocking layer BM in contact with the first hole OPT1. For example, the side of the metal oxide layer USL in contact with the second opening hole OPU2 may be arranged inwardly compared to the side of the light blocking layer BM in contact with the second hole OPT2, and the side of the metal oxide layer USL in contact with the third opening hole OPU3 may be arranged inwardly compared to the side of the light blocking layer BM in contact with the third hole OPT3.

[0164] The width W1 of the metal oxide layer USL may be smaller than the width W3 of the light blocking layer BM. For example, the width W1 of the metal oxide layer USL between the first opening hole OPU1 and the second opening hole OPU2 may be smaller than the width W3 of the light blocking layer BM between the first hole OPT1 and the second hole OPT2. For example, the width W1 of the metal oxide layer USL between the second opening hole OPU2 and the third opening hole OPU3 may be smaller than the width W3 of the light blocking layer BM between the second hole OPT2 and the third hole OPT3, and the width W1 of the metal oxide layer USL between the third opening hole OPU3 and the first opening hole OPU1 may be smaller than the width W3 of the light blocking layer BM between the third hole OPT3 and the first hole OPT1.

[0165] As described above, in the display device 10 according to the embodiment, by arranging the metal oxide layer USL that absorbs light in the ultraviolet wavelength band between the encapsulation layer TFEL and the light blocking layer BM, it is possible to reduce the light in the ultraviolet wavelength band incident from the outside to reach the pixel defining layer PDL. Accordingly, it is possible to reduce the degradation of the organic layer EL and the oxidation of the common electrode CE caused by outgassing of the pixel defining layer PDL, thereby reducing the pixel shrinkage phenomenon.

[0166] Fig.12 is a schematic cross-sectional view showing a display device according to an embodiment.

[0167] Reference Fig.12 , the implementation method is the same as above Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 The embodiment is different in that the metal oxide layer USL is disposed between the second encapsulation layer TFE2 and the third encapsulation layer TFE3 of the encapsulation layer TFEL. Hereinafter, redundant descriptions identical or similar to those of the above-described embodiment will be omitted, and differences from the above-described embodiment will be described.

[0168] The metal oxide layer USL may be arranged within the encapsulation layer TFEL. For example, the metal oxide layer USL may be arranged between the second encapsulation layer TFE2 and the third encapsulation layer TFE3 of the encapsulation layer TFEL. For example, the metal oxide layer USL may be arranged (for example, directly arranged) on the upper surface of the second encapsulation layer TFE2 and covered by the third encapsulation layer TFE3. For example, the third encapsulation layer TFE3 may cover the metal oxide layer USL.

[0169] In an embodiment, the metal oxide layer USL may be disposed on the lower side of the third encapsulation layer TFE3 and disposed adjacent to the pixel defining layer PDL. For example, because the metal oxide layer USL is adjacent to the pixel defining layer PDL, the amount of light incident on the pixel defining layer PDL may be reduced by reducing the incident angle of light in the ultraviolet wavelength band incident from the outside.

[0170] The metal oxide layer USL may overlap the pixel defining layer PDL and may overlap the light blocking layer BM. The metal oxide layer USL may include opening holes OPU1, OPU2, and OPU3. Figure 5 and Figure 6As described above, the area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be the same as the area or size of the light emitting areas EA1, EA2 and EA3 or the openings OPE1, OPE2 and OPE3. For example, the side of the metal oxide layer USL may be aligned and matched with the side of the pixel defining layer PDL. The area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be smaller than the area or size of the holes OPT1, OPT2 and OPT3 of the light blocking layer BM.

[0171] Fig.13 is a schematic cross-sectional view showing a display device according to an embodiment.

[0172] Reference Fig.13 , the implementation method is the same as above Figures 5 to 12 The embodiment is different in that the metal oxide layer USL is disposed between the first encapsulation layer TFE1 and the second encapsulation layer TFE2 of the encapsulation layer TFEL. Hereinafter, redundant descriptions identical or similar to those of the above-described embodiment will be omitted, and differences from the above-described embodiment will be described.

[0173] The metal oxide layer USL may be arranged within the encapsulation layer TFEL. For example, the metal oxide layer USL may be arranged between the first encapsulation layer TFE1 and the second encapsulation layer TFE2 of the encapsulation layer TFEL. For example, the metal oxide layer USL may be arranged (for example, directly arranged) on the upper surface of the first encapsulation layer TFE1 and covered by the second encapsulation layer TFE2. For example, the second encapsulation layer TFE2 may cover the metal oxide layer USL.

[0174] In an embodiment, the metal oxide layer USL may be disposed on the lower side of the second encapsulation layer TFE2 and disposed adjacent to the pixel defining layer PDL. For example, because the metal oxide layer USL is adjacent to the pixel defining layer PDL, the amount of light incident on the pixel defining layer PDL may be reduced by reducing the incident angle of light in the ultraviolet wavelength band incident from the outside.

[0175] The metal oxide layer USL may overlap the pixel defining layer PDL and may overlap the light blocking layer BM. The metal oxide layer USL may include opening holes OPU1, OPU2, and OPU3. Figure 5 and Figure 6As described above, the area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be the same as the area or size of the light emitting areas EA1, EA2 and EA3 or the openings OPE1, OPE2 and OPE3. For example, the side of the metal oxide layer USL may be aligned and matched with the side of the pixel defining layer PDL. The area or size of the opening holes OPU1, OPU2 and OPU3 of the metal oxide layer USL may be smaller than the area or size of the holes OPT1, OPT2 and OPT3 of the light blocking layer BM.

[0176] Fig.14 is a schematic cross-sectional view showing each light emitting region of a display device according to an embodiment. Fig.15 is a schematic plan view showing respective light emitting regions of a display device according to an embodiment. Fig.16 is along Fig.15 Schematic cross-sectional view taken along line X4-X4'. Fig.17 is a schematic cross-sectional view showing a portion of a pixel opening of a display device according to an embodiment.

[0177] exist Fig.16 In the embodiment, the lower light emitting layers OLE1, OLE2 and OLE3 and the upper light emitting layers OLE1', OLE2' and OLE3' are represented by the reference numeral "OLE" as one layer, and a common layer is continuously formed in each of the light emitting areas EA1, EA2 and EA3, for example, the hole injection layer HIL, the first hole transport layer HTL1, the first electron transport layer ETL1, the charge generation layer CGL, the second hole transport layer HTL2, the buffer layer BUL and the second electron transport layer ETL2 are represented by the reference numeral "COL" as one layer. Fig.17 , the hole injection layer HIL and the first hole transport layer HTL1 are shown as one layer, the first electron transport layer ETL1, the charge generation layer CGL and the second hole transport layer HTL2 are shown as one layer, and the buffer layer BUL and the second electron transport layer ETL2 are shown as one layer.

[0178] Reference Figures 14 to 17 , the implementation method is the same as above Figures 5 to 13 The embodiment of the present invention is different in that the pattern openings OPX1, OPX2, and OPX3 of the metal oxide layer USL are arranged on the pixel openings POP1, POP2, and POP3 arranged in the pixel defining layer PDL and the second passivation layer PAS2. Hereinafter, redundant descriptions that are the same as or similar to the description of the above-mentioned embodiment will be omitted, and differences from the above-mentioned embodiment will be described.

[0179] Reference Fig.14The light emitting elements ED1, ED2 and ED3 may be arranged in the first, second and third light emitting areas EA1, EA2 and EA3, respectively, and each of the light emitting elements ED1, ED2 and ED3 may include a pixel electrode AE, an organic layer EL and a common electrode CE.

[0180] The organic layer EL may have a structure in which a plurality of light emitting layers overlap each other, for example, a series structure. The organic layer EL may include a first stack body ST1 including lower light emitting layers OLE1, OLE2, and OLE3, a second stack body ST2 located on the first stack body ST1 and including upper light emitting layers OLE1', OLE2', and OLE3', and a charge generation layer CGL located between the first stack body ST1 and the second stack body ST2. The first stack body ST1 and the second stack body ST2 may overlap each other.

[0181] The lower light emitting layers OLE1, OLE2, and OLE3 and the upper light emitting layers OLE1', OLE2', and OLE3' may overlap each other.

[0182] The first lower light emitting layer OLE1 and the first upper light emitting layer OLE1' may emit light of a first color, for example, blue light. The second lower light emitting layer OLE2 and the second upper light emitting layer OLE2' may emit light of a second color, for example, red light. The third lower light emitting layer OLE3 and the third upper light emitting layer OLE3' may emit light of a third color, for example, green light. For example, the emission light finally emitted from the organic layer EL may be blue light in the first light emitting area EA1, red light in the second light emitting area EA2, and green light in the third light emitting area EA3.

[0183] In some embodiments, each of the first lower light emitting layer OLE1 and the first upper light emitting layer OLE1' that emit blue light may include a host and a dopant. The host is not limited as long as it is a commonly used material, for example, Alq 3 (tris(8-hydroxyquinoline)aluminum), CBP(4,4'-bis(N-carbazolyl)-1,1'-biphenyl), PVK(poly(N-vinylcarbazole)), ADN(9,10-di(naphthalene-2-yl)anthracene), TCTA(4,4',4"-tri(carbazol-9-yl)-triphenylamine), TPBi(1,3,5-tri(N-phenylbenzimidazol-2-yl)benzene), TBADN(3-tert-butyl-9,10-di(naphthalene-2-yl)anthracene), DSA(distyrylarene), CDBP(4,4'-bis(9-carbazolyl)-2,2"-dimethylbiphenyl), MADN(2-methyl-9,10-bis(naphthalene-2-yl)anthracene), etc.

[0184] For example, the first lower light emitting layer OLE1 and the first upper light emitting layer OLE1' emitting blue light may include a fluorescent material including any one selected from the group consisting of, for example, spiro-DPVBi, spiro-6P, distyrylbenzene (DSB), distyrylarene (DSA), polyfluorene (PFO)-based polymers, and poly(p-phenylene vinylene) (PPV)-based polymers. As another example, the first lower light emitting layer OLE1 and the first upper light emitting layer OLE1' emitting blue light may also include a fluorescent material including, for example, (4,6-F 2 ppy) 2 Irpic's organometallic complex phosphorescent materials.

[0185] In some embodiments, the second lower light-emitting layer OLE2 and the second upper light-emitting layer OLE2' emitting red light may include a host material including carbazole biphenyl (CBP) or 1,3-bis(carbazole-9-yl) (mCP), may be made of a phosphorescent material including a dopant including one or more selected from the group consisting of PIQIr(acac) (bis(1-phenylisoquinoline) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinoline) iridium acetylacetonate), PQIr(tris(1-phenylquinoline)iridium) and PtOEP (octaethylporphyrin platinum), and may be made of PBD:Eu(DBM) 3 The invention is made of a fluorescent material of (Phen) or perylene, but the embodiment is not limited thereto.

[0186] In some embodiments, the third lower light emitting layer OLE3 and the third upper light emitting layer OLE3' emitting green light may include a host material including CBP or mCP, and may include Ir(ppy) 3 (fac tris (2-phenylpyridine) iridium) dopant material, and different from this, can be made of Alq 3 The fluorescent material is (tris(8-hydroxyquinoline)aluminum), but the embodiment is not limited thereto.

[0187] The charge generation layer CGL may be arranged between the first stack body ST1 and the second stack body ST2. The charge generation layer CGL may play a role in injecting charges into each light emitting layer. The charge generation layer CGL may play a role in adjusting the charge balance between the first stack body ST1 and the second stack body ST2. The charge generation layer CGL may include an n-type charge generation layer CGL1 and a p-type charge generation layer CGL2. The p-type charge generation layer CGL2 may be arranged on the n-type charge generation layer CGL1 and may be located between the n-type charge generation layer CGL1 and the second stack body ST2.

[0188] The charge generation layer CGL may have a structure in which an n-type charge generation layer CGL1 and a p-type charge generation layer CGL2 are bonded to each other. The n-type charge generation layer CGL1 may be arranged closer to the pixel electrode AE ​​among the pixel electrode AE ​​and the common electrode CE. The p-type charge generation layer CGL2 may be arranged closer to the common electrode CE among the pixel electrode AE ​​and the common electrode CE. The n-type charge generation layer CGL1 may supply electrons to the pixel electrode AE ​​(e.g., Fig.14 The charge generation layer CGL2 may supply holes to the lower light emitting layers OLE1, OLE2, and OLE3 adjacent to the first stack body ST1, AE1, AE2, and AE3 in the second stack body ST2, and the p-type charge generation layer CGL2 may supply holes to the upper light emitting layers OLE1', OLE2', and OLE3' included in the second stack body ST2. The charge generation layer CGL may be arranged between the first stack body ST1 and the second stack body ST2 to provide charges to each of the light emitting layers, thereby improving emission efficiency and reducing driving voltage.

[0189] The first stack ST1 may be disposed on the first, second, and third pixel electrodes AE1, AE2, and AE3, and may further include a first hole transport layer HTL1, a first electron blocking layer EBL1, and a first electron transport layer ETL1.

[0190] The first hole transport layer HTL1 may be arranged on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, respectively. The first hole transport layer HTL1 may play a role in smoothly transporting holes and may include a hole transport material. The hole transport material may include a carbazole-based derivative (such as N-phenylcarbazole and polyvinylcarbazole), a fluorene-based derivative, a triphenylamine-based derivative (such as TPD (N, N'-bis (3-methylphenyl) -N, N'-diphenyl-[1, 1-biphenyl] -4, 4'-diamine), TCTA (4, 4', 4 "-tri (N-carbazolyl) triphenylamine) and the like), NPB (N, N'-di (1-naphthyl) -N, N'-diphenylbenzidine), TAPC (4, 4'-cyclohexylene bis [N, N-bis (4-methylphenyl) benzylamine]) and the like, but the embodiment is not limited thereto.

[0191] The first electron blocking layer EBL1 may be located on the first hole transport layer HTL1, and may be located between the first hole transport layer HTL1 and the lower light emitting layers OLE1, OLE2, and OLE3. For example, the first electron blocking layer EBL1 may be located between the first hole transport layer HTL1 and the third lower light emitting layer OLE3. The first electron blocking layer EBL1 may include a hole transport material and a metal or a metal compound that prevents electrons generated in the lower light emitting layers OLE1, OLE2, and OLE3 from being transferred to the first hole transport layer HTL1. In some embodiments, the above-mentioned first hole transport layer HTL1 and the first electron blocking layer EBL1 may also be formed as a single layer in which the corresponding materials are mixed.

[0192] The first electron transport layer ETL1 may be disposed on the lower light emitting layers OLE1, OLE2, and OLE3, and may be disposed between the charge generation layer CGL and the lower light emitting layers OLE1, OLE2, and OLE3. In some embodiments, the first electron transport layer ETL1 may include an electron transport material such as Alq. 3 (tris(8-hydroxyquinoline)aluminum), TPBi(1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)phenyl), BCP(2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen(4,7-diphenyl-1,10-phenanthroline), TAZ(3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ(4-(naphthalene-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD(2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), BAlq(bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum), Bebq 2 (bis(benzoquinoline-10-hydroxy)beryllium), ADN(9,10-di(naphthalene-2-yl)anthracene), and mixtures thereof. However, embodiments are not limited to the type of the electron transport material.

[0193] The second stack ST2 may be disposed on the charge generation layer CGL, and may further include a second hole transport layer HTL2, a second electron blocking layer EBL2, a buffer layer BUL, and a second electron transport layer ETL2.

[0194] The second hole transport layer HTL2 may be located on the charge generation layer CGL. The second hole transport layer HTL2 may be made of the same material as that of the first hole transport layer HTL1, or may also include one or more materials selected from materials such as those included in the first hole transport layer HTL1. The second hole transport layer HTL2 may be made into a single layer or multiple layers.

[0195] The second electron blocking layer EBL2 may be located on the second hole transport layer HTL2, and may be disposed between the second hole transport layer HTL2 and the upper light emitting layers OLE1', OLE2', and OLE3'. For example, the second electron blocking layer EBL2 may be located between the second hole transport layer HTL2 and the third upper light emitting layer OLE3'. The second electron blocking layer EBL2 may be made of the same material and the same structure as those of the first electron blocking layer EBL1, or may also include one or more materials selected from materials such as the material included in the first electron blocking layer EBL1.

[0196] The second electron transport layer ETL2 may be disposed on the upper light emitting layers OLE1', OLE2', and OLE3', and may be disposed between the upper light emitting layers OLE1', OLE2', and OLE3' and the common electrode CE. The second electron transport layer ETL2 may be made of the same material and the same structure as those of the first electron transport layer ETL1, or may also include one or more materials selected from materials such as those included in the first electron transport layer ETL1. The second electron transport layer ETL2 may be made into a single layer or a multilayer.

[0197] The buffer layer BUL may be disposed between the upper light emitting layers OLE1', OLE2', and OLE3' and the second electron transport layer ETL2. The buffer layer BUL may prevent holes from being transferred from the upper light emitting layers OLE1', OLE2', and OLE3' to the common electrode CE. The buffer layer BUL may include, for example, a hole transport layer material as a material having a hole property, but the embodiment is not limited thereto.

[0198] For example, the hole injection layer may be further arranged between the first stack body ST1 and the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 or between the second stack body ST2 and the charge generation layer CGL. For example, the hole injection layer HIL may be further arranged between the first stack body ST1 and the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The hole injection layer may play a role in injecting holes more smoothly into the lower light-emitting layers OLE1, OLE2, and OLE3 and the upper light-emitting layers OLE1', OLE2', and OLE3'. In some embodiments, the hole injection layer may be made of one or more selected from the group consisting of copper phthalocyanine (CuPc), poly (3,4-ethylenedioxythiophene) (PEDOT), polyaniline (PANI), and N,N-dinaphthyl-N,N'-diphenylbenzidine (NPD), but the embodiment is not limited thereto.

[0199] For example, the electron injection layer may be further located between the second electron transport layer ETL2 and the common electrode CE or between the charge generation layer CGL and the first stack ST1. The electron injection layer may play a role in smoothly injecting electrons, and may include Alq 3 (tris(8-hydroxyquinoline)aluminum), PBD, TAZ, spiro-PBD, BAlq, or SAlq. However, the embodiment is not limited thereto. For example, the electron injection layer may be a metal halide compound, and may be, for example, selected from MgF 2 , LiF, NaF, KF, RbF, CsF, FrF, LiI, NaI, KI, RbI, CsI, FrI and CaF 2One or more of the group consisting of, but the embodiment is not limited thereto. For example, the electron injection layer may also include a lanthanide-based material such as Yb, Sm or Eu. In another example, the electron injection layer may include both a metal halide material and a lanthanide-based material, such as RbI:Yb, KI:Yb, etc. In the case where the electron injection layer includes both a metal halide material and a lanthanide-based material, the electron injection layer may be formed by co-deposition of the metal halide material and the lanthanide-based material.

[0200] In the above Fig.14 In the embodiment, the charge generation layer CGL may be a common layer extending to the emission regions EA1, EA2, and EA3 and continuously arranged in the emission regions EA1, EA2, and EA3. Fig.14 In the embodiment, the charge generation layer CGL may be a common layer continuously arranged in the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. The charge generation layer CGL may play a role in generating and transferring electrons and holes that contribute to substantial light emission. In the case where the charge generation layer CGL is a common layer, leakage current may occur in which charges (e.g., electrons and holes) generated in light emitting areas adjacent to each other are transferred to light emitting areas adjacent to each other. For example, since light is emitted by leakage current in a light emitting area where light should not be emitted, color mixing may occur or an undesirable grayscale may be exhibited.

[0201] According to an embodiment, leakage current can be reduced by partially cutting off the charge generation layer CGL between the light emitting areas EA1, EA2 and EA3 to form pixel openings POP1, POP2 and POP3 that increase the path for charge movement, and unnecessary metal oxide layer USL can be omitted by forming pattern openings OPX1, OPX2 and OPX3 in the metal oxide layer USL.

[0202] like Fig.15 , Fig.16 and Fig.17As shown in the figure, the second passivation layer PAS2 and the pixel defining layer PDL may include pixel openings POP1, POP2 and POP3. The pixel openings POP1, POP2 and POP3 may be arranged between the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 so as not to overlap with the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3. The pixel openings POP1, POP2 and POP3 may overlap with the light blocking layer BM. In an embodiment, it is shown that the pixel openings POP1, POP2 and POP3 are arranged between the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3, but the embodiment is not limited thereto, and some of the pixel openings POP1, POP2 and POP3 may also be omitted. The pixel openings POP1, POP2, and POP3 may include a first pixel opening POP1 disposed between the first and second emission areas EA1 and EA2, a second pixel opening POP2 disposed between the second and third emission areas EA2 and EA3, and a third pixel opening POP3 disposed between the third emission area EA3 and the first emission area EA1.

[0203] The common layers of the organic layer EL may be separated from each other in the pixel openings POP1, POP2, and POP3. The pixel defining layer PDL and the second passivation layer PAS2 may be layers made of organic materials, and may have a very thick thickness compared to layers made of inorganic materials. For example, the pixel defining layer PDL and the second passivation layer PAS2 may have a thickness of about several microns. The sides of the pixel openings POP1, POP2, and POP3 formed in the pixel defining layer PDL and the second passivation layer PAS2 may be tapered to allow common layers (such as the hole injection layer HIL, the first hole transport layer HTL1, the first electron transport layer ETL1, the charge generation layer CGL, the second hole transport layer HTL2, the buffer layer BUL, and the second electron transport layer ETL2) having a very thin thickness to be separable. Accordingly, since the common layers are separated from each other in the pixel openings POP1, POP2, and POP3, leakage current in which charges (eg, electrons and holes) generated in light emitting regions adjacent to each other are transferred to light emitting regions adjacent to each other may be reduced.

[0204] The light blocking layer BM may be arranged on the encapsulation layer TFEL. The light blocking layer BM may include pattern openings OPX1, OPX2, and OPX3 arranged to overlap with the pixel openings POP1, POP2, and POP3. The pattern openings OPX1, OPX2, and OPX3 may be arranged between the light emitting areas EA1, EA2, and EA3 and may overlap with the light blocking layer BM. For example, the first pattern opening OPX1 may overlap with the first pixel opening POP1. The second pattern opening OPX2 may overlap with the second pixel opening POP2, and the third pattern opening OPX3 may overlap with the third pixel opening POP3.

[0205] The area or size of each of the pattern openings OPX1, OPX2, and OPX3 may be the same as the area or size of each of the pixel openings POP1, POP2, and POP3. For example, the area or size of the first pattern opening OPX1 may be the same as the area or size of the first pixel opening POP1, the area or size of the second pattern opening OPX2 may be the same as the area or size of the second pixel opening POP2, and the area or size of the third pattern opening OPX3 may be the same as the area or size of the third pixel opening POP3.

[0206] In some embodiments, the area or size of each of the pattern openings OPX1, OPX2, and OPX3 may be larger than the area or size of each of the pixel openings POP1, POP2, and POP3. In some embodiments, the area or size of each of the pattern openings OPX1, OPX2, and OPX3 may be smaller than the area or size of each of the pixel openings POP1, POP2, and POP3.

[0207] As described above, in the display device 10 according to the embodiment, leakage current can be reduced by forming pixel openings POP1, POP2, and POP3 formed in the pixel defining layer PDL and the second passivation layer PAS2 between the light emitting areas EA1, EA2, and EA3. For example, the unnecessary metal oxide layer USL can be omitted by forming pattern openings OPX1, OPX2, and OPX3 of the metal oxide layer USL overlapping with the pixel openings POP1, POP2, and POP3.

[0208] Fig.18 is a schematic diagram in a case where the display device according to the embodiment is applied to a vehicle.

[0209] Reference Fig.18 The display device 10 according to the embodiment may be, for example, a display device applied to a vehicle. The vehicle may include a vehicle body forming the appearance of the vehicle and an interior space defined by the vehicle body. The vehicle body may include a windshield W that protects a driver and a passenger from external influences and provides visibility for the driver. Fig.18 As shown in , the display device 10 may be provided in the interior space.

[0210] In an embodiment, the display device 10 may be arranged on an instrument panel provided in an interior space. For example, the display device 10 may be arranged on an instrument panel located in front of a driver's seat to provide speed information to the driver, or may be arranged on an instrument panel located in front of a passenger's seat to provide entertainment information to the passenger, or may be arranged at a central portion of the instrument panel to provide map information, etc. Fig.18 There are shown a display device 10 arranged on a dashboard located in front of a driver's seat and a driver viewing the display screen of the display device 10. The driver can recognize (or visually recognize) the display screen of the display device 10 by light LGT1 emitted from the display device 10 toward the driver.

[0211] Among the light incident from the outside or inside of the vehicle, light UV in the ultraviolet wavelength band may be incident to the display device 10. Since the display device 10 includes the above-mentioned Figures 5 to 17 The metal oxide layer USL overlapped with the pixel defining layer PDL shown in FIG. 1 can thus block light UV in the ultraviolet wavelength band incident from the outside from being incident on the pixel defining layer PDL (see FIG. 1 ). Figure 6 Accordingly, the organic layer EL (see Figure 6 ) degradation and the common electrode CE (see Figure 6 ) oxidation, thereby reducing pixel shrinkage.

[0212] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the embodiments without departing from the principles of the utility model in essence. Therefore, the embodiments of the utility model disclosed are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A display device for a vehicle, characterized in that: The display device comprises: substrate; a light emitting element layer, the light emitting element layer being arranged on the substrate and comprising a pixel electrode, an organic layer and a common electrode; a pixel defining layer disposed on the substrate and including a plurality of openings exposing portions of the pixel electrode; An encapsulation layer, the encapsulation layer being arranged on the light emitting element layer; a metal oxide layer, the metal oxide layer being arranged on or in the encapsulation layer and overlapping the pixel defining layer; a light-blocking layer disposed on and overlapping the metal oxide layer; and A color filter layer is disposed on the light blocking layer and the encapsulation layer.

2. The display device according to claim 1, wherein: The metal oxide layer contacts an upper surface of the encapsulation layer and a lower surface of the light blocking layer.

3. The display device according to claim 1, wherein: The metal oxide layer has a thickness in the range of 10 nm to 10000 nm.

4. The display device according to claim 1, wherein: The metal oxide layer includes a plurality of opening holes overlapping the plurality of openings of the pixel defining layer.

5. The display device according to claim 4, characterized in that A size of each of the plurality of opening holes of the metal oxide layer and a size of each of the plurality of openings of the pixel defining layer are identical to each other.

6. The display device according to claim 4, characterized in that The size of each of the plurality of opening holes of the metal oxide layer is larger than the size of each of the plurality of openings of the pixel defining layer, and The width of the metal oxide layer is smaller than the width of the pixel defining layer.

7. The display device according to claim 4, characterized in that The light blocking layer includes a plurality of holes overlapping the plurality of openings of the pixel defining layer, and A size of each of the plurality of opening holes of the metal oxide layer is smaller than a size of each of the plurality of holes of the light blocking layer.

8. The display device according to claim 4, characterized in that The light blocking layer includes a plurality of holes overlapping the plurality of openings of the pixel defining layer, and A size of each of the plurality of opening holes of the metal oxide layer and a size of each of the plurality of holes of the light blocking layer are identical to each other.

9. The display device according to claim 1, wherein: The pixel defining layer includes a plurality of pixel openings arranged between adjacent pixel electrodes, and The light blocking layer includes a plurality of pattern openings overlapping the plurality of pixel openings.

10. A vehicle, characterized in that: The vehicle includes an instrument panel and a display device for the vehicle arranged on the instrument panel to display information, the display device including: substrate; a light emitting element layer, the light emitting element layer being arranged on the substrate and comprising a pixel electrode, an organic layer and a common electrode; a pixel defining layer disposed on the substrate and including a plurality of openings exposing portions of the pixel electrode; An encapsulation layer, the encapsulation layer being arranged on the light emitting element layer; a metal oxide layer, the metal oxide layer being arranged in or on the encapsulation layer and overlapping the pixel defining layer; a light-blocking layer disposed on the encapsulation layer and overlapping the metal oxide layer; and A color filter layer is disposed on the light blocking layer and the encapsulation layer.

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