Quantum chip, quantum chip packaging box and quantum computer

Abstract

The utility model discloses a quantum chip, a quantum chip packaging box and a quantum computer, and belongs to the technical field of quantum chip manufacturing. In the quantum chip, a first surface and a second surface opposite to a quantum bit layer and a third surface of a wiring layer are each provided with one or more of a microwave control line, a magnetic flux control line, a reading bus and a reading resonator, and circuits of the first surface and quantum bits are in different-plane capacitance coupling. According to the quantum chip, the wiring of the whole quantum chip is dispersed to the first surface, the second surface and the third surface, the wiring pressure of the wiring layer is relieved, the transverse size of the quantum chip can be reduced, and then the influence of a packaging cavity mode on the quantum bit performance is restrained; the lines on the first surface and the quantum bits are subjected to capacitive coupling through the quantum bit layer, so that the stability of the quantum chip is effectively improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of quantum chip manufacturing, in particular to a quantum chip, a quantum chip packaging box and a quantum computer. Background Art

[0002] At present, the structure of superconducting quantum chips is basically a two-layer chip structure. The two layers of chips are connected by flip-chip technology, which can alleviate the wiring pressure problem to a certain extent.

[0003] As the number of quantum bits increases, the wiring density increases dramatically, and the lateral size of the quantum chip will continue to increase. Since the lateral size of a quantum chip is much larger than its longitudinal size, the increase in the lateral size will make it difficult to suppress the packaging cavity mode corresponding to the quantum chip, which in turn affects the performance of the quantum bit.

[0004] Therefore, reducing the lateral size of the quantum chip and thereby suppressing the impact of the packaging cavity mode on the performance of the quantum bit is an urgent problem to be solved. Utility Model Content

[0005] The purpose of the utility model is to provide a quantum chip, a quantum chip packaging box and a quantum computer to solve the deficiencies in the prior art, and the utility model can reduce the lateral size of the quantum chip.

[0006] The solution of this application example is implemented through the following contents.

[0007] In a first aspect, an example of the present application proposes a quantum chip, including a quantum bit layer and a wiring layer;

[0008] The qubit layer includes a first surface and a second surface opposite to each other, and qubits arranged on the second surface, and the wiring layer includes a third surface close to the second surface;

[0009] The first surface, the second surface and the third surface are all configured with one or more of a microwave control line, a magnetic flux control line, a read bus and a read resonator included in the quantum chip, and the line on the first surface and the quantum bit are capacitively coupled in different planes;

[0010] The read resonator is coupled to the read bus and the quantum bit respectively, and the microwave control line and the magnetic flux control line are coupled to the quantum bit respectively.

[0011] According to some examples of the present application, the second surface of the quantum bit layer and the third surface of the wiring layer are connected through a support.

[0012] According to some examples of the present application, the support member is a superconductor.

[0013] According to some examples of the present application, the support member includes an indium column;

[0014] The indium column includes a first end and a second end, the first end is connected to the second surface, and the second end is connected to the third surface.

[0015] According to some examples of the present application, the coupling mode between the circuit on the second surface and the quantum bit is capacitive coupling or inductive coupling.

[0016] According to some examples of the present application, the coupling mode between the lines of the wiring layer and the quantum bits configured in the quantum bit layer is capacitive coupling or inductive coupling.

[0017] According to some examples of the present application, the quantum chip further includes a first port, the first port being connected to the microwave control line and being used to input a microwave control signal to the microwave control line;

[0018] And / or, the quantum chip further comprises a second port, the second port being coplanarly connected to the magnetic flux control line and being used to input a magnetic flux control signal to the magnetic flux control line;

[0019] And / or, the quantum chip further includes a third port, wherein the third port is connected to the read bus and is configured to input a read signal to the quantum bit and output a read output signal fed back by the quantum bit.

[0020] In a second aspect, an example of the present application provides a quantum chip packaging box, comprising the quantum chip described in the first aspect above, wherein the quantum chip packaging box further comprises a base, side walls and a top cover;

[0021] The base is used to place the quantum chip;

[0022] The side wall has a first connection port, a second connection port and a third connection port;

[0023] The first connection port is connected to the first port of the microwave control line in the quantum chip, and is used to input a microwave control signal to the microwave control line;

[0024] The second connection port is connected to the second port of the magnetic flux control line in the quantum chip, and is used to input a magnetic flux control signal to the magnetic flux control line;

[0025] The third connection port is connected to the third port of the read bus in the quantum chip, and is used to input a read signal to the quantum bit and output a read output signal fed back by the quantum bit.

[0026] According to some examples of the present application, the first connection port and the first port are located in the same plane;

[0027] The second connection port and the second port are located in the same plane;

[0028] The third connection port and the third port are located in the same plane.

[0029] In a second aspect, an example of the present application proposes a quantum computer, comprising the quantum chip described in the first aspect above, or the quantum chip packaging box described in the second aspect above.

[0030] In the quantum chip of the aforementioned example of the present application, the microwave control line, the flux control line, the read bus and the read resonator are optionally configured on the first surface, the second surface and the third surface of the wiring layer relative to the quantum bit layer. Compared with the prior art that all wiring is configured on the wiring layer, the technical solution of the present application disperses the wiring of the entire quantum chip to the surface of the quantum bit layer and the wiring layer, which reduces the wiring pressure of the wiring layer, effectively reduces the lateral size of the quantum chip, and further reduces the cavity mode of the quantum chip packaging box corresponding to the quantum chip, which is beneficial to protect the performance of the quantum bit in the quantum chip. In addition, in the quantum chip disclosed in this patent, the circuit on the first surface and the quantum bit are capacitively coupled through the quantum bit layer, which can effectively improve the stability of the quantum chip.

[0031] The quantum chip packaging box and quantum computer provided by the utility model have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] For a clearer explanation, the following briefly introduces the drawings required for the description.

[0033] Figure 1 This is a schematic diagram of the structure of a quantum chip in an example of this application;

[0034] Figure 2 This is a schematic diagram of the structure of a quantum chip in another example of this application;

[0035] Figure 3 This is a schematic diagram of the structure of a quantum chip packaging box in another example of the present application. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.

[0037] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0039] At present, the structure of superconducting quantum chips is basically a two-layer chip structure, using the opposite surfaces of the two-layer chips for wiring layout. However, as the number of quantum bits increases, the layout pressure of the two-layer chip gradually increases, the wiring density on the quantum chip increases dramatically, and the crosstalk problem faced by the quantum bits becomes more and more serious. In addition, as the number of quantum bits increases, the lateral length and width of the quantum chip wiring layer increase, and the corresponding cavity membrane type will have a more serious impact on the performance of the quantum bits.

[0040] Therefore, how to reduce the lateral size of the quantum chip, suppress the impact of the packaging cavity mode on the performance of the quantum bit, and reduce the wiring density of the quantum chip is an urgent problem to be solved.

[0041] Based on this, Figure 1 As shown, an embodiment of the utility model discloses a quantum chip including a quantum bit layer 100 and a wiring layer 200;

[0042] The qubit layer 100 includes a first surface 110 and a second surface 120 opposite to each other, and a qubit 111 disposed on the second surface 120 , and the wiring layer 200 includes a third surface 130 close to the second surface 120 ;

[0043] The first surface 110, the second surface 120 and the third surface 130 are all configured with one or more of the microwave control lines 112, the magnetic flux control lines 113, the read bus 114 and the read resonator 115 included in the quantum chip, and the lines on the first surface 110 and the quantum bits 111 are capacitively coupled in different planes;

[0044] The read resonator 115 is coupled to the read bus 114 and the quantum bit 111 , respectively. The microwave control line 112 and the magnetic flux control line 113 are coupled to the quantum bit 111 , respectively.

[0045] Among them, the quantum chip layer 100 includes a substrate and circuits located on a first surface 110 and a second surface 120. All quantum bits 111 of the quantum chip are distributed on the second surface 120, and all circuits of each type are arranged on the same surface. For example, all microwave control lines 112 are located on the first surface 110, and all reading resonators 115 are located on the second surface 120, avoiding the risk of upper and lower routing of the same type of circuits.

[0046] It should be noted that the present application does not specifically limit the positions of the microwave control line 112 , the magnetic flux control line 113 , the read bus 114 , and the read resonator 115 , which can be selected as needed.

[0047] Specifically, the first surface 110, the second surface 120 and the third surface 130 are all configured with circuits, and the qubit 111 is configured on the second surface 120. The circuits on the first surface 110 and the qubits 111 on the second surface 120 transmit signals by means of in-plane capacitive coupling, without the need to set a through hole in the substrate of the qubit layer 100. The qubit 111 has a first coupling port, and each type of circuit on the first surface 110 has a second coupling port. It should be noted that the first coupling port of the qubit 111 and the second coupling port of the circuit on the first surface 110 overlap in the vertical projection, and a capacitor is formed between the coupling port of the qubit 111 and the coupling port of the circuit corresponding to the overlapping area, and the substrate of the qubit layer 100 corresponding to the overlapping area serves as the intermediate medium of the capacitor. Based on this, the thickness and material of the substrate of the qubit layer 100 determine the coupling strength between the circuit on the first surface 110 and the qubit 111.

[0048] In the quantum chip disclosed in the utility model, the first surface 110, the second surface 120 and the third surface 130 are all configured with one or more of the microwave control line 112, the flux control line 113, the read bus 114 and the read resonator 115, and the wiring of the entire quantum chip is dispersed to the first surface 110, the second surface 120 and the third surface 130, which reduces the wiring density of each layer and reduces the influence of line crosstalk. Compared with the structure that only uses the two opposite surfaces of the two-layer chip for wiring, the structure disclosed in the utility model uses the two surfaces of the intermediate quantum bit layer 100 to disperse the wiring pressure of the wiring layer 200, which can effectively reduce the size of the wiring layer 200, thereby reducing the length and width of the quantum chip, and suppressing the impact of the package cavity mode on the performance of the quantum bit 111. In addition, the circuit of the first surface 110 and the quantum bit 111 of the second surface 120 are coupled by different surface capacitance, and the substrate of the quantum bit layer 100 is used as the intermediate dielectric layer of the capacitor, without the need to set a through hole in the substrate of the quantum bit layer 100 for signal transmission, which can improve the stability of the quantum chip and effectively reduce the difficulty of preparing the quantum chip.

[0049] In one embodiment of the present application, the second surface 120 of the quantum bit layer 100 and the third surface 130 of the wiring layer 200 are connected via a support.

[0050] Specifically, since both the second surface 120 and the third surface 130 are provided with circuits, support pillars are provided to separate the quantum chip layer and the wiring layer 200 to protect the circuits on the second surface 120 and the third surface 130 .

[0051] In one embodiment of the present application, the support member is a superconductor.

[0052] The support member in the quantum chip disclosed in the utility model can be selected as a superconducting material such as an indium column, or a non-superconducting material. However, no matter what material the support member is made of, the support member is a structural component that supports and connects the second surface 120 and the third surface 130, rather than a signal line.

[0053] In one embodiment of the present application, the support member includes an indium column;

[0054] The indium column includes a first end and a second end. The first end is connected to the second surface 120 , and the second end is connected to the third surface 130 .

[0055] The support member includes an indium column. Since the support member is a non-signal line, the indium column does not need to be used as a transmission channel for transmitting signals, thereby avoiding the high production quality requirement of the indium column used for signal transmission.

[0056] In one embodiment of the present application, the coupling mode between the circuit on the second surface 120 and the quantum bit 111 is capacitive coupling or inductive coupling.

[0057] Specifically, since the quantum bit 111 is located on the second surface 120 , when the circuit on the second surface 120 and the quantum bit 111 are coupled, an inductor or capacitor can be set between the circuit and the quantum bit 111 to achieve inductive or capacitive coupling between the circuit on the second surface 120 and the quantum bit 111 .

[0058] In one embodiment of the present application, the coupling mode between the lines of the wiring layer 200 and the quantum bits 111 configured in the quantum bit layer 100 is capacitive coupling or inductive coupling.

[0059] Specifically, since the second surface 120 and the third surface 130 are connected via a support member, an inductor or capacitor may be provided between the circuit on the third surface 130 and the quantum bit 111 to achieve inductive or capacitive coupling between the circuit on the third surface 130 and the quantum bit 111 .

[0060] by Figure 2 For example (the support is not shown in the figure), the quantum bit 111 is located on the second surface 120, the microwave control line 112 is located on the third surface 210, the magnetic flux control line 113 is located on the first surface 110, and the read bus 114 and the read resonator 115 are located on the second surface 120, wherein a capacitor is connected between the quantum bit 111 and the microwave control line 112 for capacitive coupling, an inductor is connected between the quantum bit 111 and the read resonator 115 for inductive coupling, and a capacitor is connected between the read bus 114 and the read resonator 115 for capacitive coupling. It should be noted that the coupling mode between the line on the third surface 210 and the quantum bit 111 can be selected as needed, and the coupling mode between the line on the second surface 120 and the quantum bit 111 can be selected as needed.

[0061] Since the quantum bit 111 is respectively connected to the microwave control line 112 , the magnetic flux control line 113 and the reading resonator 115 , the first surface 110 , the second surface 120 and the third surface 210 are all configured with one of the microwave control line 112 , the magnetic flux control line 113 and the reading resonator 115 .

[0062] like Figure 3 As shown, in one embodiment of the present application, the quantum chip further includes a first port 310, and the first port 310 is connected to the microwave control line 112, and is used to input a microwave control signal to the microwave control line 112;

[0063] And / or, the quantum chip further comprises a second port 410, the second port 410 is coplanarly connected to the magnetic flux control line 113, and is used to input a magnetic flux control signal to the magnetic flux control line 113;

[0064] And / or, the quantum chip further includes a third port 510 , which is connected to the read bus 114 and is used to input a read signal to the quantum bit 111 and output a read output signal fed back by the quantum bit 111 .

[0065] Among them, since the microwave control line 112 transmits high-frequency signals, the first port 310 and the microwave control line 112 can be connected in the same plane or in different planes by capacitive coupling. For example, when the microwave control line 112 is located on the second surface 120, the first port 310 can be located on the first surface 110 and connected to the microwave control line 112 by different planes by capacitive coupling. The first port 310 can also be located on the third surface 210 and connected to the microwave control line 112 by capacitive coupling or inductive coupling. Since the read bus 114 also transmits high-frequency signals, the distribution principle of the third port 510 is consistent with the distribution principle of the first port 310. Since the magnetic flux control line 113 transmits a DC signal, the second port 410 and the magnetic flux control line 113 need to be electrically connected in the same plane. It should be noted that the present application does not make specific restrictions on the distribution positions of the first port 310, the second port 410 and the third port 510, and can be designed as needed in practical applications.

[0066] Specifically, the first port 310 of the quantum chip is bonded to the packaging box for obtaining and inputting a microwave control signal to the microwave control line 112; the second port 410 of the quantum chip is bonded to the packaging box for obtaining and inputting a flux control signal to the flux control line 113; the third port 510 of the quantum chip is bonded to the packaging box for inputting a read signal to the quantum bit 111 and outputting a read output signal fed back by the quantum bit 111.

[0067] In one embodiment of the present application, the first port 310, the second port 410 and the third port 510 are optionally distributed on the first surface 110 or the third surface 210. Based on the above port distribution principle, the microwave control line 112 is distributed on the first surface 110 or the second surface 120 or the third surface 210, the flux control line 113 is distributed on the first surface 110 or the third surface 210, and the read bus 114 is distributed on the first surface 110 or the second surface 120 or the third surface 210. Figure 3 For example, the first ports 310 are distributed on the first surface 110 , the second ports 410 are distributed on the first surface 110 , and the third ports 510 are distributed on the third surface 210 .

[0068] In one embodiment of the present application, the utility model provides a quantum chip packaging box for packaging the quantum chip disclosed above, the quantum chip packaging box further comprising a base, a side wall and a top cover;

[0069] The base is used to place the quantum chip;

[0070] The side wall has a first connection port 320 , a second connection port 420 and a third connection port 520 ;

[0071] The first connection port 320 is connected to the first port 310 of the microwave control line 112 in the quantum chip, and is used to input a microwave control signal to the microwave control line 112;

[0072] The second connection port 420 is connected to the second port 410 of the magnetic flux control line 113 in the quantum chip, and is used to input a magnetic flux control signal to the magnetic flux control line 113;

[0073] The third connection port 520 is connected to the third port 510 of the read bus 114 in the quantum chip, and is used to input a read signal to the quantum bit 111 and output a read output signal fed back by the quantum bit 111 .

[0074] Specifically, the quantum chip packaging box connects the quantum chip to the first connection port 320 , the second connection port 420 , and the third connection port 520 respectively by bonding to perform signal transmission.

[0075] Since the size of the quantum chip packaging box is determined by the size of the quantum chip wiring layer 200, when the length and width of the quantum chip are reduced, the size of the corresponding quantum chip packaging box is also reduced, thereby suppressing the influence of the cavity mode of the packaging box on the quantum bit 111 and protecting the performance of the quantum bit 111.

[0076] In one embodiment of the present application, the first connection port 320 and the first port 310 are located in the same plane;

[0077] The second connection port 420 and the second port 410 are located on the same plane;

[0078] The third connection port 520 and the third port 510 are located on the same plane.

[0079] Specifically, the first connection port 320 is coplanarly bonded to the first port 310, the second connection port 420 is coplanarly bonded to the second port 410, and the third connection port 520 is coplanarly bonded to the third port 510, which can shorten the length of the bonding wire, facilitate distortion-free transmission of the signal and reduce signal crosstalk between the bonding wires.

[0080] In one embodiment of the present application, the utility model provides a quantum computer, comprising the above-mentioned quantum chip, or the above-mentioned quantum chip packaging box.

[0081] Regarding the technical effects of the quantum chip packaging box and quantum computer of the above-mentioned embodiment, reference can be made to other embodiments of this specification for comparative explanation, and no further description will be given here.

[0082] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0083] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A quantum chip, characterized in that: Includes quantum bit layer and wiring layer; The qubit layer includes a first surface and a second surface opposite to each other, and qubits arranged on the second surface, and the wiring layer includes a third surface close to the second surface; The first surface, the second surface and the third surface are all configured with one or more of a microwave control line, a magnetic flux control line, a read bus and a read resonator included in the quantum chip, and the line on the first surface and the quantum bit are capacitively coupled in different planes; The read resonator is coupled to the read bus and the quantum bit respectively, and the microwave control line and the magnetic flux control line are coupled to the quantum bit respectively.

2. The quantum chip according to claim 1, characterized in that: The second surface of the quantum bit layer and the third surface of the wiring layer are connected via a support.

3. The quantum chip according to claim 2, characterized in that: The support member is a superconductor.

4. The quantum chip according to claim 3, characterized in that: The support member includes an indium column; The indium column includes a first end and a second end, the first end is connected to the second surface, and the second end is connected to the third surface.

5. The quantum chip according to claim 1, characterized in that: The coupling mode between the circuit on the second surface and the quantum bit is capacitive coupling or inductive coupling.

6. The quantum chip according to claim 1, characterized in that: The coupling mode between the lines of the wiring layer and the quantum bits configured in the quantum bit layer is capacitive coupling or inductive coupling.

7. The quantum chip according to claim 1, characterized in that: The quantum chip further comprises a first port, the first port being connected to the microwave control line and being used to input a microwave control signal to the microwave control line; And / or, the quantum chip further comprises a second port, the second port being coplanarly connected to the magnetic flux control line and being used to input a magnetic flux control signal to the magnetic flux control line; And / or, the quantum chip further includes a third port, wherein the third port is connected to the read bus and is configured to input a read signal to the quantum bit and output a read output signal fed back by the quantum bit.

8. A quantum chip packaging box, comprising the quantum chip according to any one of claims 1 to 7, characterized in that: The quantum chip packaging box also includes a base, side walls and a top cover; The base is used to place the quantum chip; The side wall has a first connection port, a second connection port and a third connection port; The first connection port is connected to the first port of the microwave control line in the quantum chip, and is used to input a microwave control signal to the microwave control line; The second connection port is connected to the second port of the magnetic flux control line in the quantum chip, and is used to input a magnetic flux control signal to the magnetic flux control line; The third connection port is connected to the third port of the read bus in the quantum chip, and is used to input a read signal to the quantum bit and output a read output signal fed back by the quantum bit.

9. The quantum chip packaging box according to claim 8, characterized in that: The first connection port and the first port are located in the same plane; The second connection port and the second port are located in the same plane; The third connection port and the third port are located in the same plane.

10. A quantum computer, characterized in that: The invention comprises the quantum chip according to any one of claims 1 to 7, or the quantum chip packaging box according to claim 8 or 9.

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