Groove type silicon carbide MOSFET device and preparation method thereof

Abstract

The invention provides a trench type silicon carbide MOSFET device and a preparation method thereof, and the preparation method comprises the following steps: providing a semiconductor substrate, forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on the semiconductor substrate, forming a well region and a source region in the epitaxial layers, etching to form a virtual groove, wherein the virtual groove extends into the third epitaxial layer from the source region; ion implantation is carried out in the virtual groove to form an ion implantation region, the ion implantation region extends to the first epitaxial layer, and the conduction type of the ion implantation region is the same as that of the well region; respectively depositing a first insulating layer and a first polycrystalline silicon layer in the virtual groove to form a virtual groove structure, then forming a gate groove structure, forming a gate side wall on the side wall, higher than the source region, of a second polycrystalline silicon layer in the gate groove, and etching the second polycrystalline silicon layer in the gate groove until the top of the second polycrystalline silicon layer is lower than the upper surface of the source region; and forming an interlayer dielectric layer and a front metal layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices and related manufacturing, and in particular, to a trench-type silicon carbide MOSFET device and a manufacturing method. BACKGROUND

[0002] Wide-bandgap semiconductor material silicon carbide (SiC) has become one of the key materials for manufacturing high-temperature, high-voltage, and high-power semiconductor devices suitable for extreme working environments due to its excellent characteristics such as high critical breakdown field, high thermal conductivity, and high electron saturation velocity. Compared with traditional silicon-based devices, silicon carbide devices have significant advantages in terms of voltage withstand capability, switching frequency, and high-temperature working stability, and are particularly suitable for power conversion and control applications in power electronic systems.

[0003] In silicon carbide power devices, metal-oxide-semiconductor field-effect transistors (MOSFETs) are a representative structure whose technology development has evolved from a planar gate structure to a trench gate structure. Early planar gate silicon carbide MOSFET structures are relatively simple and mature in process, and have been commercialized in multiple fields. However, the planar structure has problems such as lateral arrangement of the conduction channel, low chip area utilization rate, and significant junction field effect transistor (JFET) effect, which leads to a larger specific on-resistance of the device and restricts further improvement of its performance.

[0004] To overcome the above-mentioned defects, the industry has gradually shifted to trench gate structure technology. Trench gate silicon carbide MOSFETs arrange the conduction channel vertically instead of laterally, which not only significantly improves the integration density of the chip, but also effectively eliminates the JFET region resistance, thereby greatly reducing the specific on-resistance of the device and improving the current driving capability. However, the trench structure also introduces new technical challenges, especially the corner region at the bottom of the trench is prone to electric field concentration under high-voltage working conditions, causing the gate oxide layer at this location to bear an excessively high electric field. When the gate oxide electric field exceeds the critical threshold, it will seriously affect the long-term reliability of the device and even cause gate oxide breakdown.

[0005] To solve the above-mentioned electric field concentration problem, the existing technology usually adopts a gate oxide shielding structure, such as a P-type shielding region at the bottom of the trench, to alleviate the electric field peak. Although such technology can improve the gate oxide reliability to some extent, it often has adverse effects such as a decrease in device output characteristics and an increase in on-resistance, which limits the full performance of the trench-type silicon carbide MOSFET.

[0006] At present, the silicon carbide MOSFET products commercialized in China are still mainly of the planar gate structure, and there is a certain gap in specific on-resistance, power density, high-temperature high-frequency characteristics and other aspects compared with the international advanced level. Therefore, in order to promote the development of domestic silicon carbide MOSFET technology to a higher performance direction, it is urgent to develop a new structure of trench-type silicon carbide MOSFET with independent intellectual property rights, taking into account high withstand voltage and low on-resistance, and its supporting manufacturing process, so as to break through the existing technical bottleneck and meet the increasing demand for high-efficiency and high-reliability power semiconductor devices.

[0007] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include information that does not constitute prior art known to those skilled in the art. SUMMARY

[0008] In view of the problems in the prior art, the purpose of the present application is to provide a trench-type silicon carbide MOSFET device and a preparation method, which breaks the inherent contradictory relationship between on-resistance and breakdown voltage in existing silicon carbide power MOSFETs.

[0009] Specifically, the first aspect of the present application provides a trench-type silicon carbide MOSFET preparation method, which comprises the following steps: providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, the epitaxial layer comprising a first epitaxial layer, a second epitaxial layer and a third epitaxial layer, the doping concentration of the second epitaxial layer being greater than the doping concentration of the first epitaxial layer; forming a well region and a source region in the epitaxial layer; etching to form a virtual trench, the virtual trench extending from the source region into the third epitaxial layer; performing ion implantation in the virtual trench and depositing a carbon film layer, and after annealing, forming an ion implantation region, the ion implantation region extending to the first epitaxial layer, the conductivity type of the ion implantation region being the same as that of the well region; depositing a first insulating layer and a first polysilicon layer in the virtual trench to form a virtual trench structure; depositing a hard mask layer, patterning the hard mask layer and etching to obtain a gate trench, the gate trench being arranged between two virtual trench structures and penetrating the well region, forming a second insulating layer on the sidewall of the gate trench, and depositing a second polysilicon layer in the gate trench to form a gate trench structure; removing the hard mask layer, depositing a silicon nitride layer and etching back the silicon nitride layer, the second polysilicon layer in the gate trench being higher than the sidewall of the source region to form a gate sidewall; forming a low viscosity polymer layer or photoresist layer between the gate trench structures, etching the second polysilicon layer in the gate trench until the top of the second polysilicon layer is below the upper surface of the source region; Forming an interlayer dielectric layer and a front side metal layer on the semiconductor substrate, respectively.

[0010] According to the first aspect of the present application, the thickness of the second epitaxial layer is between 0.2-0.4 μm; and / or

[0011] The thickness of the first epitaxial layer is between 2-100 μm; and / or

[0012] The thickness of the third epitaxial layer is between 2-4 μm.

[0013] According to the first aspect of the present application, the doping concentration of the first epitaxial layer is between 5x1018-5x1019cm-3; and / or 14 -5x1019cm-3; and / or 16 -5x1019cm-3. -3

[0014] The doping concentration of the third epitaxial layer is between 5x1018-5x1019cm-3. 14 -5x1019cm-3. 16 -5x1019cm-3. -3

[0015] According to the first aspect of the present application, the doping concentration of the second epitaxial layer is 2-5 times the doping concentration of the first epitaxial layer; and / or

[0016] The doping concentration of the third epitaxial layer is the same as the doping concentration of the first epitaxial layer.

[0017] According to the first aspect of the present application, the depth of the bottom of the dummy trench from the bottom of the third epitaxial layer is greater than 0.2 μm; or

[0018] The depth of the bottom of the dummy trench from the bottom of the third epitaxial layer is between 0.3-0.5 μm.

[0019] According to the first aspect of the present application, the P-type doping concentration at the junction of the well region and the source region is between 1x1018-3x1019cm-3. 17 -3x1019cm-3. 17 -3x1019cm-3. -3

[0020] According to the first aspect of the present application, the depth of the ion implant region into the first epitaxial layer is greater than 0.1 μm; or

[0021] The depth of the ion implant region into the first epitaxial layer is between 0.15-0.25 μm.

[0022] ​​​According to the first aspect of the present application, the distance between the bottom of the gate trench and the bottom of the well region is greater than 0.3 μm; and / or

[0023] The distance between the bottom of the gate trench and the bottom of the dummy trench is between 0.7-1.2 μm.

[0024] The second aspect of the present application provides a trench-type silicon carbide MOSFET device, which is prepared by the trench-type silicon carbide MOSFET preparation method provided in the first aspect.

[0025] According to the second aspect of the present application, the trench-type silicon carbide MOSFET device comprises: a semiconductor substrate; an epitaxial layer disposed on the semiconductor substrate, the epitaxial layer comprising a first epitaxial layer, a second epitaxial layer and a third epitaxial layer, the doping concentration of the second epitaxial layer being greater than the doping concentration of the first epitaxial layer; a well region and a source region disposed in the epitaxial layer; a dummy trench and a gate trench alternately arranged in the source region; the dummy trench extends from the source region into the third epitaxial layer, and an ion implantation region is disposed on the sidewall and bottom wall of the dummy trench, the ion implantation region extending to the first epitaxial layer, the ion implantation region having the same conductivity type as the well region, and a first insulating layer and a first polysilicon layer are disposed in the dummy trench; the gate trench penetrates the well region, and a second insulating layer and a second polysilicon layer are disposed in the gate trench; an interlayer dielectric layer and a gate sidewall disposed on the upper part of the gate trench for isolating the source region; a front metal layer comprising a source metal layer and a gate metal layer, the source metal layer being connected to all source regions, and the gate metal layer comprising a plurality of gate metal units, each of the gate metal units being connected to the second polysilicon layer in each of the gate trenches.

[0026] Compared with the prior art, the trench type silicon carbide MOSFET device preparation method of the present application has no contact hole and gate trench overlaying alignment difficulty, and simultaneously adopts the virtual trench added on both sides of the gate trench as an indirect shielding structure to protect the gate oxide at the bottom of the gate trench, so as to realize the optimization of the on-resistance and the breakdown voltage, and more specifically, the virtual trench combines with the non-uniformly doped epitaxial layer to adjust the P-type doping structure at the bottom of the virtual trench, that is, the lateral size of the P-type doping at the bottom of the virtual trench D is reduced by using the higher doping concentration of the second epitaxial layer 122, so as to effectively reduce the negative influence of the JEFT effect caused by the adjacent P-type region on the on-resistance of the device. Simulation results show that, compared with the existing double-trench trench type silicon carbide MOSFET device, the on-resistance Rdson of the trench type silicon carbide MOSFET device of the present application is greatly reduced by 50%, but the breakdown voltage is only reduced by 1.5%. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application. Other features, objects, and advantages of the application will be apparent from a review of the detailed description of the non-limiting embodiments, with reference to the drawings. It will be apparent to those skilled in the art that the drawings described below are only some embodiments of the present application, and other drawings can be obtained from these drawings without creative labor. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus repeated description thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities.

[0028] Figure 1 Flow chart of the trench type silicon carbide MOSFET preparation method of an embodiment of the present application; Figures 2 to 12 Structural schematic diagram of the semiconductor substrate after each step of the trench type silicon carbide MOSFET preparation method of an embodiment of the present application; Figure 13 Output characteristic curve comparison diagram of the trench type silicon carbide MOSFET device of an embodiment of the present application and the existing trench type silicon carbide MOSFET device; Figure 14 Breakdown voltage (BV) curve comparison diagram of the trench type silicon carbide MOSFET device of an embodiment of the present application and the existing trench type silicon carbide MOSFET device. DETAILED DESCRIPTION

[0029] The present application is herein described, by way of example only, with the assistance of the accompanying drawings. As such, the particular details of the preferred embodiments can be varied, and implementation can be made to operate in different environments without departing from the spirit and scope of the application. It is to be noted that like or similar components, where appropriate, can be indicated by like reference numerals throughout the drawings.

[0030] The application will be described hereinafter with reference to the attached drawings which are given by way of illustration and are not limiting of the present application.

[0031] In the description of the present application, the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the present application. Such terms do not indicate a combination of some embodiments or examples with one or more other embodiments or examples unless explicitly stated. Furthermore, such terms do not necessarily refer to the same embodiment or example. In addition, such terms can refer to a specific feature, structure, material, or characteristic alone, or in combination with one or more other features, structures, materials, or characteristics. Other expressions of such terms shall be considered as equivalent to the terms themselves.

[0032] In order to clarify the present application, parts irrelevant to the explanation are omitted, and the same or similar components are designated by the same reference numerals throughout the drawings.

[0033] Throughout the specification, when a certain part is said to be "connected" to another part, it includes not only a case where the certain part is "directly connected" to the other part, but also a case where the certain part is "indirectly connected" to the other part with another part interposed therebetween. In addition, when a certain part is said to "include" a certain component, it does not exclude other components unless otherwise specifically stated, but means that other components can be further included.

[0034] When a certain part is said to be "on" another part, it can be directly on the other part, but can also be on the other part with another part interposed therebetween. When it is said in contrast that a certain part is "directly on" another part, there is no other part interposed therebetween.

[0035] Although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first interface and a second interface, etc. are distinguished from each other. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, steps, operations, elements, components, items, and / or groups but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, items, and / or groups thereof. As used herein, the terms "or" and "and / or" are construed to be inclusive, or mean any one or any combination. Thus, "A, B, or C" or "A, B, and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition are only present when the combination of elements, functions, steps, or actions are inherently mutually exclusive.

[0036] The professional terms used herein are only used to refer to specific embodiments and are not intended to limit the present application. The singular form used herein, unless the context clearly indicates otherwise, also includes the plural form. The meaning of "comprising" used in the specification is to specify the particular characteristics, regions, integers, steps, operations, elements, and / or components, and not to exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0037] Unless otherwise defined in the present application, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Terms defined in commonly used dictionaries are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0038] The trench-type silicon carbide MOSFET device and the preparation method thereof of the present application will be further described below in conjunction with the accompanying drawings and specific embodiments. It should be understood that each specific embodiment is not a limitation of the protection scope of the present application.

[0039] The present application provides a trench-type silicon carbide MOSFET preparation method, Figure 1 The flow chart of the trench-type silicon carbide MOSFET preparation method of an embodiment of the present application is shown in FIG. 1. Specifically, the preparation method comprises the following steps: Step S100: providing a semiconductor substrate 10, forming an epitaxial layer on the semiconductor substrate, the epitaxial layer comprising a first epitaxial layer 121, a second epitaxial layer 122 and a third epitaxial layer 123, the second epitaxial layer 122 having a doping concentration greater than that of the first epitaxial layer 121.

[0040] The semiconductor substrate 10 in step S100 can be an N-type substrate, such as an N-type doped (e.g. nitrogen-doped) SiC substrate, or a P-type doped (e.g. aluminum-doped) SiC substrate. Hereinafter, the semiconductor substrate is taken as a nitrogen-doped SiC substrate (corresponding to an n-type trench-type silicon carbide MOSFET device) as an example, the resistivity of the substrate can be between 0.015-0.025 ohm-cm, and the thickness is 350±25 μm. In actual operation, a buffer layer 11 can also be grown before the epitaxial layer, the thickness of the buffer layer 11 can be 1±0.1 μm. The conductivity type of the buffer layer 11, the first epitaxial layer 121, the second epitaxial layer 122 and the third epitaxial layer 123 is the same as that of the semiconductor substrate 10, i.e. if the semiconductor substrate 10 is N-type doped, the buffer layer 11 and the epitaxial layer are N-type doped; if the semiconductor substrate 10 is P-type doped, the buffer layer 11 and the epitaxial layer are P-type doped.

[0041] The doping concentration of the buffer layer 11 can be (1±0.1)×10 18 cm -3 . The doping concentration of the epitaxial layer and the thickness of the epitaxial layer depend on the voltage requirement of the target device, for example, the doping concentration of the epitaxial layer of a conventional 1200V SiC device can be ~5×10 15 cm -3 , and the thickness of the epitaxial layer can be ~10 μm. In the present application, the doping concentration of the epitaxial layer is variable, and the doping element is nitrogen. Specifically, the first epitaxial layer 121 formed on the buffer layer 11 has a doping concentration of 5×10 14 -5×10 16 cm -3 , and a thickness of 2-100 μm, for example, 5×10 15 cm -3 , and a thickness of 7.4 μm. The second epitaxial layer 122 is then formed, and has a doping concentration of 2-5 times that of the first epitaxial layer 121, and the thickness of the second epitaxial layer can be 0.2-0.4 μm, for example, the doping concentration is 1×10 16 cm -3 , and the thickness is 0.3 μm. The second epitaxial layer 122 can be uniformly doped or non-uniformly doped. Finally, the third epitaxial layer 123 is formed, and the doping concentration of the third epitaxial layer can be the same as that of the first epitaxial layer 121, or it can be different, and the doping concentration range can also be 5×10 14 -5×10 16 cm-3 between 2-4 μm, for example, a doping concentration of 5 x 1018cm 15 -3 2.3 μm.

[0042] Step S200: Forming the well region 2 and the source region 3 of the MOSFET device in the epitaxial layer, see Figure 2 The well region 2 and the source region 3 can be formed by ion implantation process. The well region 2 has a different conductivity type from the semiconductor substrate, i.e. P-type doping, and the implantation is P-type (e.g. Al) doping. In one embodiment, the ion implantation energy in the ion implantation process can be between 40-900 keV, the implantation ion dose can be 1 x 1014cm 12 - 1 x 1016cm 14 -2 at an implantation angle of 0° and an implantation temperature of ~500°C, and can be completed by 3-8 implantations, and the implantation depth is 0.6-0.8 μm. The source region 3 has the same conductivity type as the semiconductor substrate, i.e. N-type (e.g. nitrogen or phosphorus) doping in the upper part of the well region 2. In one embodiment, the ion implantation energy in the ion implantation process can be 25-200 keV, the implantation ion dose can be 1 x 1014cm 15 - 1 x 1016cm 16 -2 at an implantation angle of 0° and an implantation temperature of ~500°C, and can be completed by 3-5 implantations, and the implantation depth is 0.3-0.5 μm. In combination with the activation parameters of the subsequent ion implantation (~1750°C), the P-type doping concentration of the well region 2 at the junction with the source region 3 is controlled to be 1 x 1018cm 17 - 3 x 1019cm 17 -3 The length hi of the bottom of the source region 3 to the bottom of the well region 2 is between 0.2-0.5 μm.

[0043] Step S300: Etching to form a dummy trench D extending from the source region 3 into the third epitaxial layer 123, see Figure 3 ​​​​Specifically, a hard mask is deposited on the semiconductor substrate after step S200, and the hard mask is patterned. Using this pattern as a template, the semiconductor substrate is etched to form multiple virtual trenches D corresponding to the pattern on the hard mask. In one embodiment, the virtual trenches D formed on the semiconductor substrate after etching have a depth of 2.0-2.5 μm along the substrate thickness and a width of 0.35-0.7 μm. The angle between the virtual trenches D and the substrate surface is 88.5-90°, meaning the virtual trenches D are nearly perpendicular to the substrate surface. Preferably, the angle between the virtual trenches D and the substrate surface is 89.5°. Before performing step S400, the sidewalls of the virtual trenches D can be optionally repaired using a sacrificial oxygen process and / or an H2 repair process. The sacrificial oxygen process temperature is 1100-1200°C, and the H2 repair process temperature is 1350-1450°C.

[0044] Step S400: Ion implantation is performed in the virtual trench D and a carbon film layer is deposited. After annealing, an ion implantation region is formed, which extends to the first epitaxial layer 121. The conductivity type of the ion implantation region is the same as that of the well region 2, i.e., P-type ion implantation is performed, such as Al ion implantation.

[0045] In this embodiment, the ion implantation energy can be between 30-250 keV, and the implanted ion dose is 5 × 10⁻⁶. 14 -3×10 15 cm -2 The implantation angle is 0°, the process temperature is 500℃, the number of implantations can be 2-5 times, and the implantation depth is 0.5-1μm. After ion implantation, a carbon film is deposited in the virtual trench D. The carbon film can prevent carbon precipitation on the SiC substrate surface during subsequent annealing. Finally, the semiconductor substrate is annealed. The annealing temperature can be between 1650℃ and 1800℃, and the annealing time is between 5-30 minutes. The carbon film is removed after the annealing step.

[0046] After the above steps, the doping concentration of ion implantation region 4 is much greater than that of the epitaxial layer, which can reach 1×10⁻⁶. 18 -1×10 19 cm -3between 0.3-0.5 μm. After the step S400, the ion implantation region 4 extends through the second epitaxial layer 122 to the first epitaxial layer 121, and the depth of the ion implantation region 4 extending to the first epitaxial layer 121 is greater than 0.1 μm, preferably, the depth of the ion implantation region 4 extending to the first epitaxial layer 121 is between 0.15-0.25 μm, i.e. the ion implantation region 4 includes the columnar portion (the third epitaxial layer 123) on both sides of the virtual trench D, which is inverted trapezoidal in the second epitaxial layer 122 and arc-shaped in the first epitaxial layer 121, see Figure 4 This structure utilizes the high doping concentration of the second epitaxial layer 122 to reduce the lateral size of the P-type doping at the bottom region of the virtual trench D, thereby effectively reducing the negative impact of the JEFT effect caused by the adjacent P-type region on the on-resistance of the device.

[0047] Step S500: depositing a first insulating layer 5 and a first polysilicon layer 51 in the virtual trench D to form a virtual trench structure. The first insulating layer 5 can be a silicon dioxide layer, specifically, the silicon dioxide layer can be deposited by a chemical vapor deposition (CVD) process with a thickness of 500-1000 angstroms, then depositing an N-type doped first polysilicon layer 51 by a chemical vapor deposition (CVD) process with a thickness of 4000-8000 angstroms, and performing a polysilicon and silicon dioxide etching back process to remove the polysilicon and silicon dioxide on the surface of the silicon carbide substrate, after the etching back process, the height difference between the polysilicon in the virtual trench and the surface of the silicon carbide substrate is less than 1000 angstroms, and finally forming the virtual trench structure, see Figure 5 .

[0048] After forming the virtual trench, step S600 is performed: depositing a hard mask layer, patterning the hard mask layer and etching to obtain a gate trench H, the gate trench H is disposed between the two virtual trenches and penetrates the well region 2, a second insulating layer is formed on the sidewall of the gate trench H, and a second polysilicon layer is deposited in the gate trench to form a gate trench structure. The hard mask layer here is an oxide-nitride-oxide (ONO) three-layer stacked insulating structure, which can include a first silicon dioxide layer of 20-100 angstroms, a silicon nitride layer of 500-1000 angstroms, and a second silicon dioxide layer of 1-3 μm. A photoresist is spin-coated on the oxide-nitride-oxide and patterned, the hard mask layer is etched to obtain a patterned hard mask layer using the patterned photoresist as a template, the photoresist is removed, and the gate trench H is formed by etching the silicon carbide substrate using the patterned hard mask layer as a mask, see Figure 6wherein, due to the relatively thin first silicon dioxide layer and silicon nitride layer, marked as 61, and the second silicon dioxide layer, marked as 62. After the formation of the gate trench H, the thickness of the oxide-nitride-oxide is between 3000-5500 angstroms, which ensures that the width of the bottom of the subsequent gate spacer is between 0.1-0.2 μm.

[0049] The distance between the gate trench H and the dummy trench D is 0.3-0.6 μm, the depth can be 1.0-1.5 μm, the width is 0.3-0.7 μm, and the angle between the gate trench H and the substrate surface is 89-90°, preferably, the angle between the gate trench H and the substrate surface is 89.5°. The distance between the bottom of the gate trench H and the bottom of the well region 2 is greater than 0.3 μm, and the distance h2 between the bottom of the gate trench H and the bottom of the dummy trench D is between 0.7-1.2 μm.

[0050] Similarly, the gate trench H sidewall can be repaired by using a sacrificial oxide process and / or an H2 repair process, and then a 500 angstrom-800 angstrom second insulating layer (gate oxide layer) 7 is formed in the gate trench H by a thermal oxidation or atomic layer (ALD) process, see Figure 6 ; and finally, a 4000 angstrom-8000 angstrom N-type doped second polysilicon layer 71 (gate polysilicon) is deposited, and the gate polysilicon is etched to be flush with the hard mask layer by an etching process to form a gate trench, and the height difference between the gate trench polysilicon and the remaining hard mask layer 62 surface is less than 1000 angstroms.

[0051] Step S700: sequentially remove the hard mask layer by dry or wet method, deposit a silicon nitride layer and etch back the silicon nitride layer, and form a gate spacer 8 on the top of the gate trench structure which is higher than the sidewall of the source region 3, see Figure 7 The width of the bottom of the gate spacer 8 is between 0.1-0.2 μm.

[0052] Step S800: form a low viscosity polymer layer or photoresist layer G between the gate trench structures, and then etch the second polysilicon layer 71a in the gate trench by dry or wet etching process until the top of the second polysilicon layer 71a is lower than the upper surface of the source region 3, and finally remove the low viscosity polymer layer or photoresist layer G. Here, low viscosity refers to a liquid with a viscosity less than 10 centipoise (cP), and specifically, the low viscosity polymer or photoresist can be left only in the low viscosity polymer layer or photoresist layer between the gate trench structures by increasing the baking process and plasma bombardment process after spin coating, see Figure 8 The low viscosity polymer layer or photoresist layer G protects the polysilicon in the dummy trench. The top of the etched second polysilicon layer 71a in the gate trench is lower than the top of the source region 3, see Figure 9 , and the distance between the two is greater than 0.15 μm, but higher than the bottom of the source region 3 (the top of the well region 2), that is, the distance from the junction between the source region 3 and the well region 2 is greater than 0.1 μm.

[0053] Step S900: forming an interlayer dielectric layer (ILD) and a front metal layer on the semiconductor substrate respectively. Specifically, the step S900 comprises: S910: depositing the interlayer dielectric layer (ILD), depositing a silicon oxide layer with a thickness between 6000 angstroms and 10000 angstroms by a CVD process, and then using a 900-950℃ reflow densification treatment for 20-40 minutes to obtain the interlayer dielectric layer 9 with high density, see Figure 10 .

[0054] S920: removing about 2000 angstroms of the interlayer dielectric layer 9 by a chemical mechanical polishing (CMP) process to make the surface film layer of the ILD flat, and then using a self-aligned etching process to make the interlayer dielectric layer 9a remain only on the top of the polysilicon in the gate trench, and the surface of the interlayer dielectric layer 9a is flush with the surface of the semiconductor substrate, see Figure 11 .

[0055] S930: depositing the front metal layer, the front metal layer includes a source metal layer M and a gate metal layer, Figure 12 only the front source metal layer is shown. The source metal layer M is usually continuous, which can be a Ti / TiN / AlCu composite layer, and is electrically connected to all source regions 3 on the semiconductor substrate. The gate metal layer includes a plurality of gate metal units, each of which is electrically connected to the second polysilicon layer 71a in a gate trench through a gate contact hole.

[0056] Of course, the trench type silicon carbide MOSFET preparation method also includes conventional substrate thinning and back metal layer preparation steps. The back metal layer can be a Ti / Ni / Ag composite layer, and before the back metal layer is formed, a contact resistance improvement process can also be included, which is not described here.

[0057] The above preparation method is also applicable to the preparation of a p-type trench type silicon carbide MOSFET device.

[0058] The present application also provides a trench type silicon carbide MOSFET device, which is prepared by the above preparation method. Specifically, the trench type silicon carbide MOSFET device comprises: a semiconductor substrate 10; an epitaxial layer disposed on the semiconductor substrate, the epitaxial layer including a first epitaxial layer 121, a second epitaxial layer 122 and a third epitaxial layer 123, the doping concentration of the second epitaxial layer 122 being greater than that of the first epitaxial layer 121; a well region 2 and a source region 3 disposed in the epitaxial layer; Virtual trenches and gate trenches are arranged alternately in the source region; the virtual trenches extend from the source region 3 into the third epitaxial layer 123, and ion implantation regions 4 are provided on the sidewalls and bottom walls of the virtual trenches. The ion implantation regions 4 extend into the first epitaxial layer 121. The conductivity type of the ion implantation regions 4 is the same as that of the well region 2. A first insulating layer 5 and a first polysilicon layer 51 are provided in the virtual trenches; the gate trenches penetrate the well region 2, and a second insulating layer 7 and a second polysilicon layer 71 are provided in the gate trenches. Interlayer dielectric layer 9a and gate sidewall 8 are disposed on the upper part of the gate trench for isolation from source region 3; The front metal layer includes a source metal layer M and a gate metal layer. The source metal layer M connects all source regions 3. The gate metal layer includes multiple gate metal units, and each gate metal unit is connected to a second polysilicon layer 71 in a gate trench.

[0059] Of course, trench silicon carbide MOSFET devices also include a back metal layer disposed on the back side of the semiconductor substrate, which constitutes the drain electrode of the device.

[0060] Figure 13 This is a comparison of the output characteristic curves of a trench-type silicon carbide MOSFET device according to an embodiment of the present invention and a conventional trench-type silicon carbide MOSFET device. The gate voltage Vg is 18V in both cases. The horizontal axis (Vds / V) represents the drain-source voltage, indicating the voltage applied between the drain and source of the device; the vertical axis (Ids / A) represents the drain-source current, indicating the current between the drain and source. It can be seen that the slope of the output characteristic curve of the trench-type silicon carbide MOSFET device of the present invention in the linear region is significantly greater than that of the conventional trench-type silicon carbide MOSFET device in the linear region. This indicates that, under the same drain-source voltage, the device of the present invention can provide a larger current, meaning its on-resistance (Rdson) is significantly reduced by approximately 50% (reaching 20 mΩ), resulting in superior on-state performance.

[0061] Figure 14 This is a comparison of the breakdown voltage (BV) curves of a trench-type silicon carbide MOSFET device (dashed line) according to an embodiment of the present invention and a conventional trench-type silicon carbide MOSFET device (solid line). The horizontal axis (Vds / V) represents the drain-source voltage; the vertical axis (Ids / A, logarithmic scale) represents the drain-source current. The breakdown voltage (BV) curve shows the drain-source voltage (Vds) when the drain-source current (Ids) suddenly increases sharply. Combined with... Figure 13 and 14 As can be seen, compared with existing technology devices, the on-resistance Rdson of the trench silicon carbide MOSFET device of the present invention is significantly reduced by about 50%, while its breakdown voltage is only slightly reduced by 1.5% (about 23V).

[0062] In summary, in traditional devices, achieving high breakdown voltage requires a thin, lightly doped epitaxial layer, which directly leads to a sharp increase in resistance. This invention introduces a virtual trench structure as an indirect electric field shielding structure into a trench silicon carbide MOSFET device. Simultaneously, it employs a non-uniformly doped multilayer epitaxial structure (first, second, and third epitaxial layers) and precisely controls the three-dimensional electric field distribution within the device by implanting P-type ions of a specific shape around the virtual trench. Most importantly, by utilizing the high doping concentration of the second epitaxial layer, the lateral dimension of the P-type doping in the bottom region of the virtual trench (D) is reduced, effectively suppressing the JFET effect. This synergistic effect allows this invention to significantly reduce on-resistance with almost no sacrifice in breakdown voltage, breaking the inherent contradiction between on-resistance and breakdown voltage in existing trench silicon carbide MOSFETs.

[0063] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0064] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a trench-type silicon carbide MOSFET, characterized in that, The preparation method includes the following steps: A semiconductor substrate is provided, and an epitaxial layer is formed on the semiconductor substrate. The epitaxial layer includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the doping concentration of the second epitaxial layer is greater than the doping concentration of the first epitaxial layer. A well region and a source region are formed within the epitaxial layer; Etching forms virtual trenches that extend from the source region into the third epitaxial layer; Ion implantation and carbon film deposition are performed in the virtual trench. After annealing, an ion implantation region is formed. The ion implantation region extends to the first epitaxial layer. The conductivity type of the ion implantation region is the same as that of the well region. A virtual trench structure is formed by depositing a first insulating layer and a first polysilicon layer within the virtual trench. A hard mask layer is deposited, the hard mask layer is patterned, and a gate trench is obtained by etching. The gate trench is disposed between two virtual trench structures and extends through the well region. A second insulating layer is formed on the sidewall of the gate trench, and a second polysilicon layer is deposited in the gate trench to form a gate trench structure. Remove the hard mask layer, deposit a silicon nitride layer and etch the silicon nitride layer back onto it, and form a gate sidewall by extending the second polysilicon layer in the gate trench above the sidewall of the source region. A low-viscosity polymer layer or photoresist layer is formed between the gate trench structures, and a second polysilicon layer in the gate trench is etched until its top is below the upper surface of the source region; An interlayer dielectric layer and a front metal layer are formed on a semiconductor substrate, respectively.

2. The method for fabricating a trench-type silicon carbide MOSFET according to claim 1, characterized in that, The thickness of the second epitaxial layer is between 0.2 and 0.4 μm; and / or The thickness of the first epitaxial layer is between 2 and 100 μm; and / or The thickness of the third epitaxial layer is between 2 and 4 μm.

3. The method for fabricating a trench-type silicon carbide MOSFET according to claim 1, characterized in that, The doping concentration of the first epitaxial layer is 5×10 14 -5×10 16 cm -3 Between; and / or The doping concentration of the third epitaxial layer is 5 × 10⁻⁶. 14 -5×10 16 cm -3 between.

4. The method for fabricating a trench-type silicon carbide MOSFET according to claim 1, characterized in that, The doping concentration of the second epitaxial layer is 2-5 times that of the first epitaxial layer; and / or The doping concentration of the third epitaxial layer is the same as that of the first epitaxial layer.

5. The method for fabricating a trench-type silicon carbide MOSFET according to claim 1, characterized in that, The depth of the bottom of the virtual trench from the bottom of the third epitaxial layer is greater than 0.2 μm; or The depth of the bottom of the virtual trench from the bottom of the third epitaxial layer is between 0.3 and 0.5 μm.

6. The method for fabricating a trench-type silicon carbide MOSFET according to claim 1, characterized in that, The P-type doping concentration at the boundary between the well and source regions is 1×10⁻⁶. 17 -3×10 17 cm -3 between.

7. The method for fabricating a trench-type silicon carbide MOSFET according to claim 1, characterized in that, The ion implantation region extends to a depth greater than 0.1 μm into the first epitaxial layer; or The depth of the ion implantation region extending into the first epitaxial layer is between 0.15 and 0.25 μm.

8. The method for fabricating a trench-type silicon carbide MOSFET according to claim 1, characterized in that, The distance between the bottom of the gate trench and the bottom of the well region is greater than 0.3 μm; and / or The distance between the bottom of the gate trench and the bottom of the virtual trench is between 0.7 and 1.2 μm.

9. A trench-type silicon carbide MOSFET device, characterized in that, The device is fabricated using the trench-type silicon carbide MOSFET fabrication method described in any one of claims 1 to 8.

10. The trench-type silicon carbide MOSFET device according to claim 9, characterized in that, include: Semiconductor substrate; An epitaxial layer is disposed on the semiconductor substrate, the epitaxial layer comprising a first epitaxial layer, a second epitaxial layer and a third epitaxial layer, wherein the doping concentration of the second epitaxial layer is greater than the doping concentration of the first epitaxial layer; The well region and the source region are disposed within the epitaxial layer; Virtual trenches and gate trenches are alternately arranged within the source region; the virtual trenches extend from the source region into the third epitaxial layer, and ion implantation regions are provided on the sidewalls and bottom walls of the virtual trenches, extending into the first epitaxial layer. The conductivity type of the ion implantation regions is the same as that of the well region. A first insulating layer and a first polysilicon layer are provided within the virtual trenches; the gate trenches penetrate the well region, and a second insulating layer and a second polysilicon layer are provided within the gate trenches. An interlayer dielectric layer and a gate sidewall are disposed on the upper part of the gate trench for isolation from the source region; The front metal layer includes a source metal layer and a gate metal layer. The source metal layer connects all source regions, and the gate metal layer includes a plurality of gate metal units. Each gate metal unit is connected to a second polysilicon layer in each gate trench.

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