Preparation method of novel split-gate power MOSFET device and device

Abstract

According to the preparation method of the novel split-gate power MOSFET device and the device provided by the embodiment of the invention, a PN junction can be directly formed between an N-type epitaxial layer and the P-type second source polycrystalline silicon mainly by filling a cell region groove with the P-type second source polycrystalline silicon, the electric field intensity near the side wall is improved by the structure by utilizing the large-area PN junction, and the performance of the device is improved. The overall breakdown voltage of the device is improved; meanwhile, the concentration of the epitaxial layer is improved or the thickness of the epitaxial layer is reduced, so that the conduction impedance is reduced, the injection concentration of the second source polycrystalline silicon is adjusted through a process, so that a reverse biased PN junction electric field formed by the second source polycrystalline silicon and the epitaxial layer is adjusted, the device performance can be balanced and adjusted, and the conduction resistance can be optimized; the electric field of the device can reach a peak value, the waste of the depth of the groove is avoided, and the whole electric field distribution can reach a balanced state.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating a novel split-gate power MOSFET device and the device itself. Background Technology

[0002] In existing power MOSFET structures, optimizing the high electric field is necessary to improve the breakdown voltage of high-voltage devices during fabrication. Reducing the epitaxial layer density can increase the breakdown voltage, but it also increases the on-resistance. Therefore, optimizing the electric field near the trench in the cell region to improve the overall breakdown voltage and reduce the on-resistance is an urgent problem to be solved. Summary of the Invention

[0003] To address or mitigate the problems in the prior art, this application provides a novel method for fabricating a split-gate power MOSFET device and the device itself. By reducing the field strength at the bottom of the trench in the cell region of traditional devices, the overall breakdown voltage of the device is increased and the on-resistance is reduced.

[0004] In a first aspect, embodiments of this application provide a method for fabricating a novel split-gate power MOSFET device, comprising: Cell region trenches and terminal region trenches are etched on the epitaxial layer, wherein the doping type of the epitaxial layer is N-type. A first oxide layer is grown on the sidewalls of the cell trench and the terminal trench, and a first source polysilicon is filled in the cell trench and the terminal trench, wherein the doping type of the first source polysilicon is P-type. Only the first oxide layer and the first source polysilicon in the trench of the cell region are etched back; The second source polysilicon is filled into the cell region trench after the first oxide layer and the first source polysilicon have been removed; Only the second source polysilicon is etched back; Ion implantation is performed on the second source polysilicon to form a P-type second source polysilicon; A second oxide layer is grown on the sidewall of the trench in the cell region and above the second source polycrystalline silicon. The cell region trench is filled with gate polysilicon, and the gate polysilicon is N-type doped. A well region and an injection region are sequentially formed in the epitaxial layer between the trenches of the cell region; A first source contact hole is provided through the injection region, and a second source contact hole is formed in the first source polysilicon in the trench of the terminal region. The bottom of the first source contact hole extends into the well region.

[0005] In a preferred embodiment of this application, the trenches in the cell regions have the same depth.

[0006] As a preferred embodiment of this application, the step of ion implantation into the second source polycrystalline silicon includes: The second source polycrystalline silicon is annealed.

[0007] In a second aspect, embodiments of this application also provide a novel split-gate power MOSFET device, fabricated by the method described in any one of the first aspects, including a cell trench and a terminal trench; Both the cell region trench and the terminal region trench are disposed in the epitaxial layer, and the doping type of the epitaxial layer is N-type. The terminal region trench is filled with a first source polysilicon, and the cell region trench is provided with a gate polysilicon, a second oxide layer, a second source polysilicon and a first source polysilicon in sequence from top to bottom; A second oxide layer is disposed on the trench sidewall of the region where the gate polysilicon is located. A first oxide layer is provided on the trench sidewall of the region where the first source polysilicon is located, and the second source polysilicon is in direct contact with the trench sidewall of the cell region. A well region and an implantation region are sequentially arranged from bottom to top in the epitaxial layer between the trenches of the cell region; a first source contact hole is disposed through the implantation region, and a second source contact hole is disposed in the first source polysilicon in the trench of the terminal region, with the bottom of the first source contact hole extending into the well region.

[0008] In a preferred embodiment of this application, the doping concentration of the second source polysilicon is smaller than the doping concentration of the epitaxial layer.

[0009] In a preferred embodiment of this application, the top and bottom heights of the second source polysilicon in all cell regions are the same.

[0010] In a preferred embodiment of this application, the doping concentration of the second source polysilicon in all cell regions is also the same.

[0011] Compared with existing technologies, this application provides a novel method for fabricating a split-gate power MOSFET device and the device itself. It primarily involves filling the cell region trench with P-type second-source polysilicon, allowing a direct PN junction to be formed between the N-type epitaxial layer and the P-type second-source polysilicon. This structure utilizes a large-area PN junction to enhance the electric field strength near the sidewalls, thereby increasing the overall breakdown voltage of the device. Simultaneously, it increases the concentration of the epitaxial layer or decreases its thickness, thereby reducing the on-resistance. By adjusting the implantation concentration of the second-source polysilicon through the process, the electric field of the reverse-biased PN junction formed by the second-source polysilicon and the epitaxial layer can be adjusted, balancing device performance and optimizing on-resistance. This ensures the device's electric field reaches its peak value, avoids wasting trench depth, and achieves a balanced electric field distribution. Attached Figure Description

[0012] Non-limiting and non-exhaustive embodiments of the invention are described by way of example with reference to the following figures, wherein: Figure 1 This paper illustrates a flowchart of a method for fabricating a novel split-gate power MOSFET device according to an embodiment of this application. Figures 2 to 9 for Figure 1 The flowchart in the document contains a structural diagram of each step. Detailed Implementation

[0013] To make the above and other features and advantages of the present invention clearer, the invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explanation to those skilled in the art and are exemplary only, not restrictive.

[0014] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] In a first aspect, embodiments of this application provide a method for fabricating a novel split-gate power MOSFET device, comprising: Step S101: Cell region trench 102 and terminal region trench 103 are etched on epitaxial layer 101, wherein the doping type of epitaxial layer is N-type. refer to Figure 1 and Figure 2Trenches are formed on the epitaxial layer 101 by etching using semiconductor etching processes. The specific etching process and the placement of a mask layer on the upper surface of the epitaxial layer before etching are conventional techniques known to those skilled in the art and will not be elaborated upon here. In the embodiments of this application, the trenches in the cell regions have the same depth.

[0017] Step S102: A first oxide layer 104 is grown on the sidewalls of the cell trench 102 and the terminal trench 103, and a first source polysilicon 105 is filled in the cell trench 102 and the terminal trench 103, wherein the doping type of the first source polysilicon 105 is N-type. refer to Figure 1 and Figure 3 Growing the first oxide layer 104 in the cell region trench 102 and the terminal region trench 103 is a conventional technique for those skilled in the art in the semiconductor field, and will not be elaborated here. The first oxide layer 104 mainly serves an insulating function. Filling the first source polysilicon 105 is mainly for the formation of source polysilicon. The doping concentration of the first source polysilicon 105 in this step is fixed and cannot be adjusted by the process. The specific filling process is a conventional technique for those skilled in the art.

[0018] Step S103: Only the first oxide layer 104 and the first source polysilicon 105 in the cell trench 102 are etched back; refer to Figure 1 and Figure 4 This step selectively etches the first oxide layer 104 in the cell trench first, followed by etching the first source polysilicon 105 in the cell trench 102. The first oxide layer 104 and the first source polysilicon 105 in the terminal trench 103 are left unetched, as the terminal trench 103 is the terminal region and essentially the stop ring of the entire device. The specific process for selectively etching the first oxide layer 104 and the first source polysilicon 105 is a conventional technique for those skilled in the art and will not be elaborated here. After etching back the first oxide layer 104 and the first source polysilicon 105 in the cell trench 102, the height of the first oxide layer 104 and the first source polysilicon 105 is less than the height of the entire cell trench.

[0019] Step S104: Fill the cell trench 102 where the first oxide layer 104 and the first source polysilicon 105 have been removed with a second source polysilicon 106. refer to Figure 1 and Figure 5As shown, the second source polysilicon 106 is further filled into the cell region trench 102 after the first oxide layer 104 and the first source polysilicon 105 have been etched away. Because the trench sidewalls in the region where the second source polysilicon 106 is located do not have the first oxide layer 104, the second source polysilicon 106 is in direct contact with the sidewalls of the cell region trench 102. The process of filling the second source polysilicon 106 is a conventional technique for those skilled in the art and will not be described in detail here.

[0020] Step S105: Only the second source polysilicon 106 is etched back; refer to Figure 1 and Figure 6 As shown, the second source polysilicon 106 filled in the cell trench 102 is etched until the remaining portion of the second source polysilicon 106 in the cell trench 102 is etched. The second source polysilicon 106 filled in this step is undoped. Furthermore, the height of the last remaining second source polysilicon 106 in each cell trench 102 is the same.

[0021] Step S106: Ion implantation is performed on the second source polysilicon 106 to form a P-type second source polysilicon 106. Ion implantation is performed on the second source polysilicon 106. In this embodiment, boron ions are implanted to obtain a P-type second source polysilicon 106. Since the second source polysilicon 106 is in direct contact with the sidewall of the trench 102 in the cell region, it is also equivalent to contact with the epitaxial layer 101. Because the epitaxial layer in this embodiment is N-type, the epitaxial layer 101 and the second source polysilicon 106 form a PN junction. This structure uses a large-area PN junction to increase the electric field strength near the sidewall, thereby increasing the overall breakdown voltage of the device. At the same time, the concentration of the epitaxial layer 101 is increased or the thickness of the epitaxial layer is decreased, thereby reducing the on-resistance. By adjusting the implantation concentration of the second source polysilicon 106 through the process, the electric field of the reverse bias PN junction formed by the second source polysilicon 106 and the epitaxial layer 101 can be adjusted to balance the device performance and optimize the specific on-resistance. This allows the electric field of the device to reach the entire peak value, avoids the waste of trench depth, and allows the entire electric field distribution to reach a balanced state.

[0022] After ion implantation of the second source polycrystalline silicon 106, the process includes: The second source polysilicon 106 is annealed. Annealing allows for greater ion diffusion depth and more uniform diffusion in the ion-implanted polysilicon 106.

[0023] Step S107: A second oxide layer 107 is grown on the sidewall of the cell trench 102 and above the second source polysilicon 106. refer to Figure 1 and Figure 7 This step is mainly to prepare for the formation of the gate polysilicon 108. It is necessary to first grow a second oxide layer 107 on the sidewall of the trench 102 in the cell region. The second oxide layer 107 is the gate oxide. At the same time, a second oxide layer 107 is formed on the upper surface of the second source polysilicon 106 to isolate the second source polysilicon 106 from the gate polysilicon 108.

[0024] Step S108: Fill the cell trench 102 with gate polysilicon 108, wherein the gate polysilicon 108 is N-type doped. refer to Figure 1 and Figure 8 A gate polysilicon 108 is filled above the second source polysilicon 106 to form a gate, and the gate polysilicon 108 is N-type doped.

[0025] Step S109: A well region 111 and an injection region 112 are sequentially formed in the epitaxial layer 101 between the cell trenches 102; In step S110, a first source contact hole 110 is provided through the injection region 112, and a second source contact hole 109 is formed in the first source polysilicon 105 in the terminal region trench 103, with the bottom of the first source contact hole 105 extending into the well region 111.

[0026] refer to Figure 1 and Figure 9 Steps S109 and S110 are mainly for forming the source extraction region.

[0027] Secondly, such as Figure 9 As shown, this application embodiment also provides a novel split-gate power MOSFET device, which is fabricated by the method described in any one of the first aspects, including a cell trench 102 and a terminal trench 103; The cell region trench 102 and the terminal region trench 103 are both disposed in the epitaxial layer 101, and the doping type of the epitaxial layer 101 is N-type. The terminal region trench 103 is filled with a first source polysilicon 105, and the cell region trench 102 is provided with a gate polysilicon 108, a second oxide layer 107, a second source polysilicon 106 and a first source polysilicon 105 from top to bottom. A second oxide layer 107 is disposed on the trench sidewall of the region where the gate polysilicon 108 is located. A first oxide layer 104 is provided on the trench sidewall of the region where the first source polysilicon 105 is located, and the second source polysilicon 106 is in direct contact with the sidewall of the cell region trench 102. A well region 111 and an implantation region 112 are sequentially disposed from bottom to top in the epitaxial layer 101 between the cell trenches 102; a first source contact hole 109 is disposed through the implantation region 112, and a second source contact hole 110 is disposed in the first source polysilicon 105 in the terminal trench 103, with the bottom of the first source contact hole 109 extending into the well region 111.

[0028] In a preferred embodiment of this application, the doping concentration of the second source polysilicon 106 is smaller than the doping concentration of the epitaxial layer 101.

[0029] In a preferred embodiment of this application, the top and bottom heights of the P-type second source polysilicon 106 in all cell regions are the same.

[0030] In a preferred embodiment of this application, the doping concentration of the P-type second source polysilicon 106 in all cell regions is also the same.

[0031] In this embodiment, the depth and doping concentration of the P-type second source polysilicon 106 in all cell regions are set to be the same, mainly to make all P-type second source polysilicon 106 and epitaxial layer 101 form the same PN junction size, which helps to reduce the breakdown voltage of the entire device.

[0032] The technical features of the above implementation schemes can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above implementation schemes are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0033] Although the invention has been described in conjunction with embodiments, those skilled in the art will understand that the above description and drawings are exemplary and not restrictive, and the invention is not limited to the disclosed embodiments. Various modifications and variations are possible without departing from the spirit of the invention.

Claims

1. A method for fabricating a novel split-gate power MOSFET device, characterized in that, include: Cell region trenches and terminal region trenches are etched on the epitaxial layer, wherein the doping type of the epitaxial layer is N-type. A first oxide layer is grown on the sidewalls of the cell trench and the terminal trench, and a first source polysilicon is filled in the cell trench and the terminal trench, wherein the doping type of the first source polysilicon is P-type. Only the first oxide layer and the first source polysilicon in the trench of the cell region are etched back; The second source polysilicon is filled into the cell region trench after the first oxide layer and the first source polysilicon have been removed; Only the second source polysilicon is etched back; Ion implantation is performed on the second source polysilicon to form a P-type second source polysilicon; A second oxide layer is grown on the sidewall of the trench in the cell region and above the second source polycrystalline silicon. The cell region trench is filled with gate polysilicon, and the gate polysilicon is N-type doped. A well region and an injection region are sequentially formed in the epitaxial layer between the trenches of the cell region; A first source contact hole is provided through the injection region, and a second source contact hole is formed in the first source polysilicon in the trench of the terminal region. The bottom of the first source contact hole extends into the well region.

2. The method for fabricating a novel split-gate power MOSFET device as described in claim 1, characterized in that, The trenches in the cell regions have the same depth.

3. The method for fabricating a novel split-gate power MOSFET device as described in claim 1, characterized in that, The process after ion implantation in the second source polycrystalline silicon includes: The second source polycrystalline silicon is annealed.

4. A novel split-gate power MOSFET device, characterized in that, Prepared by the method according to any one of claims 1 to 3, comprising cellular trenches and terminal trenches; Both the cell region trench and the terminal region trench are disposed in the epitaxial layer, and the doping type of the epitaxial layer is N-type. The terminal region trench is filled with a first source polysilicon, and the cell region trench is provided with a gate polysilicon, a second oxide layer, a second source polysilicon and a first source polysilicon in sequence from top to bottom; A second oxide layer is disposed on the trench sidewall of the region where the gate polysilicon is located. A first oxide layer is provided on the trench sidewall of the region where the first source polysilicon is located, and the second source polysilicon is in direct contact with the trench sidewall of the cell region. A well region and an implantation region are sequentially arranged from bottom to top in the epitaxial layer between the trenches of the cell region; a first source contact hole is disposed through the implantation region, and a second source contact hole is disposed in the first source polysilicon in the trench of the terminal region, with the bottom of the first source contact hole extending into the well region.

5. A novel split-gate power MOSFET device as described in claim 4, characterized in that, The doping concentration of the second source polysilicon is lower than that of the epitaxial layer.

6. The method for fabricating a novel split-gate power MOSFET device as described in claim 4, characterized in that, The top and bottom heights of the second source polysilicon in all cell regions are the same.

7. The method for fabricating a novel split-gate power MOSFET device as described in claim 6, characterized in that, The doping concentration of the second source pole polysilicon in all cell regions is also the same.

Images