Semiconductor device with multi-channel structure

Abstract

The utility model belongs to the technical field of semiconductor devices, and discloses a semiconductor device with a multi-channel structure, which comprises a substrate, a buffer layer, a channel layer, a barrier layer and the multi-channel structure, the buffer layer, the channel layers and the barrier layers are sequentially arranged on one side of the substrate in the first direction, the multiple barrier layers and the multiple channel layers are arranged, and the multiple barrier layers and the multiple channel layers are arranged in a staggered mode in the first direction; the first direction is perpendicular to the plane where the substrate is located and points to the barrier layer from the substrate; the multi-channel structure comprises a plurality of 2DEG channels arranged along a first direction, the plurality of 2DEG channels are arranged side by side along a second direction, and the plurality of 2DEG channels are used for each barrier layer to convey electrons; the second direction is perpendicular to the plane where the substrate is located and points to the other opposite end from one end of the substrate. According to the invention, large current can be obtained, the problem of large current concentration can be effectively relieved, and the semiconductor device is prevented from being burnt and failed due to overlarge current.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a semiconductor device with a multi-channel structure. Background Art

[0002] Gallium nitride (GaN) material, as the third generation wide bandgap semiconductor material, has the advantages of high breakdown electric field strength, small dielectric constant, high electron mobility, high saturated electron drift rate, large thermal conductivity, and strong radiation resistance, and has become a hot topic in the field of semiconductor research in recent years. Gallium nitride high electron mobility transistor (GaN HEMT) has significant advantages in power electronics and radio frequency due to its large bandgap width, high saturation velocity and large current density. In order to meet the current high-power application needs, a larger current capacity is usually required.

[0003] In related technical means, in order to obtain a larger current, it can generally be achieved by increasing the gate width of the device or by adding multiple two-dimensional electron gas (2DEG) channels in the vertical direction of the device. Increasing the gate width of the device will increase the size of the device, thereby increasing the production cost of the device and bringing more reliability issues; by adding multiple two-dimensional electron gas (2DEG) channels in the vertical direction of the device, it is possible to improve the current capability of the device without increasing the gate width of the device. There are currently two main ohmic contact schemes for multi-channel devices: 1. Directly depositing metal on the top barrier layer and then annealing to form an ohmic contact; 2. Partially etching the barrier layer and the channel layer, and then depositing metal to achieve ohmic contact, such as Figure 1 The multi-channel devices of the above two ohmic contact schemes may cause current concentration problems, which may seriously lead to device burnout and failure.

[0004] With regard to the above-mentioned technical means, there is a problem of current concentration when multi-channel devices meet the application requirements of large currents, which may seriously lead to the defect of burning out and failing of the device. Utility Model Content

[0005] The embodiments of the present application provide a semiconductor device with a multi-channel structure, which can obtain large current and effectively alleviate the problem of large current concentration, thereby preventing the semiconductor device from burning out and failing due to excessive current.

[0006] A multi-channel semiconductor device provided in the present application adopts the following technical solution:

[0007] A semiconductor device with a multi-channel structure, comprising a substrate, a buffer layer, a channel layer, a barrier layer and a multi-channel structure;

[0008] The buffer layer, the channel layer and the barrier layer are sequentially arranged on one side of the substrate along a first direction, the barrier layer and the channel layer are both provided with multiple layers, and the multiple layers of the barrier layer and the channel layer are staggered along the first direction; the first direction is perpendicular to the plane where the substrate is located, and points from the substrate to the barrier layer;

[0009] The multi-channel structure includes a plurality of 2DEG channels arranged along a first direction, the plurality of 2DEG channels are arranged side by side along a second direction, and the plurality of 2DEG channels are used to transport electrons in each barrier layer; the second direction is perpendicular to the plane where the substrate is located, and points from one end of the substrate to the other opposite end.

[0010] Optionally, the 2DEG channel is formed by etching the barrier layer or the barrier layer and the channel layer, and a plurality of the 2DEG channels are arranged in a stepped manner along the second direction according to the etching depth.

[0011] Optionally, the etching angles of the plurality of 2DEG channels are different.

[0012] Optionally, the etching angles of the plurality of 2DEG channels are the same, and the etching angles of the plurality of 2DEG channels are close to a right angle to ensure the directionality of the current.

[0013] Optionally, the material, composition and thickness of the barrier layer corresponding to each of the 2DEG channels are the same or different, and the material used for the barrier layer is one of AlxGa1-xN, InxAl1-xN and AlxInyGa1-x-yN (0≤x / y≤1).

[0014] Optionally, it also includes source metal, drain metal and gate metal, the outermost surface of the barrier layer along the first direction has a passivation layer, both ends of the passivation layer are in contact with the source metal and the drain metal, and the gate metal is arranged on the upper surface of the passivation layer.

[0015] Optionally, the multi-channel structure is provided with two groups of source metals and drain metals corresponding one to one, the 2DEG channel is provided with a doped region, the source metal and the drain metal are deposited to fill the doped region, and an ohmic contact is formed by high temperature annealing.

[0016] Optionally, the doped region is filled with heavily doped n-type GaN.

[0017] Optionally, the doping region includes a first doping region and a second doping region, the first doping region and the second doping region are arranged in sequence along the second direction, the first doping region is filled with the corresponding drain metal or the source metal, and the second doping region is filled with a medium.

[0018] Optionally, the first doped region is filled with heavily doped n-type GaN, and the second doped region is filled with a dielectric.

[0019] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0020] Multiple 2DEG channels are set up to transport electrons to control the flow of current. The electrons are restricted to move in the 2DEG channels and will not produce a drift effect, thereby not affecting the gate width of the device. The electrons are diverted through multiple 2DEG channels, and each 2DEG channel is responsible for part of the electron transport. On the one hand, the total current of the device is increased to enhance the current capacity of the device and meet the needs of large current applications; on the other hand, the electrons are dispersed into multiple 2DEG channels for transport, which can disperse the current and reduce the degree of current concentration in the device, thereby avoiding the burning and failure of the semiconductor device due to excessive current. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of an ohmic contact solution for a multi-channel device disclosed in the prior art;

[0022] Figure 2 A cross-sectional view of a semiconductor device embodiment 1 having a multi-channel structure disclosed in an embodiment of the present application;

[0023] Figure 3 A schematic diagram showing a multi-channel structure in Embodiment 1 of a semiconductor device with a multi-channel structure disclosed in an embodiment of the present application;

[0024] Figure 4 A cross-sectional view of a semiconductor device embodiment 2 having a multi-channel structure disclosed in an embodiment of the present application;

[0025] Figure 5a A cross-sectional view of a semiconductor device embodiment 3 having a multi-channel structure disclosed in an embodiment of the present application;

[0026] Figure 5b A top view of a semiconductor device embodiment 3 with a multi-channel structure disclosed in an embodiment of the present application;

[0027] Figure 6 It is a cross-sectional view of a semiconductor device embodiment 4 with a multi-channel structure disclosed in the embodiments of the present application.

[0028] Description of reference numerals:

[0029] 1. Substrate; 2. Buffer layer; 3. Channel layer; 4. Barrier layer; 5. 2DEG channel; 51. Doping region; 511. First doping region; 512. Second doping region; 6. Source metal; 7. Drain metal; 8. Gate metal. DETAILED DESCRIPTION

[0030] The present application is further described in detail below in conjunction with the accompanying drawings.

[0031] The embodiments of the present application provide a semiconductor device with a multi-channel structure, which can obtain large current and effectively alleviate the problem of large current concentration, thereby preventing the semiconductor device from burning out and failing due to excessive current.

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] The terms "first", "second", "third", "fourth", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] For ease of understanding, the semiconductor device with a multi-channel structure in the embodiment of the present application is described below. Figure 2 , an embodiment of a semiconductor device with a multi-channel structure in an embodiment of the present application comprises: a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4 and a multi-channel structure, wherein the buffer layer 2, the channel layer 3 and the barrier layer 4 are sequentially arranged on one side of the substrate 1 along a first direction, the barrier layer 4 and the channel layer 3 are both provided with multiple layers, and the multiple barrier layers 4 and the channel layer 3 are staggered along the first direction; in this embodiment, the first direction is perpendicular to the plane where the substrate 1 is located, and points from the substrate 1 to the barrier layer 4, that is, the substrate 1 is located at the bottom layer, the buffer layer 2 is located on the upper surface of the substrate 1, and the barrier layer 4 is located on the upper surface of the channel layer 3. The outermost barrier layer 4 along the first direction has a passivation layer on its surface, the two ends of the passivation layer are in contact with the source metal 6 and the drain metal 7, and the gate metal 8 is arranged on the upper surface of the passivation layer. The material used for the substrate 1 is one of silicon, silicon carbide and sapphire; the material used for the passivation layer is one of aluminum oxide, hafnium oxide, silicon nitride and silicon dioxide.

[0035] See also Figure 2 and Figure 3 , the multi-channel structure is provided with two groups of source metal 6 and drain metal 7 corresponding to each other, and the multi-channel structure is connected to the source metal 6 or the drain metal 7, which is used to meet the high current application requirements of the device while alleviating the problem of current concentration. The multi-channel structure includes a plurality of 2DEG channels 5 arranged along a first direction, and a plurality of 2DEG channels 5 are arranged side by side along a second direction, and a plurality of 2DEG channels 5 are used to transport electrons in each barrier layer 4; the second direction is perpendicular to the plane where the substrate 1 is located, and points from one end of the substrate 1 to the other opposite end. In this embodiment, the number of 2DEG channels 5 in the multi-channel structure is at least two. The electrons are restricted to move within the 2DEG channel 5, and no drift effect occurs, thus not affecting the gate width of the device. A plurality of 2DEG channels 5 are provided to transport electrons to control the flow of current, and the electrons are diverted through the plurality of 2DEG channels 5. Each 2DEG channel 5 undertakes part of the electron transport, which, on the one hand, increases the total current of the device to enhance the current capability of the device and meet the requirements of high current applications; on the other hand, dispersing the electrons into a plurality of 2DEG channels 5 for transport can disperse the current and reduce the degree of current concentration in the device, thereby preventing the semiconductor device from burning out and failing due to excessive current.

[0036] See also Figure 3 , the 2DEG channel 5 is formed by etching the barrier layer 4 or the barrier layer 4 and the channel layer 3. The material, composition and thickness of the barrier layer 4 corresponding to each 2DEG channel 5 may be the same or different. The material used for the barrier layer 4 is one of AlxGa1-xN, InxAl1-xN and AlxInyGa1-x-yN (0≤x / y≤1). In this embodiment, a multi-channel structure formed by three 2DEG channels 5 is used as an example for explanation. Each 2DEG channel 5 sequentially connects to different layers of barrier layers 4 for the transmission of electrons in the corresponding barrier layer 4. The three 2DEG channels 5 are arranged adjacent to each other, and the ends of the three 2DEG channels 5 away from the substrate 1 are connected to the drain metal 7 or the source metal 6.

[0037] Multiple 2DEG channels 5 are arranged in a stepped manner along the second direction according to the etching depth, and different etching depths are used to connect different layers of barrier layers 4. Since the density of electron gas may be different at different positions, the use of a stepped multi-channel structure can further optimize the transmission of electrons and further reduce the degree of current concentration.

[0038] In some embodiments, the etching angles of the plurality of 2DEG channels 5 are all different. In some other embodiments, the etching angles of two or more of the plurality of 2DEG channels 5 are the same, and the etching angles of the remaining 2DEG channels 5 are different.

[0039] In this embodiment, the etching angles of the plurality of 2DEG channels 5 are the same, and the etching angles of the plurality of 2DEG channels 5 are close to a right angle to ensure the directionality of the current. During the etching process, selecting an etching angle close to a right angle can ensure the directionality of the channel, so that the current can only flow in one direction in the channel, and can avoid unnecessary leakage or charge accumulation, thereby improving the working efficiency of the transistor.

[0040] The 2DEG channel 5 is provided with a doped region 51, and the source metal 6 and the drain metal 7 are deposited to fill the doped region 51 and form an ohmic contact through high temperature annealing. After the etching of the multiple 2DEG channels 5 is completed, a layer of metal material is deposited to fill the doped region 51 to enhance the current transmission capability between the source and drain and the semiconductor. The high temperature annealing can promote the diffusion between the metal and the semiconductor material, so that the metal and the semiconductor form a good contact and reduce the contact resistance.

[0041] See also Figure 4 In other embodiments, the doping region 51 is filled with heavily doped n-type GaN. In the above embodiment, the source metal 6 and the drain metal 7 deposited in the doping region 51 are replaced with n-type GaN. The heavily doped n-type GaN will affect the contact resistance. The heavily doped n-type GaN has higher conductivity and can provide better electron injection performance, thereby reducing the ohmic contact resistance and achieving surface flatness of the doping region 51.

[0042] See also Figure 5a and Figure 5b In some other embodiments, the doping region 51 includes a first doping region 511 and a second doping region 512, the first doping region 511 and the second doping region 512 are sequentially arranged along the second direction, the first doping region 511 is filled with the corresponding drain metal 7 or source metal 6, and the second doping region 512 is filled with a dielectric. The multiple 2DEG channels 5 are stepped along the second direction so that the multiple first doping regions 511 are separated by the second doping region 512, that is, the metals are isolated by the dielectric. By adding dielectric isolation between the ohmic contact metals, the metal area of ​​the source and drain can be reduced, the capacitance value can be reduced, and the operation speed and performance of the device can be improved.

[0043] See also Figure 6 In some other embodiments, the first doping region 511 is filled with heavily doped n-type GaN, and the second doping region 512 is filled with a dielectric. That is, based on the technology of the above embodiment, the source metal 6 and the drain metal 7 deposited in the first doping region 511 are replaced with n-type GaN, and the filling of the second doping region 512 remains unchanged.

[0044] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device with a multi-channel structure, characterized in that: include: Substrate (1), buffer layer (2), channel layer (3), barrier layer (4) and multi-channel structure; The buffer layer (2), the channel layer (3) and the barrier layer (4) are sequentially arranged on one side of the substrate (1) along a first direction; the barrier layer (4) and the channel layer (3) are both provided with multiple layers, and the multiple layers of the barrier layer (4) and the channel layer (3) are staggered along the first direction; the first direction is perpendicular to the plane where the substrate (1) is located, and points from the substrate (1) to the barrier layer (4); The multi-channel structure comprises a plurality of 2DEG channels (5) arranged along a first direction, the plurality of 2DEG channels (5) being arranged side by side along a second direction, the plurality of 2DEG channels (5) being used for transporting electrons to each barrier layer (4); the second direction is perpendicular to the plane where the substrate (1) is located, and points from one end of the substrate (1) to the other opposite end.

2. A multi-channel semiconductor device according to claim 1, characterized in that: The 2DEG channel (5) is formed by etching the barrier layer (4) or the barrier layer (4) and the channel layer (3), and a plurality of the 2DEG channels (5) are arranged in a step-like manner along the second direction according to the etching depth.

3. A multi-channel semiconductor device according to claim 2, characterized in that: The etching angles of the plurality of 2DEG channels (5) are all different.

4. The semiconductor device with a multi-channel structure according to claim 2, characterized in that: The etching angles of the plurality of 2DEG channels (5) are all the same, and the etching angles of the plurality of 2DEG channels (5) are all close to a right angle to ensure the directionality of the current.

5. The semiconductor device with a multi-channel structure according to claim 2, characterized in that: The barrier layer (4) corresponding to each of the 2DEG channels (5) has the same or different materials, components and thicknesses, and the material used in the barrier layer (4) is one of AlxGa1-xN, InxAl1-xN and AlxInyGa1-x-yN (0≤x / y≤1).

6. The semiconductor device with a multi-channel structure according to claim 1, characterized in that: It also includes a source metal (6), a drain metal (7) and a gate metal (8); the outermost surface of the barrier layer (4) along the first direction has a passivation layer, both ends of the passivation layer are in contact with the source metal (6) and the drain metal (7), and the gate metal (8) is arranged on the upper surface of the passivation layer.

7. The semiconductor device with a multi-channel structure according to claim 6, characterized in that: The multi-channel structure is provided with two groups of source metals (6) and drain metals (7) which are arranged in one-to-one correspondence, the 2DEG channel (5) is provided with a doping region (51), the source metal (6) and the drain metal (7) are deposited to fill the doping region (51), and an ohmic contact is formed by high-temperature annealing.

8. The semiconductor device with a multi-channel structure according to claim 7, characterized in that: The doping region (51) is filled with heavily doped n-type GaN.

9. The semiconductor device with a multi-channel structure according to claim 7, characterized in that: The doping region (51) comprises a first doping region (511) and a second doping region (512), the first doping region (511) and the second doping region (512) being arranged in sequence along a second direction, the first doping region (511) being filled with the corresponding drain metal (7) or the source metal (6), and the second doping region (512) being filled with a medium.

10. The semiconductor device with a multi-channel structure according to claim 9, characterized in that: The first doping region (511) is filled with heavily doped n-type GaN, and the second doping region (512) is filled with a medium.

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