Low-on-resistance high-voltage SOI LDMOS power device and preparation method thereof

Abstract

The invention discloses a low-on-resistance high-voltage SOI LDMOS power device and a preparation method thereof.The power device comprises a P-type substrate, a BOX layer, a P-Window buried layer, a first N-type drift region, a second N-type drift region, a first P-pillar buried layer and a second P-pillar buried layer, the P-Window buried layer and the BOX layer are arranged on the upper surface of the P-type substrate in the left-right direction, and the first N-type drift region and the second N-type drift region are arranged on the lower surface of the P-type substrate in the left-right direction. The N-type drift region I and the N-type drift region II are respectively overlapped above the P-Window buried layer and the BOX layer, an oxidation tank is arranged on the left side of the N-type drift region I, polycrystalline silicon grows in the oxidation tank, the P-pillar buried layer I and the P-pillar buried layer II are arranged along the vertical direction and extend rightwards from the left side surface of the N-type drift region I into the N-type drift region II, and the P-pillar buried layer II and the P-pillar buried layer II are arranged along the vertical direction. The length of the first P-pillar buried layer is larger than that of the second P-pillar buried layer, and the doping concentration of the first N-type drift region and the doping concentration of the second N-type drift region are different. According to the device structure, the on resistance is effectively reduced, the breakdown voltage is improved, and the performance of the device is well improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a low on-resistance high-voltage SOI LDMOS power device and a preparation method thereof. Background Art

[0002] SOI (Silicon on Insulator) refers to silicon on insulator technology. SOI process technology is a full dielectric isolation technology. LDMOS has the advantages of good compatibility with CMOS process, good frequency characteristics, low noise and fast switching speed, but there is a 2.5-power opposite relationship between its breakdown voltage and specific on-resistance.

[0003] How to alleviate the contradiction between the breakdown voltage and the specific on-resistance of LDMOS is something that those skilled in the art are committed to solving. Summary of the invention

[0004] The object of the present invention is to provide a low on-resistance high-voltage SOI LDMOS power device for alleviating the conflicting relationship between specific on-resistance and breakdown voltage.

[0005] To achieve this purpose, the present invention adopts the following technical scheme: a low on-resistance high-voltage SOI LDMOS power device, comprising a P-type substrate, a BOX layer, a P-Window buried layer, an N-type drift region 1, an N-type drift region 2, a P-pillar buried layer 1 and a P-pillar buried layer 2, wherein the P-Window buried layer and the BOX layer are arranged on the upper surface of the P-type substrate along the left-right direction, the N-type drift region 1 and the N-type drift region 2 are respectively stacked on the P-Window buried layer and the BOX layer, an oxidation groove is arranged on the left side of the N-type drift region 1, polysilicon is grown in the oxidation groove, the P-pillar buried layer 1 and the P-pillar buried layer 2 are arranged along the up-down direction and both extend from the left side of the N-type drift region 1 to the right into the N-type drift region 2, the length of the P-pillar buried layer 1 is longer than the length of the P-pillar buried layer 2, and the doping concentrations of the N-type drift region 1 and the N-type drift region 2 are different.

[0006] As a specific implementation, the element doped in the N-type drift region 1 and the N-type drift region 2 is phosphorus, wherein the doping concentration of the N-type drift region 1 is 3×10 15 cm -3 ; The doping concentration of the N-type drift region 2 is 4.6×10 15 cm -3 .

[0007] As a specific implementation method, the element doped in the P-pillar buried layer 1 and the P-pillar buried layer 2 is boron, and the doping concentration of the P-pillar buried layer 1 is 5×10 16 cm -3 , length is 13-15μm; the doping concentration of the P-pillar buried layer II is 3.5×10 16 cm -3 , length is 9-11μm.

[0008] As a specific implementation manner, the thickness of the BOX layer and the P-Window buried layer is 1±0.05 μm.

[0009] As a specific implementation manner, the thickness of the N-type drift region 1 and the N-type drift region 2 is 4±0.2 μm.

[0010] Another object of the present invention is to provide a method for preparing a low on-resistance high-voltage SOI LDMOS power device, which is used to prepare the low on-resistance high-voltage SOI LDMOS power device, comprising the following steps: 1) A P-type substrate with a P-Window buried layer and a BOX layer is prepared, and an N-type drift region 1 and an N-type drift region 2 are epitaxially grown on the P-Window buried layer and the BOX layer, respectively, and the P-Window buried layer is located on the left side of the BOX layer; 2) Boron ions are implanted into the N-type drift region 1 and the N-type drift region 2 to form a P-pillar buried layer 2; 3) Boron ions are implanted again at a distance of 2~3μm above the P-pillar buried layer 2 to form the P-pillar buried layer 1; 4) Etching the left side of the N-type drift region 1 to form an oxide groove, and forming a source P+ region, a source N+ region, a P-body region, and a drain N+ region on the upper surfaces of the N-type drift region 1 and the N-type drift region 2 by ion implantation and heating diffusion; 5) Grow polysilicon in the oxidation groove to form a trench gate; 6) The gate, source and drain of the device are formed on the top of the N-type drift region 1 and the N-type drift region 2 by dry etching and metal deposition.

[0011] As a specific implementation, the oxidation groove has a thickness of 5±0.5 μm and a width of 0.5±0.05 μm.

[0012] Compared with the prior art, the technical solution of the present invention has the following advantages: 1) In the present invention, two P-pillar buried layers with different doping concentrations and lengths are arranged in the N-type drift region. The ends of the two P-pillar buried layers will generate high electric fields, which can better modulate the body electric field of the device. The length of the P-pillar buried layer 1 is longer because the P-pillar buried layer 1 can introduce the surface high electric field near the drain into the body of the device, thereby avoiding the problem of premature breakdown caused by excessive concentration of the drain electric field; 2) Compared with the conventional SOILDMOS structure with uniform doping distribution, the present invention adopts two N-type drift regions with different doping concentrations, and the doping concentration of the drift region in the PL-SOILDMOS can be relatively large. The increase in the drift region concentration can improve the current capability of the PL-SOILDMOS structure, thereby reducing Ronp; 3) The PL-SOIL DMOS structure of the present invention can avoid the electric field concentration between the drift region and the P-body region when a planar gate electrode is used by using a trench gate electrode, thereby improving the insulation breakdown voltage of the PL-SOIL DMOS structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural schematic diagram of the low on-resistance high-voltage SOI LDMOS power device according to the present invention; Figure 2 A flow chart for preparing a low on-resistance high-voltage SOI LDMOS power device according to the present invention; Among them: 1. P-type substrate; 2. P-Window buried layer; 3. BOX layer; 4. N-type drift region 1; 5. N-type drift region 2; 6. P-pillar buried layer 2; 7. P-pillar buried layer 1; 8. Oxidation groove; 9. Source N+ region; 10. Source P+ region; 11. P-body region; 12. Drain N+ region. DETAILED DESCRIPTION

[0014] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific embodiments.

[0015] A low on-resistance high voltage SOI LDMOS power device, see Figure 1As shown, it includes a P-type substrate 1, a BOX layer 3, a P-Window buried layer 2, an N-type drift region 14, an N-type drift region 25, a P-pillar buried layer 17 and a P-pillar buried layer 26, wherein the P-Window buried layer 2 and the BOX layer 3 are arranged on the upper surface of the P-type substrate 1 along the left-right direction, the N-type drift region 14 and the N-type drift region 25 are respectively stacked on the P-Window buried layer 2 and the BOX layer 3, an oxidation groove 8 is arranged on the left side of the N-type drift region 14, and polycrystalline silicon is grown in the oxidation groove 8, the P-pillar buried layer 17 and the P-pillar buried layer 26 are arranged along the up-down direction and both extend from the left side of the N-type drift region 14 to the right into the N-type drift region 25, the doping concentrations of the P-pillar buried layer 17 and the P-pillar buried layer 26 are different, and the length of the P-pillar buried layer 17 is longer than that of the P-pillar buried layer 17. The length of the buried layer 2 6, the doping concentrations of the N-type drift region 1 4 and the N-type drift region 2 5 are different.

[0016] The method for preparing the low on-resistance high voltage SOI LDMOS power device is described in detail in Figure 2 As shown, the following steps are included: 1) A P-type substrate 1 having a P-Window buried layer 2 and a BOX layer 3 is prepared, and an N-type drift region 1 4 and an N-type drift region 2 5 are epitaxially grown on the P-Window buried layer 2 and the BOX layer 3, respectively, and the P-Window buried layer 2 is located on the left side of the BOX layer 3; 2) Boron ions are implanted into the N-type drift region 14 and the N-type drift region 25 to form a P-pillar buried layer 26. The boron ion implantation concentration is 3.5×10 16 cm -3 , length 10 μm, thickness 0.2 μm; 3) Boron ions are injected again at a distance of 2 μm above the P-pillar buried layer 6 to form a P-pillar buried layer 7. The boron ion injection concentration is 5×10 16 , length 14μm, thickness 0.2μm; 4) Etching the left side of the N-type drift region 1 4 to form an oxide groove 8, the thickness of the oxide groove 8 is 5 μm and the width is 0.5 μm, and forming a source P+ region 10, a source N+ region 9, a P-body region 11 and a drain N+ region 12 on the upper surfaces of the N-type drift region 1 4 and the N-type drift region 2 5 by ion implantation and heating diffusion; 5) growing polysilicon in the oxidation groove 8 to form a trench gate; 6) The gate, source and drain of the device are formed on the top of the N-type drift region 1 4 and the N-type drift region 2 5 by dry etching and metal deposition.

[0017] Here, the thickness of the BOX layer 3 and the P-Window buried layer 2 is 1 μm; the thickness of the N-type drift region 1 4 and the N-type drift region 2 5 is 4 μm, and the doping concentrations of the N-type drift region 1 4 and the N-type drift region 2 5 are 3×10 15 cm -3 and 4.6×10 15 cm -3 , the doping element is phosphorus.

[0018] The present invention introduces a P-Window buried layer 2 on the left side of the BOX layer 3 (silicon dioxide layer). The introduction of the P-Window buried layer generates two high electric fields, improves the distribution of the electric field inside the device, and increases the BV (insulation breakdown voltage) of the PL-SOILDMOS structure. Since the N-type drift region 4 and the P-Window buried layer are mutually depleted, it is beneficial to increase the concentration of the drift region of the PL-SOILDMOS structure, thereby reducing its Ron,sp (on-resistance).

[0019] In the N-type drift region, a P-pillar buried layer 1 7 and a P-pillar buried layer 2 6 with different doping concentrations and lengths are set. The ends of the two P-pillar buried layers will generate high electric fields, so the body electric field of the device can be modulated well. The length of the P-pillar buried layer 1 is set longer because the P-pillar buried layer 1 can introduce the surface high electric field near the drain into the body of the device to avoid premature breakdown due to excessive concentration of the drain electric field. Since the two N-type drift regions have a depletion effect with the P-pillar buried layer 1 7 and the P-pillar buried layer 2, the drift region concentration of the PL-SOILDMOS structure can be greatly increased, thereby achieving the purpose of reducing Ron,sp (on-resistance).

[0020] In addition, the doping concentrations of the two N-type drift regions are different, so that a new surface electric field peak is generated at the interface between the two N-type drift regions, which can significantly improve the RESURF effect. There is a certain concentration difference between the doping concentrations of the two N-type drift regions. Compared with the conventional SOILDMOS structure with uniform doping distribution, the doping concentration of the drift region in the PL-SOILDMOS can be relatively large. The increase in the concentration of the drift region can improve the current capability of the PL-SOILDMOS structure, thereby reducing Ronp. In the design of the PL-SOILDMOS structure, the doping concentration of the N-type drift region 25 is relatively large relative to the doping concentration of the N-type drift region 14. This is because the high potential is near the drain, and also because the high electric field of the buried layer in some SOILDMOS structures is positively correlated with the doping concentration, improving the device body electric field distribution, thereby improving the PL-SOILDMOS breakdown voltage. The PL-SOILDMOS structure can avoid the electric field concentration between the N-type drift region 14 and the P-body region 11 when a planar gate electrode is used by using a grooved gate electrode, thereby improving BV.

[0021] The above contents are only preferred embodiments of the present invention. For ordinary technicians in this field, according to the concept of the present invention, there will be changes in the specific implementation methods and application scopes. The content of this specification should not be understood as limiting the present invention.

Claims

1. A low on-resistance high voltage SOI LDMOS power device, characterized in that: The invention comprises a P-type substrate, a BOX layer, a P-Window buried layer, an N-type drift region 1, an N-type drift region 2, a P-pillar buried layer 1 and a P-pillar buried layer 2, wherein the P-Window buried layer and the BOX layer are arranged on the upper surface of the P-type substrate along the left-right direction, the N-type drift region 1 and the N-type drift region 2 are respectively stacked on the P-Window buried layer and the BOX layer, an oxidation groove is arranged on the left side of the N-type drift region 1, polysilicon is grown in the oxidation groove, the P-pillar buried layer 1 and the P-pillar buried layer 2 are arranged along the up-down direction and both extend from the left side of the N-type drift region 1 to the right into the N-type drift region 2, the length of the P-pillar buried layer 1 is longer than the length of the P-pillar buried layer 2, and the doping concentrations of the N-type drift region 1 and the N-type drift region 2 are different.

2. A low on-resistance high voltage SOI LDMOS power device according to claim 1, characterized in that: The doping elements of the N-type drift region 1 and the N-type drift region 2 are phosphorus, wherein the doping concentration of the N-type drift region 1 is 3×10 15 cm -3 ; The doping concentration of the N-type drift region 2 is 4.6×10 15 cm -3 .

3. The low on-resistance high voltage SOI LDMOS power device according to claim 1, characterized in that: The doping elements of P-pillar buried layer 1 and P-pillar buried layer 2 are boron, and the doping concentration of P-pillar buried layer 1 is 5×10 16 cm -3 , length is 13-15μm; the doping concentration of the P-pillar buried layer II is 3.5×10 16 cm -3 , length is 9-11μm.

4. The low on-resistance high voltage SOI LDMOS power device according to claim 1, characterized in that: The thickness of the BOX layer and the P-Window buried layer is 1±0.05μm.

5. The low on-resistance high voltage SOI LDMOS power device according to claim 1, characterized in that: The thickness of the N-type drift region 1 and the N-type drift region 2 is 4±0.2 μm.

6. A method for preparing a low on-resistance high-voltage SOI LDMOS power device, used for preparing a low on-resistance high-voltage SOI LDMOS power device as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: 1) A P-type substrate with a P-Window buried layer and a BOX layer is prepared, and an N-type drift region 1 and an N-type drift region 2 are epitaxially grown on the P-Window buried layer and the BOX layer, respectively, and the P-Window buried layer is located on the left side of the BOX layer; 2) Boron ions are implanted into the N-type drift region 1 and the N-type drift region 2 to form a P-pillar buried layer 2; 3) Boron ions are implanted again at a distance of 2~3μm above the P-pillar buried layer 2 to form the P-pillar buried layer 1; 4) Etching the left side of the N-type drift region 1 to form an oxide groove, and forming a source P+ region, a source N+ region, a P-body region, and a drain N+ region on the upper surfaces of the N-type drift region 1 and the N-type drift region 2 by ion implantation and heating diffusion; 5) Grow polysilicon in the oxidation groove to form a trench gate; 6) The gate, source and drain of the device are formed on the top of the N-type drift region 1 and the N-type drift region 2 by dry etching and metal deposition.

7. The method for preparing a low on-resistance high-voltage SOI LDMOS power device according to claim 6, characterized in that: The oxidation groove has a thickness of 5±0.5 μm and a width of 0.5±0.05 μm.

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