A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer

Abstract

The present invention discloses a lateral double diffused metal oxide field effect transistor with a continuous P-Top layer. The present invention adopts a longitudinal P-type injection layer segment, the two ends of which are respectively located below a first shallow trench isolation region and a second shallow trench isolation region, and forms a continuous P-type injection layer by connecting the longitudinal P-type injection layer segment with the lateral P-type injection layer segment, and optimizes the doping introduced into the low-resistance path region and the STI region on the surface of the device to be continuous as a whole, thereby adjusting the electric field distribution of the low-resistance path region and the STI region together, and reducing the local electric field strength in the drift region of the device. The present invention improves the current performance by reducing the longitudinal width of the P-Top layer located between the first and second shallow trench isolation regions, thereby achieving the performance of the LDMOS device. The present invention adopts a continuous P-Top layer placed in the low-resistance path region, and improves the breakdown performance by optimizing the STI region, thereby improving the electric field control capability and device performance of the device.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor manufacturing, and in particular relates to a lateral double diffused metal oxide field effect transistor with a continuous P-Top layer. Background Art

[0002] In the field of semiconductor manufacturing, the BCD (bipolar-CMOS-DMOS) process is an important technology that combines the advantages of bipolar transistors, CMOS (complementary metal oxide semiconductor) and DMOS (channel metal oxide semiconductor) to manufacture high-performance analog and mixed signal circuits. One of the core components in the BCD process is the lateral double-diffused metal oxide field effect transistor (LDMOS), which is widely used in the field of power electronics due to its strong voltage resistance, large drive current, good switching performance and low production cost.

[0003] As the market demand for high-performance power LDMOS devices continues to expand, the industry urgently needs to develop a power LDMOS device with high breakdown voltage, low characteristic on-resistance, small gate-drain capacitance and high reliability.

[0004] The Split Shallow Trench Isolation (Split-STI) LDMOS device is an improved device, whose main feature is that the STI structure is partially removed and the gate field plate is no longer a whole, thereby achieving better electric field modulation capability. This structure is conducive to improving the current capability of the device, reducing the on-resistance, and thus improving the overall performance of the device.

[0005] However, traditional Split-STI LDMOS devices have at least the following problems:

[0006] 1) Electric field concentration effect: In high voltage and high frequency applications, electric field concentration effect is an important limiting factor. Traditional STI processes have limitations in reducing electric field concentration effect.

[0007] 2) Current path: Split-STI technology introduces a split structure on the insulating layer so that a portion of the electrons emitted from the source in the on state can be directly collected by the drain without bypassing the STI in the drift region, thereby forming an additional low-resistance current path on the device surface.

[0008] 3) Decreased breakdown voltage: Although partial removal of STI improves the current capability of the device, it may also cause a decrease in the breakdown voltage of the device.

[0009] In order to achieve high breakdown voltage and low specific on-resistance in traditional N-LDMOS devices, double-layer and multi-layer RESURF (Reduced Surface Field) technology is used to reduce hot carrier injection into the medium. By adding a segmented P-type injection layer (P-Top) on top of the N-type drift region, the specific on-resistance can be reduced. The segmented P-Top buried layer can achieve a better FOM (Figure of Merit) value, while maintaining the same breakdown voltage (BV), while increasing the doping concentration of the drift region. However, the introduction of the segmented P-Top currently also has at least the following disadvantages:

[0010] 1) Additional process: The addition of the segmented P-Top layer requires an additional process in the standard LDMOS process flow to fill it in the low-resistance current path. The optimization direction is linear doping, segmented P-Top, etc.

[0011] 2) The segmented P-Top region creates an electric field difficulty that assists in optimizing STI concentration.

[0012] In summary, although Split-STI LDMOS devices have advantages in improving current capability and reducing on-resistance, there are still challenges in electric field concentration effect, breakdown voltage and process integration of P-Top layer. The present invention aims to solve these problems and provide an improved LDMOS device structure to achieve higher breakdown voltage, lower on-resistance and better electric field distribution, thereby improving the performance and reliability of the device. Summary of the invention

[0013] The object of the present invention is to overcome the above-mentioned deficiencies of the prior art and provide a lateral double diffused metal oxide field effect transistor with a continuous P-Top layer.

[0014] The present invention is implemented as follows: a lateral double diffused metal oxide field effect transistor with a continuous P-Top layer comprises: a P-type substrate, a high voltage N-type drain region, an N-type drift region, a P-type injection layer, an N-type drain region, a first shallow trench isolation region, a second shallow trench isolation region, a P-type body region, an N-type source region, a P-type region, and a gate;

[0015] The P-type injection layer is an integrally formed structure, including a lateral P-type injection layer segment and at least one longitudinal P-type injection layer segment; wherein the lateral P-type injection layer segment is located above the N-type drift region between the first shallow trench isolation region and the second shallow trench isolation region; the longitudinal P-type injection layer segment includes an integrally formed first P-type injection layer sub-segment, a second P-type injection layer sub-segment, and a third P-type injection layer sub-segment, wherein the first P-type injection layer sub-segment and the third P-type injection layer sub-segment are respectively located below the first shallow trench isolation region and the second shallow trench isolation region, the second P-type injection layer sub-segment is located between the first shallow trench isolation region and the second shallow trench isolation region, and the two ends of the second P-type injection layer sub-segment are respectively connected to the first P-type injection layer sub-segment and the third P-type injection layer sub-segment, and extend to the middle section and are located above the N-type drift region between the first shallow trench isolation region and the second shallow trench isolation region.

[0016] Preferably, the high-voltage N-type drain region is arranged above the P-type substrate; the N-type drift region and the P-type body region are respectively arranged on both sides above the high-voltage N-type drain region; the N-type source region and the P-type region are arranged in the P-type body region, and the P-type region is located at the end of the N-type source region away from the N-type drift region; the N-type drift region is provided with a P-type injection layer, an N-type drain region, a first shallow trench isolation region, and a second shallow trench isolation region; the N-type drain region is located on the other side of the N-type drift region that is flush with the high-voltage N-type drain region; the gate is located above the first shallow trench isolation region, the second shallow trench isolation region, the N-type drift region, and the high-voltage N-type drain region.

[0017] Preferably, there is a distance between the first shallow trench isolation region and the second shallow trench isolation region, and they are separated by an N-type drift region.

[0018] Preferably, the P-type injection layer is spaced apart from the first shallow trench isolation region and the second shallow trench isolation region and is separated by an N-type drift region.

[0019] Preferably, the P-type injection layer is located in a low-resistance path region formed by the first shallow trench isolation region and the second shallow trench isolation region.

[0020] Preferably, the length of the P-type injection layer is smaller than the length of the low-resistance path region.

[0021] Preferably, the length of the first shallow trench isolation region is the same as the length of the second shallow trench isolation region.

[0022] Preferably, the same side of the first shallow trench isolation region and the second shallow trench isolation region are in contact with the N-type drain region.

[0023] Preferably, the top of the N-type drift region and the top of the P-type body region are flush with the top of the other side of the high-voltage N-type drain region.

[0024] Preferably, at least one longitudinal P-type injection layer segment in the P-type injection layer is close to the N-type drain region or the N-type source region.

[0025] The beneficial effects of the present invention are:

[0026] The present invention adopts a longitudinal P-type injection layer segment, with both ends located below the first shallow trench isolation region and the second shallow trench isolation region respectively, and forms a coherent P-type injection layer by connecting the longitudinal P-type injection layer segment with the transverse P-type injection layer segment, so as to optimize the doping introduced into the low-resistance path region and the STI region on the surface of the device and connect them into a whole, thereby adjusting the electric field distribution of the low-resistance path region and the STI region together, thereby reducing the local electric field strength in the drift region of the device.

[0027] The present invention improves the current performance by reducing the longitudinal width of the P-Top layer between the first and second shallow trench isolation regions, thereby achieving the performance of the LDMOS device.

[0028] In summary, the present invention adopts a coherent P-Top layer with a specific structure, and places it in the low-resistance path area of ​​the N-type drift region between the first shallow trench isolation region and the second shallow trench isolation region. By optimizing the STI region, the breakdown performance is improved, and the electric field control capability and device performance of the device are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 It is a schematic diagram of the structure of the LDMOS device provided in Example 1 of the present invention.

[0031] Figure 2 It is a schematic cross-sectional view of a partial structure of an LDMOS device provided in Example 1 of the present invention.

[0032] Figure 3 A schematic front cross-sectional view of a partial structure of an LDMOS device provided in Embodiment 1 of the present invention.

[0033] Figure 4 It is a schematic side cross-sectional view of a partial structure of an LDMOS device provided in Example 1 of the present invention.

[0034] Figure 5 It is a schematic cross-sectional view of a partial structure of an LDMOS device provided in Embodiment 2 of the present invention.

[0035] Figure 6It is a schematic cross-sectional view of a partial structure of an LDMOS device provided in Example 3 of the present invention.

[0036] Figure 7 It is a schematic cross-sectional view of a partial structure of an LDMOS device provided in Example 4 of the present invention.

[0037] Markings in the figure: 1, P-type substrate; 2, high-voltage N-type drain region; 3, N-type drift region; 4, P-type injection layer; 4-1, lateral P-type injection layer segment; 4-2, longitudinal P-type injection layer segment; 4-2-1, first P-type injection layer sub-segment; 4-2-2, second P-type injection layer sub-segment; 4-2-3, third P-type injection layer sub-segment; 5, N-type drain region; 6, first shallow trench isolation region; 7, second shallow trench isolation region; 8, P-type body region; 9, N-type source region; 10, P-type region; 11, gate. DETAILED DESCRIPTION

[0038] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0040] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or intervening elements may also be present. Moreover, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0041] As described in the background technology, in order to obtain a larger breakdown voltage, the drift region is extended in the prior art, resulting in poor device performance. In order to solve the above problem, the present application proposes a new LDMOS device and a manufacturing method thereof. The technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention.

[0042] Embodiment 1:

[0043] like Figure 1-Figure 4As shown, in this embodiment, an LDMOS device with a continuous P-Top layer is provided, and its structural design is intended to optimize and improve the breakdown performance, improve the electric field control capability of the device and the device performance. The following is a detailed description of the LDMOS device structure and an expansion of the preparation process:

[0044] The LDMOS device of this embodiment includes: a P-type substrate 1 (P-sub), a high-voltage N-type drain region 2 (HV-Nwell), an N-type drift region 3 (N-drift), a P-type injection layer 4 (P-top), an N-type drain region 5 (N+), a first shallow trench isolation region 6 (STI), a second shallow trench isolation region 7 (STI), a P-type body region 8 (P-body), an N-type source region 9 (N+), a P-type region 10 (P+), and a gate 11 (gate);

[0045] The high voltage N-type drain region 2 is arranged above the P-type substrate 1;

[0046] The N-type drift region 3 and the P-type body region 8 are respectively arranged on both sides above the high-voltage N-type drain region 2;

[0047] The top of the N-type drift region 3 and the top of the P-type body region 8 are flush with the top of the other side of the high-voltage N-type drain region 2;

[0048] The P-type body region 8 is provided with an N-type source region 9 and a P-type region 10, wherein the P-type region 10 is located at an end of the N-type source region 9 away from the N-type drift region 3;

[0049] The N-type drift region 3 is provided with a P-type injection layer 4, an N-type drain region 5, a first shallow trench isolation region 6, and a second shallow trench isolation region 7;

[0050] The N-type drain region 5 is located on the other side of the N-type drift region 3 that is flush with the high-voltage N-type drain region 2;

[0051] There is a distance between the first shallow trench isolation region 6 and the second shallow trench isolation region 7, and they are separated by the N-type drift region 3, thereby forming a low-resistance path region between the first shallow trench isolation region and the second shallow trench isolation region;

[0052] The gate 11 is located above the first shallow trench isolation region 6, the second shallow trench isolation region 7, the N-type drift region 3, and the high-voltage N-type drain region 2;

[0053] The P-type injection layer 4 is an integrated structure, which includes a transverse P-type injection layer segment 4-1 and a longitudinal P-type injection layer segment 4-2; the design of the transverse P-type injection layer segment 4-1 and the longitudinal P-type injection layer segment 4-2 helps to form a continuous P-type region, reduce electric field concentration, and thus improve the voltage resistance of the device. Specifically, the width and length design of the transverse P-type injection layer segment 4-1, as well as the distance from the first shallow trench isolation region 6 and the second shallow trench isolation region 7, are all for optimizing the electric field distribution and reducing the risk of device breakdown under high voltage.

[0054] Specifically, the lateral P-type injection layer segment 4-1 is located above the N-type drift region 3 between the first shallow trench isolation region 6 and the second shallow trench isolation region 7; the width of the lateral P-type injection layer segment 4-1 is 0.1-0.2μm, and the length is 0.3-0.6μm; the length of the first shallow trench isolation region 6 and the second shallow trench isolation region 7 is 0.5-0.8μm. After ion implantation, high-concentration doping will remain on the surface, and the injection layer will diffuse inward after a thermal annealing process. The doping legend shows the area where the P-type injection layer exists, and does not mean that there is a gap between the P-type injection layer and the device surface or the lower surface of the shallow trench isolation region.

[0055] The longitudinal P-type injection layer segment 4-2 is close to the N-type source region 9, and includes a first P-type injection layer sub-segment 4-2-1, a second P-type injection layer sub-segment 4-2-2, and a third P-type injection layer sub-segment 4-2-3 which are integrally formed;

[0056] The first P-type injection layer sub-segment 4-2-1 and the third P-type injection layer sub-segment 4-2-3 are respectively located below the first shallow trench isolation region 6 and the second shallow trench isolation region 7; the width of the first P-type injection layer sub-segment 4-2-1 is 0.1-0.2μm, and the length is 0.2-0.4μm; the length and width of the first P-type injection layer sub-segment 4-2-1 and the third P-type injection layer sub-segment 4-2-3 are equal. After ion implantation, high-concentration doping will remain on the surface, and the injection layer will diffuse inward after the thermal annealing process. The doping legend shows the area where the P-type injection layer exists, and does not mean that there is a gap between the P-type injection layer and the device surface or the lower surface of the shallow trench isolation region.

[0057] The second P-type injection layer sub-segment 4-2-2 is located between the first shallow trench isolation region 6 and the second shallow trench isolation region 7, and the two ends of the second P-type injection layer sub-segment 4-2-2 are respectively connected to the first P-type injection layer sub-segment 4-2-1 and the third P-type injection layer sub-segment 4-2-3, and extend to the middle section located above the N-type drift region 3 between the first shallow trench isolation region 6 and the second shallow trench isolation region 7;

[0058] There is a distance between the P-type injection layer 4 and the first shallow trench isolation region 6 and the second shallow trench isolation region 7, and they are separated by the N-type drift region 3;

[0059] The length of the P-type injection layer 4 is less than the length of the first shallow trench isolation region 6; the length of the first shallow trench isolation region 6 is the same as the length between the second shallow trench isolation regions 7;

[0060] One end of the first shallow trench isolation region 6 and one end of the second shallow trench isolation region 7 are in contact with the N-type drain region 5 .

[0061] In addition, this embodiment also provides a preparation process of the above LDMOS device, comprising the following steps:

[0062] Step 1: Perform N-type ion implantation on the P-type substrate 1, and obtain a high-voltage N-type drain region 2 after high-temperature annealing. This step is crucial to control the doping concentration and depth of the drain region;

[0063] Step 2: Obtain a shallow groove by etching, and form an N-type drift region 3 by N-type ion implantation and high-temperature annealing; the etching accuracy of the shallow groove and the dose of the N-type ion implantation need to be precisely controlled to ensure the formation of the N-type drift region 3.

[0064] Step 3: Form a P-type implantation layer 4 by high-temperature annealing after P-type ion implantation; the process parameters of high-temperature annealing after P-type ion implantation need to be carefully adjusted to ensure the formation and electrical characteristics of the P-type implantation layer 4.

[0065] Step 4: depositing silicon dioxide in the trench and using chemical mechanical polishing to form shallow trench isolation regions, namely, first shallow trench isolation regions 6 and second shallow trench isolation regions 7;

[0066] Step 5: Deposition and etching to form the gate 11; the formation of the gate 11 requires precise photolithography and etching technology to ensure the size and position of the gate.

[0067] Step 6: Use high-dose ion implantation to form an N-type drain region 5, a P-type body region 8, an N-type source region 9 and a P-type region 10.

[0068] Embodiment 2:

[0069] In this embodiment, based on the embodiment 1, only the longitudinal P-type injection layer segment 4-2 of the P-type injection layer 4 is located near the N-type drain region 5. Figure 5 , other process conditions are the same as those in Example 1.

[0070] Embodiment 3:

[0071] In this embodiment, on the basis of the embodiment 1, the P-type injection layer 4 is only changed to be formed by one lateral P-type injection layer segment 4-1 and two longitudinal P-type injection layer segments 4-2, which are formed in one piece. The two longitudinal P-type injection layer segments 4-2 are respectively located near the N-type drain region 5 and the N-type source region 9. Figure 6 , other process conditions are the same as those in Example 1.

[0072] Embodiment 4:

[0073] In this embodiment, on the basis of the embodiment 1, only the P-type injection layer 4 is changed to be formed by one horizontal P-type injection layer segment 4-1 and three vertical P-type injection layer segments 4-2, two vertical P-type injection layer segments 4-2 are respectively located near the N-type drain region 5 and the N-type source region 9, and another vertical P-type injection layer segment 4-2 is located between the two vertical P-type injection layer segments 4-2. Figure 7 , other process conditions are the same as those in Example 1.

[0074] The above embodiment uses a coherent P-top composed of multiple longitudinal P-type injection layer segments 4-2 and a transverse P-type injection layer segment 4-1. Compared with the segmented P-top, it optimizes the entire drift region, makes the electric field distribution in the drift region more uniform, reduces the local electric field peak, and reduces the risk of edge breakdown. In the low-resistance path, the P-top layer plays a role in optimizing the electric field and improving the withstand voltage. The structure coherent with the longitudinal P-type injection layer segment 4-2 can achieve a more uniform electric field distribution. The uniform electric field improves the breakdown voltage performance of the device. The coherent P-top structure suppresses the excessive concentration of the electric field at the edge of the STI, avoids the opening of parasitic devices, reduces the risk of leakage current, and thus improves the stability and reliability of the device in long-term operation. The interference of local high electric field areas on electron migration is reduced, thereby reducing the scattering effect, improving the electron migration efficiency, and reducing the temperature rise in the local area, thereby improving the BV and device performance of the device.

[0075] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer, comprising: P-type substrate (1), high-voltage N-type drain region (2), N-type drift region (3), P-type injection layer (4), N-type drain region (5), first shallow trench isolation region (6), second shallow trench isolation region (7), P-type body region (8), N-type source region (9), P-type region (10), gate (11); characterized in that: The P-type injection layer (4) is an integrally formed structure, comprising a transverse P-type injection layer segment (4-1) and at least one longitudinal P-type injection layer segment (4-2); wherein the transverse P-type injection layer segment (4-1) is located above the N-type drift region (3) between the first shallow trench isolation region (6) and the second shallow trench isolation region (7); the longitudinal P-type injection layer segment (4-2) comprises an integrally formed first P-type injection layer sub-segment (4-2-1), a second P-type injection layer sub-segment (4-2-2), and a third P-type injection layer sub-segment (4-2-3); the first P-type injection layer sub-segment (4-2-1) is an integrally formed structure, and the second P-type injection layer sub-segment (4-2-2) is an integrally formed structure, and the second P-type injection layer sub-segment (4-2-3) is an integrally formed structure, wherein the first P-type injection layer sub-segment (4-2-1) is an integrally formed structure, wherein the first P-type injection layer sub-segment (4-2-2) is an integrally formed structure, wherein the first ...3) is an integrally formed structure, wherein the first P-type injection layer sub-segment (4-2-1) is an integrally formed structure, wherein the first P-type injection layer sub-segment (4-2-3) is an integrally formed structure. -2-1), and the third P-type injection layer sub-segment (4-2-3) are respectively located below the first shallow trench isolation region (6) and the second shallow trench isolation region (7), the second P-type injection layer sub-segment (4-2-2) is located between the first shallow trench isolation region (6) and the second shallow trench isolation region (7), and the two ends of the second P-type injection layer sub-segment (4-2-2) are respectively connected to the first P-type injection layer sub-segment (4-2-1) and the third P-type injection layer sub-segment (4-2-3), and extend to the middle section located above the N-type drift region (3) between the first shallow trench isolation region (6) and the second shallow trench isolation region (7).

2. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 1, characterized in that: The high-voltage N-type drain region (2) is arranged above the P-type substrate (1); the N-type drift region (3) and the P-type body region (8) are arranged on both sides above the high-voltage N-type drain region (2); the N-type source region (9) and the P-type region (10) are arranged in the P-type body region (8), and the P-type region (10) is located at the end of the N-type source region (9) away from the N-type drift region (3); the N-type drift region (3) is provided with a P-type injection layer (4), an N-type drain region (5), a first shallow trench isolation region (6), and a second shallow trench isolation region (7); the N-type drain region (5) is located on the other side of the N-type drift region (3) that is flush with the high-voltage N-type drain region (2); and the gate (11) is located above the first shallow trench isolation region (6), the second shallow trench isolation region (7), the N-type drift region (3), and the high-voltage N-type drain region (2).

3. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 2, characterized in that: There is a distance between the first shallow trench isolation region (6) and the second shallow trench isolation region (7), and they are separated by the N-type drift region (3).

4. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 3, characterized in that: The P-type injection layer (4) is spaced apart from the first shallow trench isolation region (6) and the second shallow trench isolation region (7), and is separated by an N-type drift region (3).

5. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 1, characterized in that The P-type injection layer (4) is located in a low-resistance path region formed between the first shallow trench isolation region (6) and the second shallow trench isolation region (7).

6. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 5, characterized in that The length of the P-type injection layer (4) is smaller than the length of the low-resistance path region.

7. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 1, characterized in that The length of the first shallow trench isolation region (6) is the same as the length between the second shallow trench isolation regions (7).

8. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 1, characterized in that The same side of the first shallow trench isolation region (6) and the second shallow trench isolation region (7) are in contact with the N-type drain region (5).

9. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 1, characterized in that: The top of the N-type drift region (3) and the top of the P-type body region (8) are flush with the top of the other side of the high-voltage N-type drain region (2).

10. A lateral double diffused metal oxide field effect transistor with a continuous P-Top layer according to claim 1, characterized in that: At least one longitudinal P-type injection layer segment (4-2) in the P-type injection layer (4) is close to the N-type drain region (5) or the N-type source region (9).

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