Ethernet circuit suitable for 2 * 2-vote-2 architecture security computer

Abstract

The utility model provides an Ethernet circuit suitable for a 2 * 2-vote-2 architecture security computer, which relates to the technical field of network communication, and comprises a central processing unit (CPU), a first intra-system communication circuit, a second intra-system communication circuit, a first intersystem communication circuit and a second intersystem communication circuit, each intersystem communication circuit is connected with two CPUs, and each CPU is correspondingly provided with an intra-system communication circuit. Working state signals of the CPU are transmitted to an intra-system control chip of the intra-system communication circuit through a reset sub-circuit of the intra-system communication circuit, the intra-system control chip controls the CPU to conduct data transmission after judging the signals, and the inter-system communication circuit receives data transmission signals of the CPU through a PWM wave constant voltage sub-circuit of the inter-system communication circuit. And the intersystem control chip is used for transmitting a data signal indicating whether to work or not to the intersystem communication circuit after logical judgment. The circuit meets the requirements of an Ethernet communication circuit of a 2 * 2-vote-2 architecture security computer.

Description

Technical Field

[0001] The utility model relates to the technical field of network communication, in particular to an Ethernet circuit suitable for a 2-by-2-by-2 architecture security computer. Background Art

[0002] With the development of railway transportation, the demand for driving safety is increasing, and the requirements for driving safety equipment are improving. As a train control device that controls train operation and ensures railway driving safety, safety computers are gradually becoming the core of train control equipment in recent years. Safety computers are mainly divided into two architectures: 3 out of 2 and 2x2 out of 2. Since 2x2 out of 2 safety computers are easy to maintain, can be tested offline, and their safety performance is several times that of 3 out of 2 systems, 2x2 out of 2 safety computers have been increasingly widely used in train control equipment that emphasizes safety first. The 2x2 out of 2 architecture consists of four computers (CPUs) forming two subsystems, one of which is used as the host to output control instructions, and the other is hot standby. The two computers in the subsystem each execute a set of programs with the same code, and then compare the calculation results. If they are consistent, the output is driven. If they are inconsistent, it is considered that a computer is faulty and the output is immediately switched to another subsystem. Among them, the 2x2 out of 2 architecture is divided into 2 series, each of which has two computer units (CPUs) that perform data calculations and comparisons at the same time. After confirming that the results are consistent, the two CPUs simultaneously control the drive unit to output the results. Ethernet communication circuits controlled by a single CPU under other architectures are no longer applicable. Therefore, it is necessary to design an Ethernet circuit suitable for a 2x2x2 architecture secure computer. Utility Model Content

[0003] The utility model aims to provide an Ethernet circuit suitable for a 2x2 take 2 architecture security computer, so as to meet the demand for an Ethernet communication circuit conforming to the 2x2 take 2 architecture security computer.

[0004] To achieve the above purpose, the utility model provides the following solutions:

[0005] An Ethernet circuit suitable for a 2x2-out-of-2 architecture security computer includes a CPU, and further includes: a first intra-system communication circuit, a second intra-system communication circuit, a first inter-system communication circuit, and a second inter-system communication circuit; the first intra-system communication circuit and the second intra-system communication circuit are both connected to the CPU, and the first inter-system communication circuit and the second inter-system communication circuit are both connected to the CPU;

[0006] The first intra-system communication circuit and the second intra-system communication circuit both include: an intra-system control chip, an external active crystal oscillator sub-circuit and a reset sub-circuit corresponding to the intra-system control chip; the intra-system control chip is connected to the external active crystal oscillator sub-circuit and the reset sub-circuit corresponding to the intra-system control chip and the CPU corresponding to the intra-system communication circuit, and the reset sub-circuit is connected to the CPU;

[0007] The first inter-system communication circuit and the second inter-system communication circuit both include: an inter-system control chip, an external active crystal oscillator sub-circuit and a PWM wave constant voltage sub-circuit corresponding to the inter-system control chip; the inter-system control chip is connected to the external active crystal oscillator sub-circuit and the PWM wave constant voltage sub-circuit corresponding to the inter-system control chip, and the PWM wave constant voltage sub-circuit is connected to the CPU.

[0008] Optionally, the in-system control chip adopts a DP83640TVV / NOPB Ethernet PHY chip, and a power pin of the in-system control chip is provided with a filter capacitor; the filter capacitor is used to provide a stable power input for the in-system control chip.

[0009] Optionally, the external active crystal oscillator subcircuit has a CRYSTAL series chip built in; the external active crystal oscillator subcircuit is used to provide a 25 MHz external clock input for the intra-system control chip and the inter-system control chip.

[0010] Optionally, the CPU includes a first CPU and a second CPU.

[0011] Optionally, the reset subcircuit is used to enable the first CPU to control the in-system control chips corresponding to the first CPU and the second CPU, and to enable the second CPU to control the in-system control chips corresponding to the first CPU and the second CPU.

[0012] Optionally, the inter-system control chip adopts a DM9000CIEP Ethernet MAC+PHY chip; the inter-system control chip is used to control the working states of the first CPU and the second CPU.

[0013] Optionally, the PWM wave constant voltage circuit has two built-in NAND gate chips, both of which use SN74LVC1G00DBVR series chips, and the PWM wave constant voltage circuit is connected to the first CPU and the second CPU; the PWM wave constant voltage circuit is used to provide a dual enable control terminal for the inter-system control chip.

[0014] According to the specific embodiments provided by the utility model, the utility model discloses the following technical effects: an Ethernet circuit suitable for a 2-by-2-take-2 architecture security computer, including a CPU, and also including: a first intra-system communication circuit, a second intra-system communication circuit, a first inter-system communication circuit and a second inter-system communication circuit; the first intra-system communication circuit and the second intra-system communication circuit are both connected to the CPU, and the first inter-system communication circuit and the second inter-system communication circuit are both connected to the CPU; the first intra-system communication circuit and the second intra-system communication circuit both include: an intra-system control chip, an external active crystal oscillator sub-circuit and a reset sub-circuit corresponding to the intra-system control chip; the intra-system control chip is connected to the external active crystal oscillator sub-circuit corresponding to the intra-system control chip, the reset sub-circuit and the CPU corresponding to the intra-system communication circuit, and the reset sub-circuit is connected to the CPU; the first inter-system communication circuit and the second inter-system communication circuit both include: an inter-system control chip, an external active crystal oscillator sub-circuit and a PWM wave constant voltage sub-circuit corresponding to the inter-system control chip; the inter-system control chip is connected to the external active crystal oscillator sub-circuit and the PWM wave constant voltage sub-circuit corresponding to the inter-system control chip, and the PWM wave constant voltage sub-circuit is connected to the CPU. The utility model meets the requirements of a 2x2 take 2 architecture security computer controlled simultaneously by two CPUs and having mutually independent and redundant security Ethernet communication circuits, which can be used for redundant security communication within a system and for redundant security communication between devices between systems and has universal applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 This is a structural diagram of an Ethernet communication circuit according to an embodiment of the utility model;

[0017] Figure 2 This is a schematic diagram of the DP83640 chip circuit of an embodiment of the utility model; Figure 2 Part (a) is the structure diagram of the DP83640 chip; Figure 2 Part (b) is the schematic diagram of the filter capacitor circuit of the DP83640 chip;

[0018] Figure 2 Part (c) is the schematic diagram of the external active crystal oscillator circuit corresponding to the DP83640 chip; Figure 2 Part (d) is the schematic diagram of the reset subcircuit;

[0019] Figure 3 This is a schematic diagram of the DM9000 chip circuit of an embodiment of the utility model; Figure 3Part (a) is the DM9000 chip structure diagram; Figure 3 Part (b) is the schematic diagram of the filter capacitor circuit of the DM9000 chip;

[0020] Figure 3 Part (c) is the schematic diagram of the impedance matching circuit of the Ethernet signal line of the DM9000 chip; Figure 3 Part (d) is the schematic diagram of the external active crystal oscillator circuit corresponding to the DM9000 chip; Figure 3 Part (e) is the structure diagram of the PWM wave constant voltage circuit and the NOT gate chip; Figure 3 Part (f) is the main circuit diagram of the PWM wave constant voltage circuit.

[0021] Explanation of the reference numerals: 1. first CPU; 2. second CPU; 3. first intra-system communication circuit; 4. second intra-system communication circuit; 5. first inter-system communication circuit; 6. second inter-system communication circuit. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0023] The utility model aims to provide an Ethernet circuit suitable for a 2x2 take 2 architecture security computer, so as to meet the demand for an Ethernet communication circuit conforming to the 2x2 take 2 architecture security computer.

[0024] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0025] like Figure 1 As shown, the utility model provides an Ethernet circuit suitable for a 2-by-2-by-2 architecture security computer, including a CPU, and also including: a first intra-system communication circuit 3, a second intra-system communication circuit 4, a first inter-system communication circuit 5 and a second inter-system communication circuit 6; the first intra-system communication circuit 3 and the second intra-system communication circuit 4 are both connected to the CPU, and the first inter-system communication circuit 5 and the second inter-system communication circuit 6 are both connected to the CPU; the CPU includes a first CPU 1 and a second CPU 2.

[0026] like Figure 2As shown, the first intra-system communication circuit 3 and the second intra-system communication circuit 4 both include: an intra-system control chip, an external active crystal oscillator sub-circuit and a reset sub-circuit corresponding to the intra-system control chip; the intra-system control chip is connected to the external active crystal oscillator sub-circuit corresponding to the intra-system control chip, the reset sub-circuit and the CPU corresponding to the intra-system communication circuit, and the reset sub-circuit is connected to the CPU; and also include: other auxiliary peripheral current limiting resistors, matching resistors, filter capacitors, inductors and light-emitting diodes.

[0027] like Figure 2 As shown in part (a), the control chip in the system adopts DP83640TVV / NOPB Ethernet PHY chip (DP83640 chip). The first CPU1 and the second CPU2 correspond to a DP83640 chip respectively. The chip transmits data with the corresponding CPU through the MII bus. The MII bus is provided with line matching resistors R3, R4, R7, R8, R9 and R16 and pull-up and pull-down resistors R5, R6 and R15. Resistors R5 and R6 are used for pulling up the CRS chip select signal and RX_ER signal of the MII bus, and resistor R15 is used for pulling down the RX_DV signal of the MII bus.

[0028] Among them, pin 1 of the DP83640 chip is connected to resistor R3, the resistance of resistor R3 is 22 ohms, pin 7 is connected to the 3.3V input voltage through resistor R10, pins 8 to 12 are empty pins, the resistance of resistor R10 is 4.7K ohms, pins 13, 14, 16 and 17 are respectively connected to one end of resistor R11, resistor R12, resistor R13 and resistor R14, and the other ends of resistors R11 to R14 are connected to the 3.3V input voltage together. The resistance values ​​of resistors R11 to R14 are all 49.9 ohms, with an accuracy of 1%. Pins 15 and 18 are grounded, pin 19 is connected to the 3.3V input voltage, pin 20 is grounded through resistor R18, the resistance value of resistor R18 is 4.87K ohms, with an accuracy of 1%, pins 21 to 25 are empty pins, pin 26 is connected to resistor R19, resistor R19 is connected to LED1, LED1 is connected to the 3.3V input voltage, the resistance value of resistor R19 is 10K ohms, and LED1 is green The 32-pin is connected to the 3.3V input voltage, the resistance value of the resistor R17 is 1.5K ohms, the 33-pin is an empty pin, the 34-pin is connected to the external active crystal oscillator subcircuit corresponding to the chip, the 35-pin is grounded, the 36-pin and the 37-pin are empty pins, the 38-pin is connected to the resistor R16, the resistance value of the resistor R16 is 22 ohms, and the 39-pin is connected to the external active crystal oscillator subcircuit corresponding to the chip through the resistor R15. Grounded, the resistance of resistor R15 is 2.2K ohms, pin 40 and pin 41 are connected to one end of resistor R6 and resistor R5 respectively, the other ends of resistor R6 and resistor R5 are commonly connected to 3.3V input voltage, the resistance values ​​of resistor R6 and resistor R5 are both 2.2K ohms, pins 43 to 46 are connected to resistors R9, R8, R7 and R4 respectively, the resistance values ​​of resistors R9, R8, R7 and R4 are all 22 ohms, pin 47 is grounded, and pin 48 is connected to 3.3V input voltage.

[0029] Specifically, the maximum operating voltage of the DP83640 chip is 4.2V, and it has a typical operating voltage of 3.3V. It can work normally within the voltage fluctuation range of ±5%, and supports 10 / 100M full-duplex working mode, meeting the performance requirements of communication rate ≥1Mbps and data throughput ≥400Kbps, and the operating temperature meets the operating range of -40℃ to +85℃.

[0030] Figure 2Part (b) is the filter capacitor of the DP83640 chip, which is used to provide a stable power input for the DP83640 chip. Among them, one end of capacitors C3 and C4 are connected to the 32-pin of the DP83640 chip and the 3.3V input voltage, and the other end is grounded. The capacitance of capacitor C3 is 100nF, and the withstand voltage is 50V. The capacitance of capacitor C4 is 10μF, and the withstand voltage is 25V. One end of capacitors C5 and C6 are connected to the 48-pin of the DP83640 chip and the 3.3V input voltage, and the other end is grounded. The capacitance of capacitor C5 is 100nF, and the withstand voltage is 50V. The capacitance of capacitor C6 is 10μF, and the withstand voltage is 25V.

[0031] like Figure 2 As shown in part (c), the external active crystal oscillator subcircuit corresponding to the DP83640 chip consists of a CRYSTAL series chip, an inductor and a capacitor. Among them, one end of capacitor C1 is connected to the 3.3V input voltage and one end of inductor L1, the other end of capacitor C1 is connected to one end of capacitor C2, the ground electrode and pin 2 of the CRYSTAL series chip, the other end of capacitor C2 is connected to the other end of the inductor and pin 4 of the CRYSTAL series chip, pin 3 of the CRYSTAL series chip is connected to pin 34 of the DP83640 chip, and pin 1 is an empty pin. Among them, the capacitance of capacitor C1 is 100nF, and the withstand voltage is 50V, the capacitance of capacitor C2 is 1nF, and the withstand voltage is 50V, and the impedance of inductor L1 at a frequency of 100MHz is 1.5K ohms. This external active crystal oscillator subcircuit is used to provide a 25MHz external clock input for the DP83640 chip.

[0032] like Figure 2 As shown in part (d), the reset subcircuit adopts a coupled RESET circuit and is connected to the first CPU1 and the second CPU2, so that the first CPU1 and the second CPU2 can both control the working state of the DP83640 chip of the first CPU1 and the DP83640 chip of the second CPU2. Among them, the connection end of the resistor R1 and the resistor R2 is connected to the 29 pin of the DP83640 chip, the other end of the resistor R2 is connected to the 3.3V input voltage, and the other end of the resistor R1 is connected to the CPU. The resistance value of the resistor R1 is 20 ohms, and the resistance value of the resistor R2 is 1K ohms. When any of the CPUs is abnormal, the high level or low level signal sent by the RESET circuit is used to reset any DP83640 chip, so that any DP83640 chip does not perform data transmission, ensuring that both CPUs are in normal working state before data transmission.

[0033] like Figure 3As shown, the first inter-system communication circuit 5 and the second inter-system communication circuit 6 both include: an inter-system control chip, an external active crystal oscillator sub-circuit and a PWM wave constant voltage sub-circuit corresponding to the inter-system control chip; the inter-system control chip is connected to the external active crystal oscillator sub-circuit and the PWM wave constant voltage sub-circuit corresponding to the inter-system control chip, and the PWM wave constant voltage sub-circuit is connected to the CPU; and also include: other auxiliary peripheral current limiting resistors, matching resistors, filter capacitors, inductors, Schottky diodes and light-emitting diodes.

[0034] like Figure 3 As shown in part (a), the inter-system control chip adopts the DM9000CIEP Ethernet MAC+PHY chip (DM9000 chip); the DM9000 chip corresponding to the first inter-system communication circuit 5 transmits data with a group of first CPU1 and second CPU2 through the FSMC bus, and the DM9000 chip corresponding to the second inter-system communication circuit 6 transmits data with another group of first CPU1 and second CPU2 through the FSMC bus.

[0035] Among them, pin 1 of the DM9000 chip is grounded through resistor R30, the resistance value of resistor R30 is 6.8K ohms, and the accuracy is 1%. Pin 2 is connected to the 2.5V input voltage, pins 3 and 4 are connected to capacitor C9 through resistors R25 and R27 respectively, capacitor C9 is grounded, the resistance values ​​of resistors R25 and R27 are both 49.9 ohms, the accuracy is 1%, the capacitance of capacitor C9 is 100nF, and the withstand voltage is 50V, pin 5 is connected to pin 6 and grounded together, pins 7 and 8 are connected to capacitor C7 through resistors R22 and R23 respectively, capacitor C7 is grounded, the resistance values ​​of resistors R22 and R23 are both 49.9 ohms, the accuracy is 1%, the capacitance of capacitor C7 is 100nF, and the withstand voltage is 50V, pin 9 is connected to the 2.5V input voltage, pin 15 is grounded, and pin 19 is empty. Pin 20 is connected to the 3.3V input voltage and pin 23 through resistor R21, the resistance value of resistor R21 is 4.7K ohms, pin 21 is grounded through resistor R20, the resistance value of resistor R20 is 0 ohms, pin 30 is connected to the 3.3V input voltage, pin 33 is grounded, pin 34 is connected to the 3.3V input voltage through resistor R29, the resistance value of resistor R29 is 4.7K ohms, pin 37 is connected to the 3.3V input voltage through resistor R32, the resistance value of resistor R32 is 4.7K ohms, pin 40 is connected to the 3.3V input voltage connected to pin 37 through resistor R33, pin 41 is grounded, pin 42 is connected to the 3.3V input voltage, pin 43 is an empty pin, pin 44 is connected to the external active crystal oscillator sub-circuit corresponding to the chip, pins 45, 47 and 48 are grounded together, and pin 46 is an empty pin.

[0036] The maximum operating voltage of the DM9000 chip is 3.6V, and it has a typical operating voltage of 3.3V. It can work normally within the voltage fluctuation range of ±5%, and supports 10 / 100M full-duplex working mode, meeting the performance requirements of communication rate ≥1Mbps and data throughput ≥400Kbps, and the operating temperature meets the working range of -40℃ to +85℃.

[0037] like Figure 3 As shown in part (b), the filter capacitors of the DM9000 chip are used to provide a stable power input for the DM9000 chip. Among them, one end of capacitors C13 and C15 are connected to the DM9000 chip pin 23 and the 3.3V input voltage, and the other end is grounded. One end of capacitors C14 and C16 are connected to the DM9000 chip pin 30 and the 3.3V input voltage, and the other end is grounded. One end of capacitor C17 is connected to the DM9000 chip pin 42 and the 3.3V input voltage, and the other end is grounded. One end of capacitor C18 is connected to the DM9000 chip pin 9 and the 2.5V input voltage, and the other end is grounded. One end of capacitors C19 and C20 are connected to pin 2 of the DM9000 chip and the 2.5V input voltage, and the other end is grounded; the capacitance of capacitors C13 and C14 are both 10μF, and the withstand voltage is 25V; the capacitance of capacitors C15, C16 and C17 are all 100nF, and the withstand voltage is 50V; the capacitance of capacitors C18 and C19 are both 22μF, and the withstand voltage is 6.3V; the capacitance of capacitor C20 is 100nF, and the withstand voltage is 50V.

[0038] like Figure 3 As shown in part (c), the impedance matching resistor of the Ethernet signal line of the DM9000 chip greatly improves the anti-interference ability and stability of the communication circuit.

[0039] like Figure 3 As shown in part (d), the external active crystal oscillator sub-circuit corresponding to the DM9000 chip is the same as the external active crystal oscillator sub-circuit corresponding to the DP83640 chip, wherein pin 3 of the CRYSTAL series chip is connected to pin 44 of the DM9000 chip, and the external active crystal oscillator sub-circuit is used to provide a 25MHz external clock input for the DM9000 chip.

[0040] like Figure 3 Part (e) and Figure 3As shown in part (f), the PWM wave constant voltage circuit is set on the FSMC bus. The PWM wave constant voltage circuit is composed of two NAND gate chips (U3 and U4) connected to the PWM wave constant voltage main circuit. The two NAND gate chips are both SN74LVC1G00DBVR series chips. The PWM wave constant voltage main circuit is connected to the first CPU1 and the second CPU2; the PWM wave constant voltage circuit serves as an enable end, and the dual CPU dynamic enable method is used to control the working state of the DM9000 chip.

[0041] Among them, the 5 pins of U3 and U4 are connected to different 3.3V input voltages, the 1 pin of U3 is connected to the 2 pin, and is connected to the external chip select control signal from the first CPU1, the 3 pins of U3 and U4 are connected to the ground electrode, the 4 pin of U3 is connected to the pin of U4, and are both grounded through the resistor R34, the resistance value of the resistor R34 is 4.7K ohms, the 4 pin of U4 is connected to the 3.3V input voltage through the resistor R31, the resistance value of the resistor R31 is 4.7K ohms, the 2 pin of U4 is connected to the resistor R28, the resistance value of the resistor R28 is 34.8K ohms, the accuracy is 1%, and the voltage is Resistor R28 is grounded through resistor R24, and the resistance of resistor R24 ​​is 5.1K ohms. Capacitor C8 is connected in parallel with resistor R24, and the capacitance of capacitor C8 is 4.7μF, and the withstand voltage is 25V. Diode D1 and diode BAS40-04 are forward connected and connected in parallel with resistor R24. The positive electrode of diode D1 is grounded, and the cathode of diode D1 and the positive electrode of diode BAS40-04 are connected with capacitor C10, and the capacitance of capacitor C10 is 4.7μF, and the withstand voltage is 25V. Capacitor 10 is connected to CPU through resistor R26, and the resistance of resistor R26 is 100 ohms.

[0042] Only when the first CPU1 and the second CPU2 are both in normal working state, the generated PWM wave signal of the specified frequency passes through the NAND gate chip in the PWM wave constant voltage circuit to obtain the level signal for controlling the working state of the DM9000 chip, so that the DM9000 chip can perform normal data transmission.

[0043] The beneficial effects of the utility model are as follows:

[0044] The utility model meets the requirements of a 2x2 take 2 architecture security computer controlled simultaneously by two CPUs and having mutually independent and redundant security Ethernet communication circuits, which can be used for redundant security communication within a system and for redundant security communication between devices between systems and has universal applicability.

[0045] This article uses specific examples to illustrate the principles and implementation methods of the utility model. The above examples are only used to help understand the method and core ideas of the utility model. At the same time, for those skilled in the art, according to the ideas of the utility model, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the utility model.

Claims

1. An Ethernet circuit suitable for a 2x2-out-of-2 architecture secure computer, comprising a CPU, characterized in that: It also includes: a first intra-system communication circuit, a second intra-system communication circuit, a first inter-system communication circuit, and a second inter-system communication circuit; the first intra-system communication circuit and the second intra-system communication circuit are both connected to the CPU, and the first inter-system communication circuit and the second inter-system communication circuit are both connected to the CPU; The first intra-system communication circuit and the second intra-system communication circuit both include: an intra-system control chip, an external active crystal oscillator subcircuit and a reset subcircuit corresponding to the intra-system control chip; the intra-system control chip is connected to the external active crystal oscillator subcircuit corresponding to the intra-system control chip, the reset subcircuit and the CPU corresponding to the intra-system communication circuit, and the reset subcircuit is connected to the CPU; The first inter-system communication circuit and the second inter-system communication circuit both include: an inter-system control chip, an external active crystal oscillator sub-circuit and a PWM wave constant voltage sub-circuit corresponding to the inter-system control chip; the inter-system control chip is connected to the external active crystal oscillator sub-circuit and the PWM wave constant voltage sub-circuit corresponding to the inter-system control chip, and the PWM wave constant voltage sub-circuit is connected to the CPU.

2. The Ethernet circuit suitable for a 2x2-out-of-2 architecture secure computer according to claim 1, characterized in that: The in-system control chip adopts a DP83640TVV / NOPB Ethernet PHY chip, and a power pin of the in-system control chip is provided with a filter capacitor; the filter capacitor is used to provide a stable power input for the in-system control chip.

3. The Ethernet circuit suitable for a 2x2-out-of-2 architecture secure computer according to claim 1, characterized in that: The external active crystal oscillator subcircuit has a CRYSTAL series chip built in it; the external active crystal oscillator subcircuit is used to provide a 25MHz external clock input for the intra-system control chip and the inter-system control chip.

4. The Ethernet circuit suitable for a 2x2-out-of-2 architecture secure computer according to claim 1, characterized in that: The CPU includes a first CPU and a second CPU.

5. The Ethernet circuit applicable to a 2x2-out-of-2 architecture secure computer according to claim 4, characterized in that: The reset subcircuit is used to enable the first CPU to control the in-system control chip corresponding to the first CPU and the second CPU, and to enable the second CPU to control the in-system control chip corresponding to the first CPU and the second CPU.

6. The Ethernet circuit applicable to a 2x2-out-of-2 architecture secure computer according to claim 4, characterized in that: The inter-system control chip adopts a DM9000CIEP Ethernet MAC+PHY chip; the inter-system control chip is used to control the working states of the first CPU and the second CPU.

7. The Ethernet circuit applicable to a 2x2-out-of-2 architecture secure computer according to claim 4, characterized in that: The PWM wave constant voltage subcircuit has two built-in NAND gate chips, both of which are SN74LVC1G00DBVR series chips. The PWM wave constant voltage subcircuit is connected to the first CPU and the second CPU; the PWM wave constant voltage subcircuit is used to provide a dual enable control terminal for the inter-system control chip.

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