Matrix video signal low-delay transmission system

Abstract

The utility model discloses a matrix video signal low-delay transmission system. The matrix video signal low-delay transmission system comprises an interface chip input module and a first FPGA unit; the system comprises a first FPGA unit, a second FPGA unit and an interface chip output module, wherein the first FPGA unit comprises a data packaging module and a Serdes sending module which are connected with each other; the second FPGA unit comprises a serdes receiving module, a ddr cache module and an Osd module which are connected with one another in sequence; and the interface chip input module, the first FPGA unit and the second FPGA unit are connected with one another. Video signal data of the structure is subjected to high-speed serial transmission of SERDES and cache processing of DDR, so that video signals are input through a matrix and then output and processed, low-delay transmission of video data compared with video source data is achieved, data time delay is lower compared with similar products, and a good data transmission effect is achieved.

Description

Technical Field

[0001] The utility model belongs to the relevant technical field of video transmission, and particularly relates to a matrix video signal low-delay transmission system. Background Art

[0002] With the rapid development of network technology, all information tends to be transmitted over long distances and at high speeds through the network. The network video matrix system effectively solves the bandwidth problem of signal transmission through signal encoding and decoding technology, and realizes low-bandwidth and low-loss network transmission of high-definition video.

[0003] However, the existing video data transmission has a long delay time. During the data transmission process, you will obviously find that the data transmission speed is relatively slow, so it needs to be improved. Utility Model Content

[0004] The purpose of the utility model is to provide a matrix video signal low-delay transmission system, which solves the problem that the existing data transmission has a long delay time and you will obviously find that the data transmission speed is relatively slow during the data transmission process.

[0005] In order to solve the above technical problems, the utility model is realized by the following technical solutions:

[0006] The utility model is a matrix video signal low-delay transmission system, the transmission system comprising:

[0007] The interface chip input module is responsible for converting the data coming from the HDMI interface into the corresponding receiving signal;

[0008] A first FPGA unit includes a data packaging module and a Serdes sending module connected to each other;

[0009] The second FPGA unit includes a serdes receiving module, a ddr buffer module and an osd module which are connected to each other in sequence;

[0010] Interface chip output module, used for data output operation to drive HDMI display;

[0011] Among them, the interface chip input module, the first FPGA unit and the second FPGA unit are connected to each other, and the data packaging module is used to package the received video data into input information to the Serdes sending module according to the protocol; the Serdes sending module is used to send data to the serdes receiving module of the second FPGA unit; the serdes receiving module is used to perform protocol unpacking processing on the received serdes data; the ddr cache module is responsible for caching the data unpacked by the serdes receiving module; the Osd module is used to generate the data in the ddr cache module into corresponding output information and then give it to the interface chip output module.

[0012] Preferably, the output signal converted by the Osd module may be a clock signal clk or / and a line synchronization signal h or / and a field synchronization signal v or / and a valid signal de or / and a data signal data.

[0013] Preferably, the received signal converted by the interface chip input module may be a clock signal clk or / and a line synchronization signal h or / and a field synchronization signal v or / and a valid signal de or / and a data signal data.

[0014] Preferably, in order to implement security detection on the transmitted data and further improve the security of data transmission, a data security detection module for performing security detection on the transmitted data is also connected between the data packaging module and the interface chip input module.

[0015] Preferably, in order to realize the function of timing data transmission, the Serdes transmission module is connected with a timer, and the timer is used to transmit the transmitted data at a timing.

[0016] The utility model has the following beneficial effects: the video signal data of the structure is transmitted serially through the high-speed serial transmission of SERDES and the cache processing of DDR, so that the video signal is input through the matrix and then output for processing, and the low-latency transmission of the video data is achieved compared with the video source data. Compared with similar products, it has a lower data time delay and achieves a better data transmission effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the connection structure of a matrix video signal low-latency transmission system in Example 1;

[0018] Figure 2 This is a schematic diagram of the connection structure of a matrix video signal low-latency transmission system in Example 2;

[0019] Figure 3 This is a schematic diagram of the connection structure of a matrix video signal low-latency transmission system in Example 3.

[0020] Reference numerals:

[0021] Interface chip input module 1, first FPGA unit 2, data packaging module 201, Serdes sending module 202, second FPGA unit 3, serdes receiving module 301, ddr cache module 302,

[0022] Osd module 303, interface chip output module 4, timer 5, data security detection module 6. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the utility model clearer, the technical solution in the embodiments of the utility model will be clearly and completely described below in combination with the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0024] Example 1

[0025] See also Figure 1 As shown, this embodiment discloses a matrix video signal low-latency transmission system, and the transmission system includes:

[0026] Interface chip input module 1 is used to convert the data coming from the HDMI interface into corresponding receiving signals;

[0027] The first FPGA unit 2 includes a data packaging module 201 and a Serdes sending module 202 connected to each other;

[0028] The second FPGA unit 3 includes a serdes receiving module 301, a ddr buffer module 302 and an osd module 303 which are connected to each other in sequence;

[0029] The interface chip output module 4 is used for data output operation to realize driving HDMI display;

[0030] Among them, the interface chip input module 1, the first FPGA unit 2 and the second FPGA unit 3 are interconnected, and the data packaging module 201 is used to package the received video data into input information to the Serdes sending module 202 according to the protocol; the Serdes sending module 202 is used to send data to the serdes receiving module 301 of the second FPGA unit 3; the serdes receiving module 301 is used to perform protocol unpacking processing on the received serdes data; the ddr cache module 302 is responsible for caching the data unpacked by the serdes receiving module 301; the Osd module 303 is used to generate the data in the ddr cache module 302 into corresponding output information and then give it to the interface chip output module 4.

[0031] Preferably, the output signal converted by the Osd module 303 may be a clock signal clk or / and a line synchronization signal h or / and a field synchronization signal v or / and a valid signal de or / and a data signal data.

[0032] Preferably, the received signal converted by the interface chip input module 1 may be a clock signal clk or / and a line synchronization signal h or / and a field synchronization signal v or / and a valid signal de or / and a data signal data.

[0033] The specific working principle of this structure is as follows: first, after the video source data signal comes in through the HDMI interface, the corresponding interface chip in the interface chip input module 1 is used to convert the video signal into a clock signal (clk) and / or a line synchronization signal (h) and / or a field synchronization signal (v) and / or a valid signal (de) and / or a data signal (data) data interface to the first FPGA unit 2. At this time, the data packaging module 201 in the first FPGA unit 2 packages the data accordingly, and then sends it out through the high-speed serial transceiver SERDES inside the Serdes sending module 202 in the first FPGA unit 2, thereby realizing the input data 0 delay transmission, and then transmitted to the second FPGA unit 3, the data is received by the serdes receiving module 301 in the second FPGA unit 3 and the data is unpacked into the corresponding data signal, and then the DDR inside the ddr cache module 302 in the second FPGA unit 3 is called. The IP core is used to program a DDR data controller, which directly reads and writes data to realize the DDR data cache. The data passing through the DDR and the generated driving signal are used to generate a clock signal (clk) and / or a line synchronization signal (h) and / or a field synchronization signal (v) and / or a valid signal (de) and / or a data signal (data) to be given to the corresponding interface chip in the interface chip output module 4 through the Osd module 303. The interface chip then gives the data to the corresponding interface (HDMI, VGA, SDI, DVI) interface to be displayed on the display screen. Therefore, the video signal data of this structure is transmitted via the high-speed serial transmission of SERDES and the cache processing of DDR, thereby realizing the video signal input through the matrix and then outputting it for processing, realizing the low-latency transmission of video data compared to the video source data, having a lower data time delay than similar products, and achieving a better data transmission effect. It should be noted that the above-mentioned interface chip input module 1, data packaging module 201, Serdes sending module 202, serdes receiving module 301, ddr cache module 302, Osd module 303, interface chip output module 4, timer 5, and data security detection module 6 are all existing technologies, which can be purchased directly, so no specific description is given.

[0034] Example 2

[0035] See also Figure 2 As shown, the general structure of a matrix video signal low-latency transmission system disclosed in this embodiment is the same as that of Example 11, except that, as a preference, a data security detection module 6 for performing security detection on the transmitted data is further connected between the data packaging module 201 and the interface chip input module 1. This structure connects a data security detection module 6 between the data packaging module 201 and the interface chip input module 1 to perform security detection on the transmitted data, thereby further improving the security of data transmission.

[0036] Example 3

[0037] See also Figure 3 As shown, the general structure of a matrix video signal low-latency transmission system disclosed in this embodiment is the same as that of Embodiment 11, except that, as a preference, the Serdes sending module 202 is connected with a timer 5, and the timer 5 is used to time the data to be sent. By adding a timer 5, this structure can realize the function of timed data sending.

[0038] The above are only preferred embodiments of the present invention and do not limit the present invention. Any modification to the technical solutions recorded in the aforementioned embodiments and any equivalent replacement of some of the technical features therein, any modification, equivalent replacement, and improvement made are all within the protection scope of the present invention.

Claims

1. A matrix video signal low-delay transmission system, characterized in that: The transmission system comprises: The interface chip input module (1) is used for inputting and is responsible for converting the data coming in from the HDMI interface into corresponding receiving signals; A first FPGA unit (2), comprising a data packaging module (201) and a Serdes sending module (202) connected to each other; The second FPGA unit (3) comprises a Serdess receiving module (301), a DDR buffer module (302) and an Osd module (303) which are sequentially connected to each other; The interface chip output module (4) is used for data output operation to realize driving HDMI display; The interface chip input module (1), the first FPGA unit (2) and the second FPGA unit (3) are interconnected, and the data packaging module (201) is used to package the received video data into input information for the Serdes sending module (202) according to the protocol; the Serdes sending module (202) is used to send the data to the serdes receiving module (301) of the second FPGA unit (3); the serdes receiving module (301) is used to perform protocol unpacking processing on the received serdes data; the ddr cache module (302) is responsible for caching the data unpacked by the serdes receiving module (301); and the osd module (303) is used to generate the data in the ddr cache module (302) into corresponding output information and then send it to the interface chip output module (4).

2. A matrix video signal low-delay transmission system according to claim 1, characterized in that: The output signal converted by the Osd module (303) may be a clock signal clk or / and a line synchronization signal h or / and a field synchronization signal v or / and a valid signal de or / and a data signal data.

3. A matrix video signal low-delay transmission system according to claim 1, characterized in that: The received signal converted by the interface chip input module (1) may be a clock signal clk or / and a line synchronization signal h or / and a field synchronization signal v or / and a valid signal de or / and a data signal data.

4. A matrix video signal low-delay transmission system according to claim 1, characterized in that: A data security detection module (6) for performing security detection on transmitted data is also connected between the data packaging module (201) and the interface chip input module (1).

5. The low-delay transmission system for matrix video signals according to claim 1, characterized in that: The Serdes sending module (202) is connected to a timer (5), and the timer (5) is used to send the data at a fixed time.

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