Data storage structure, chip and electronic equipment

Abstract

The utility model relates to the field of integrated circuit design, and provides a data storage structure, a chip and electronic equipment. The data storage structure comprises a semi-dynamic register which comprises a first dynamic latch structure and a second static latch structure, and the first dynamic latch structure and the second static latch structure are in data connection; the first dynamic latch structure stores charges based on a parasitic capacitance at an electrode node; the second static latch structure comprises a data transmission path and a feedback loop; the second static latch structure stores data based on the feedback loop; the area occupied by the first dynamic latch structure is smaller than the chip area occupied by the second static latch structure. The semi-dynamic register of the data storage structure has the advantages of being small in occupied area and high in data stability.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a data storage structure, a chip and an electronic device. Background Art

[0002] In modern integrated circuit design, registers are commonly used as basic units for storing data information and are widely used in sequential logic. Registers can be divided into Static D-flip-flop (static register) and Dynamic D-flip-flop (dynamic register). Both have advantages and disadvantages. The data of static registers is stable and not volatile, but its circuit is more complicated, such as Figure 1 As shown in (a), it takes up a large chip area. Figure 1 As shown in (b), the dynamic register occupies a small area and consumes low power, but the dynamic register stores data through the parasitic capacitance of the device's internal storage node. The data stored in the dynamic node is easily affected by leakage, resulting in data loss.

[0003] Currently, there is a need for a register and data storage structure that occupies a small chip area and stores data stably. Utility Model Content

[0004] In view of this, the present application aims to provide a data storage structure, a chip and an electronic device, so that the data stability of the register and the occupied chip area have better effects.

[0005] In a first aspect, an embodiment of the present application provides a data storage structure, including: a semi-dynamic register, including a first dynamic latch structure and a second static latch structure, the first dynamic latch structure and the second static latch structure being data connected; the first dynamic latch structure stores charge based on parasitic capacitance at an electrode node; the second static latch structure includes a data transmission path and a feedback loop; the second static latch structure stores data based on the feedback loop; the area occupied by the first dynamic latch structure is smaller than the chip area occupied by the second static latch structure.

[0006] The dynamic register usually includes a two-level dynamic latch structure, forming two dynamic nodes for storing data, and storing data through the two dynamic nodes. The static latch usually includes a two-level static latch structure, and each static latch structure includes a feedback loop for storing data. In the embodiment of the present application, the first-level latch structure of the dynamic register and the static register is respectively adopted to form a semi-dynamic register in the data storage structure of the present application. The first-level structure of the semi-dynamic register is a first dynamic latch structure, which stores data through electrode nodes, and the second-level structure is a second static latch structure, which stores data through a feedback loop. Since the first level is a dynamic latch structure, the area required for it will be smaller than that required for a pure static register, and the second level is a static latch structure. Therefore, the data can be stably stored at the second level, reducing the time when the data is affected by leakage and improving the stability of data storage. As a result, the semi-dynamic register makes the data stability ability and the occupied chip area of ​​the data storage structure between the dynamic register and the static register, so that it can be used in more scenarios.

[0007] In one embodiment, the data storage structure also includes: a pulse clock generation module, which is used to connect to a clock source; the pulse clock generation module is used to receive a source clock signal output by the clock source, and adjust the source clock signal to obtain a pulse clock signal; the pulse clock signal includes a first level and a second level; the first level is less than half of the signal period of the source clock signal, and is greater than the minimum pulse width condition for storing data in the first dynamic latch structure; the pulse clock generation module is also respectively connected to the clock end of the first dynamic latch structure and the clock end of the second static latch structure to output the pulse clock signal to the first dynamic latch structure and the second static latch structure; the first level is used to make the electrode node of the first dynamic latch structure in a state of storing data; the second level is used to make the second static latch structure temporarily store data.

[0008] In the embodiment of the present application, the source clock signal is adjusted by the pulse clock generation module to obtain a pulse clock signal for controlling the semi-dynamic register to store data. The first level of the pulse clock signal is used to control the electrode node of the first dynamic latch structure to be in the state of storing data nodes, and because the time of the first level is less than half of the clock cycle and greater than the minimum pulse width condition for storing data in the first dynamic latch structure, that is, under the premise of satisfying the first dynamic latch structure to store data, the duration of the first level is reduced, so that the time for storing data in the first dynamic latch structure is reduced, and the time for storing data in the second static latch structure is extended, thereby reducing the influence of leakage on the stability of the first dynamic latch structure on the storage data, and making the second static latch structure with more stable storage data store data as much as possible, thereby further reducing the influence of leakage on data storage and improving the stability of data storage.

[0009] In one embodiment, the pulse clock generation module includes a pulse width modulation circuit; the pulse clock generation module is used to modulate the duty cycle of the first level in the source clock signal to obtain the pulse clock signal.

[0010] Pulse width modulation can adjust the duty cycle of a high level within a clock cycle. Therefore, in an embodiment of the present application, a pulse width modulation circuit can be set to modulate the duty cycle of a first level to obtain a pulse clock signal.

[0011] In one embodiment, the pulse clock generation module includes: a cutting edge circuit; the cutting edge circuit is used to generate a cutting edge signal, and logically process the source clock signal according to the cutting edge signal within the first level duration of the source clock signal to generate a falling edge during the first level period of the source clock signal to obtain the pulse clock signal.

[0012] In the embodiment of the present application, the edge cutting circuit can perform logic processing on the source clock signal, generate a falling edge during the first level period of the source clock signal, and maintain the low level unchanged until the next rising edge arrives, so that the duration of the first level in the pulse clock signal is less than the duration of the first level in the source clock signal. Compared with pulse width modulation, the pulse clock signal may change with transmission in a scenario with a large number of semi-dynamic register levels, and the pulse clock signal processed by the edge cutting circuit has better stability.

[0013] In one embodiment, the data output end of the first dynamic latch structure is connected to the data input end of the second static latch structure; or, the data input end of the first dynamic latch structure is connected to the data output end of the second static latch structure.

[0014] In the embodiment of the present application, the order in which the first dynamic latch structure and the second static latch structure are connected in the data storage structure is not limited, and the corresponding connection method can be selected according to the layout in the chip to meet the usage requirements of the data storage structure in different scenarios.

[0015] In one embodiment, the first dynamic latch structure includes a transmission gate; the transmission gate includes a first NMOS and a first PMOS; the gates of the first NMOS and the first PMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the sources of the first NMOS and the first PMOS are connected to the port of input data, and the drains of the first NMOS and the first PMOS are used to output data.

[0016] In the embodiment of the present application, the transmission gate can store data in the capacitor at the output node, so the transmission gate can be configured in the first dynamic chip structure. The transmission gate only needs two devices, the first NMOS and the first PMOS, to be implemented, which can effectively reduce the chip area occupied by the first dynamic latch structure.

[0017] In one embodiment, the second static latch structure includes a transmission unit and a feedback loop, the transmission unit includes a second PMOS, a third PMOS, a third NMOS, and a second NMOS; the source of the second PMOS is connected to a power supply, the source of the second NMOS is grounded, the drain of the second PMOS is connected to the source of the third PMOS, the drain of the third PMOS is connected to the drain of the third NMOS, and the source of the third NMOS is connected to the drain of the second NMOS; the gates of the second NMOS and the second NMOS are used to input data; the gates of the third PMOS and the third NMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the feedback loop includes: a fifth PMOS, a sixth PMOS, a seventh PMOS, and a fifth NMOS , the sixth NMOS and the seventh NMOS; the gates of the fifth NMOS and the fifth PMOS are connected to the drain of the third PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth PMOS is connected to the power supply; the source of the fifth NMOS is grounded; the drain of each device in the sixth PMOS, the seventh PMOS, the seventh NMOS and the sixth NMOS is connected to the source of the next device; the source of the sixth PMOS is connected to the power supply; the source of the sixth NMOS is grounded; the drain of the seventh PMOS and the drain of the seventh NMOS are connected to the drain of the third PMOS; the sixth PMOS and the third NMOS are connected to the same clock terminal; the sixth NMOS and the third PMOS are connected to the same clock terminal.

[0018] In the embodiment of the present application, the fifth PMOS, the sixth PMOS, the seventh PMOS, the fifth NMOS, the sixth NMOS, and the seventh NMOS can form a feedback loop at the source of the third NMOS to stably store data through the above connection under the control of the clock. Compared with the second stage also using a dynamic latch structure, the second stage uses a static latch structure, and the static latch structure has almost no dynamic leakage data loss problem, which can reduce the impact of leakage on the data stored in the second static latch structure, effectively reduce the possibility of data loss, and improve the stability of data storage.

[0019] In one embodiment, the second static latch structure includes a transmission unit and a feedback loop, the transmission unit includes a tenth PMOS, an eleventh PMOS, a tenth NMOS, and an eleventh NMOS; the source of the tenth PMOS is connected to a power supply, and the source of the tenth NMOS is grounded; the drain of the tenth PMOS is connected to the source of the eleventh PMOS, the drain of the eleventh PMOS is connected to the drain of the eleventh NMOS, and the drain of the tenth NMOS is connected to the source of the eleventh NMOS; the gates of the eleventh PMOS and the eleventh NMOS are used to input data; the gates of the tenth PMOS and the tenth NMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the feedback loop includes: a fifth PMOS, a sixth PMOS, and a seventh PMOS , the fifth NMOS, the sixth NMOS and the seventh NMOS; the gates of the fifth NMOS and the fifth PMOS are connected to the drain of the eleventh PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth PMOS is connected to the power supply; the source of the fifth NMOS is grounded; the drain of each device in the sixth PMOS, the seventh PMOS, the seventh NMOS and the sixth NMOS is connected to the source of the next device; the source of the sixth PMOS is connected to the power supply; the source of the sixth NMOS is grounded; the drain of the seventh PMOS and the drain of the seventh NMOS are connected to the drain of the eleventh PMOS; the sixth PMOS and the tenth NMOS are connected to the same clock terminal; the sixth NMOS and the tenth PMOS are connected to the same clock terminal.

[0020] In one embodiment, the first dynamic latch structure includes a three-state gate; the three-state gate includes an eighth NMOS, a ninth NMOS, an eighth PMOS and a ninth PMOS; the gates of the ninth NMOS and the ninth PMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the gates of the eighth NMOS and the eighth PMOS are connected to the port for inputting data, and the drain of the ninth NMOS is connected to the drain of the ninth PMOS for outputting data; the drain of the eighth PMOS is connected to the source of the ninth PMOS, and the source of the ninth NMOS is connected to the drain of the eighth NMOS; the source of the eighth PMOS is connected to a power supply; and the source of the eighth NMOS is grounded.

[0021] The tri-state gate has a high impedance state, the input end is invalid in the high impedance state, and the internal data can be stored in the parasitic capacitance of the dynamic storage node. Therefore, in the embodiment of the present application, a tri-state gate can also be set in the first dynamic latch structure to store data through the tri-state gate. Accordingly, compared with the feedback loop of the static latch structure, the tri-state gate requires fewer devices and occupies a smaller chip area, which can also achieve the effect of reducing the chip area occupied.

[0022] In a second aspect, an embodiment of the present application provides a chip, comprising the data storage structure described in any one of the first aspects above.

[0023] In a third aspect, an embodiment of the present application provides an electronic device, comprising the chip described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A circuit diagram of an existing static register and a dynamic register;

[0026] Figure 2 A schematic diagram of a data storage structure provided by an embodiment of the present application;

[0027] Figure 3 A first dynamic latch structure provided for an embodiment of the present application includes a circuit diagram of a transmission gate;

[0028] Figure 4 A first dynamic latch structure provided for an embodiment of the present application includes a circuit diagram of a tri-state gate;

[0029] Figure 5 A circuit diagram of a semi-dynamic register provided in one embodiment of the present application;

[0030] Figure 6 A circuit diagram of another transmission unit provided in an embodiment of the present application;

[0031] Figure 7 An extended schematic diagram of a data storage structure provided in an embodiment of the present application;

[0032] Figure 8 A schematic diagram of a pulse clock signal provided in an embodiment of the present application;

[0033] Fig. 9 A schematic diagram of a pulse clock generation module provided in an embodiment of the present application.

[0034] Icons: data storage structure 10 ; semi-dynamic register 100 ; first dynamic latch structure 110 ; second static latch structure 120 ; pulse clock generation module 200 . DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present application more clear, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.

[0036] See also Figure 2 , Figure 2 A schematic diagram of a data storage structure provided in an embodiment of the present application. The data storage structure 10 provided in an embodiment of the present application includes a semi-dynamic register 100 .

[0037] The semi-dynamic register 100 includes a two-level structure, wherein the first-level structure is a first dynamic latch structure 110 , and the other-level structure is a second static latch structure 120 .

[0038] The existing dynamic register includes a two-stage latch structure, which constitutes two electrode nodes, and charges are stored at the electrode nodes to achieve data storage. The latch structure of the dynamic register has the characteristic of occupying a small chip area. Therefore, in the embodiment of the present application, the first dynamic latch structure 110 can store charges based on the electrode nodes to achieve data storage.

[0039] In an embodiment of the present application, the first dynamic latch structure 110 may include a transmission gate.

[0040] For example, see Figure 3 , Figure 3A schematic diagram of a first dynamic latch structure 110 including a transmission gate is provided for an embodiment of the present application, wherein CKN and CKP are two clock terminals for transmitting opposite clock signals, a first NMOS is connected to CKN, a first PMOS is connected to CKP, and D is a port for inputting data.

[0041] The transmission gate includes a first NMOS and a first PMOS; the gates of the first NMOS and the first PMOS are respectively connected to different clock terminals and respectively receive opposite clock signals output by different clock terminals; the sources of the first NMOS and the first PMOS are connected to the ports for inputting data, and the drains of the first NMOS and the first PMOS are used for outputting data.

[0042] The transmission gate has a state with very high off-resistance, in which the transmission gate can act as a switch to store data on the parasitic capacitance formed by the electrode node, thereby storing the data on the parasitic capacitance at the electrode node S0 (ie, the drain of the first NMOS and the first PMOS).

[0043] Similarly, the tri-state gate has similar characteristics to the transmission gate. The tri-state gate has a high impedance state. In the high impedance state, the tri-state gate can also be used as a switch to store data on the parasitic capacitor at the output node of the tri-state gate. Therefore. In another embodiment of the present application, the first dynamic latch structure may also include a tri-state gate. The specific structure of the tri-state gate can refer to the prior art and will not be expanded here.

[0044] For example, see Figure 4 , Figure 4 A schematic diagram of a first dynamic latch structure 110 including a tri-state gate provided in an embodiment of the present application, wherein P8 is the eighth PMOS, P9 is the ninth PMOS, N8 is the eighth NMOS, and N9 is the ninth NMOS.

[0045] In this example, the first dynamic latch structure 110 includes a three-state gate; the three-state gate includes an eighth NMOS, a ninth NMOS, an eighth PMOS and a ninth PMOS; the gates of the eighth NMOS and the eighth PMOS are respectively connected to different clock terminals, the sources of the ninth NMOS and the ninth PMOS are connected to the ports of input data, the drain of the ninth NMOS is connected to the drain of the ninth PMOS for outputting data; the drain of the eighth PMOS is connected to the source of the ninth PMOS, the source of the ninth NMOS is connected to the drain of the eighth NMOS; the source of the eighth PMOS is connected to the power supply; the source of the eighth NMOS is grounded.

[0046] Whether the first dynamic latch structure 110 is a tri-state gate or a transmission gate, the first dynamic latch structure 110 occupies a smaller area than the static latch structure of the static register. Among them, since the transmission gate uses fewer devices, the use of the transmission gate can further reduce the occupied chip area compared to the tri-state gate. The above is only an example, and the first dynamic latch structure 110 can also use a circuit with similar functions, which will not be expanded here.

[0047] The existing static register includes a two-stage latch structure, and each stage of the latch structure includes a feedback loop for data storage, so that the data storage has a high stability. Therefore, in the embodiment of the present application, the semi-dynamic register 100 can also be provided with a second static latch structure 120, and the second static latch structure 120 is provided with a feedback loop to stably store data through the feedback loop.

[0048] It can be understood that due to the existence of the feedback loop, the second static latch structure 120 needs to occupy a larger area. Therefore, the area occupied by the first dynamic latch structure 110 is smaller than the chip area occupied by the second static latch structure 120 .

[0049] In the embodiment of the present application, the second static latch structure 120 may include two parts, namely a transmission unit and a feedback loop. Figure 5 , Figure 5 A circuit diagram of a data storage structure 10 provided in one embodiment of the present application. P2 to P7 represent the second PMOS to the seventh PMOS, respectively, and N2 to N7 represent the second NMOS to the seventh NMOS, respectively. P2, P3, N3, and N2 constitute a transmission unit, and P5, P6, P7, N5, N6, and N7 constitute a feedback loop.

[0050] like Figure 5 As shown, in a feasible implementation, the transmission unit of the second static latch structure 120 may include a second PMOS, a third PMOS, a third NMOS, and a second NMOS; the source of the second PMOS is connected to the power supply, the source of the second NMOS is grounded, the drain of the second PMOS is connected to the source of the third PMOS, the drain of the third PMOS is connected to the drain of the third NMOS, and the source of the third NMOS is connected to the drain of the second NMOS; the gates of the second NMOS and the second NMOS are used to input data; the gates of the third PMOS and the third NMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals.

[0051] See also Figure 6 , Figure 6Another connection method of a transmission unit provided in an embodiment of the present application, in another feasible implementation manner, the transmission unit includes a tenth PMOS, an eleventh PMOS, a tenth NMOS and an eleventh NMOS, the source of the tenth PMOS is connected to a power supply, and the source of the tenth NMOS is grounded; the drain of the tenth PMOS is connected to the source of the eleventh PMOS, the drain of the eleventh PMOS is connected to the drain of the eleventh NMOS, and the source of the eleventh NMOS is connected to the drain of the tenth NMOS; the gates of the tenth PMOS and the tenth NMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the gates of the eleventh PMOS and the eleventh NMOS are used to input data.

[0052] Accordingly, please continue to refer to Figure 5 , the feedback loop may include: the fifth PMOS, the sixth PMOS, the seventh PMOS, the fifth NMOS, the sixth NMOS and the seventh NMOS; the gates of the fifth NMOS and the fifth PMOS are connected to the drain of the third PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth PMOS is connected to the power supply; the source of the sixth NMOS is grounded; the drain of each device in the sixth PMOS, the seventh PMOS, the seventh NMOS and the sixth NMOS is connected to the source of the next device; the source of the sixth PMOS is connected to the power supply; the source of the sixth NMOS is grounded; the drain of the seventh PMOS and the drain of the seventh NMOS are connected to the drain of the third PMOS; the sixth PMOS and the third NMOS are connected to the same clock terminal; the sixth NMOS and the third PMOS are connected to the same clock terminal. The feedback loop may be connected to the transmission unit provided in any of the above embodiments. In another embodiment of the transmission unit, the drain of the seventh NMOS is connected to the drain of the eleventh PMOS, the sixth PMOS and the tenth NMOS are connected to the same clock terminal; the sixth NMOS and the tenth PMOS are connected to the same clock terminal.

[0053] In the embodiment of the present application, the connection order of the first dynamic latch structure 110 and the second static latch structure 120 in the semi-dynamic register 100 is not limited. For example, in one embodiment, it can be as follows Figure 5 As shown, the data output end of the first dynamic latch structure 110 is connected to the data input end of the second static latch structure 120. In another embodiment, the data input end of the first dynamic latch structure 110 and the data output end of the second static latch structure 120 may be connected. In this embodiment, if the first dynamic structure 110 is further connected to a structure with parasitic capacitance to store data, that is, it may be as follows Figure 5 The structure composed of P4 and N4 is shown.

[0054] The connection sequence of the first dynamic latch structure 110 and the second static latch structure 120 does not affect their functions and chip area. Therefore, the connection sequence of the two can be configured according to actual requirements in circuit design.

[0055] like Figure 5 As shown, the connection point between the transmission unit and the feedback loop is node S1, and the data is temporarily stored at S1 through the feedback loop. After the clock signal changes, the data is output through P4 and N4 at the output end. Among them, P4 is the fourth PMOS, N4 is the fourth NMOS, the gates of P4 and N4 are connected to the node S1, the source of P4 is connected to the power supply, the drain of P4 is connected to the drain of N4, and the source of N4 is grounded.

[0056] by Figure 5 As an example, the working state of the semi-dynamic register 100 is described. The first dynamic latch structure 110 temporarily stores data at a high level, and the second static latch structure 120 temporarily stores data at a low level.

[0057] Different clock signals include CKP and CKN. CKP is input to P1, P6, and N3 respectively, and CKN is input to N1, P3, and N6 respectively.

[0058] State 1: When the pulse clock signal is at a low level, CKP=0, CKN=1. At this time, P3 / N3 is closed, P5 / N5 / P6 / N6 / P7 / N7 forms a feedback loop to the S1 node to lock the data, and the output Q is stable. At this time, P1 / N1 is turned on, and the input D is directly transmitted to the S0 node through N1 / P1.

[0059] State 2: When the rising edge of the pulse clock signal arrives, CKP rises from 0 to 1, CKN falls from 1 to 0, N1 / P1 is closed, S0 is floating, and the data is temporarily stored by the P2 / N2 gate capacitance of the first dynamic latch structure 110 and the parasitic capacitance at the S0 node; P3 / N3 is turned on, P6 / N6 is closed, and the data originally stored in the S0 node is directly transmitted to S1, and then transmitted to the output Q through P4 / N4.

[0060] State 3: When the pulse clock signal is at a high level, CKP=1, CKN=0. At this time, the S0 node holds data by parasitic capacitance.

[0061] State 4: When the falling edge of the pulse clock signal arrives, CKN rises from 0 to 1, CKP falls from 1 to 0, N1 / P1 is turned on, and data is directly transmitted to the S0 node through N1 / P1 after being input from D. Since P3 / N3 is closed, P6 / N6 is turned on, P5 / N5 / P6 / N6 / P7 / N7 forms a feedback loop to the S1 node, and the data at the node S1 is stored in the feedback loop, and the output terminal Q is stable, and then enters state 1.

[0062] As mentioned above, the first dynamic latch structure 110 is still affected by leakage. Specifically, the leakage model of the first dynamic latch structure 110 can be expressed as:

[0063] ΔQ=i*t

[0064] Wherein, ΔQ represents the charge change of the dynamic storage node caused by leakage (which can be charging or discharging), i represents the parasitic current or leakage current, and t represents the duration of leakage.

[0065] The charge Q stored in the parasitic capacitance of the dynamic node leaks charge ΔQ under the influence of leakage, making the remaining charge of the storage node become Q ′ =Q-ΔQ. When the residual charge Q' is not enough to keep the data output of the output stage (storage node back stage) unchanged, the stored data is mis-flipped, which is considered to be caused by leakage. Therefore, the data stability can be improved by reducing the leakage time, reducing the leakage current or increasing the total amount of stored charge (such as increasing the power supply voltage, increasing the parasitic capacitance). In the embodiment of the present application, the leakage effect is reduced by reducing the first level pulse width to reduce the leakage duration t.

[0066] In one embodiment of the present application, the frequency of the pulse clock signal output to the semi-dynamic register 100 may be increased to reduce the duration of leakage during each data transmission.

[0067] In some other embodiments of the present application, the pulse clock signal output to the semi-dynamic register 100 may be adjusted so that the time for the first dynamic latch structure 110 to temporarily store data is reduced.

[0068] See also Figure 7 , Figure 7 This is an expanded schematic diagram of a data storage structure 10 provided in an embodiment of the present application. In an embodiment of the present application, a pulse clock adjustment circuit may also be configured in the data storage structure 10.

[0069] The pulse clock generating module 200 is used to connect to a clock source.

[0070] In this embodiment, the pulse clock generation module 200 is used to receive the source clock signal output by the clock source, and adjust the source clock signal to obtain a pulse clock signal. The pulse clock signal includes a first level and a second level; the first level is less than half of the signal period of the source clock signal and greater than the minimum pulse width condition for the first dynamic latch structure 110 to store data.

[0071] The pulse clock generation module 200 is also connected to the clock end of the first dynamic latch structure 110 and the clock end of the second static latch structure 120 respectively to output the pulse clock signal to the first dynamic latch structure 110 and the second static latch structure 120; the first level is used to make the electrode node of the first dynamic latch structure 110 in a state of storing data; the second level is used to make the second static latch structure 120 temporarily store data.

[0072] For example, if the first dynamic latch structure 110 is stored by a high-level control data, the first level may be a high level, and the second level may be a low level.

[0073] See also Figure 8 , Figure 8 Schematic diagram of a pulse clock signal provided in an embodiment of the present application. Figure 8 The first and second pulse clock signals are pulse clock signals of the static register and the dynamic register respectively. The static register and the dynamic register can directly use the source clock signal, that is, the high level and the low level each occupy half of the clock cycle.

[0074] In the embodiment of the present application, the pulse clock signal is adjusted by the pulse clock generation module 200, and the duration of the high-level signal used by the first dynamic latch structure 110 is shortened to less than half of the clock cycle, and correspondingly, the duration of the low-level signal exceeds half of the clock cycle. The shorter the time for the first dynamic latch structure to hold data, the more conducive it is to data stability.

[0075] By adjusting the pulse clock signal, for the first dynamic latch structure 110, since the duration of the first level in a single cycle is reduced, the time required for the first dynamic latch structure 110 to save data is reduced, and the possibility of data being lost in the first dynamic latch structure 110 due to leakage is reduced. For the second static latch structure 120, since the low level time is extended, the time for saving data through the second static latch structure 120 is extended, and the stability of the second static latch structure 120 saving data is higher. Therefore, the time for the second static latch structure 120 to save data can be extended to improve the stability of data storage. The time for saving data is increased and decreased, which effectively improves the stability of data storage.

[0076] There are many ways to adjust the pulse clock signal. For example:

[0077] In one embodiment, the pulse clock generation module 200 may include a pulse width modulation circuit; the pulse width modulation circuit is used to modulate the duty cycle of the first level in the source clock signal to obtain a pulse clock signal.

[0078] PWM (Pulse width modulation) can adjust the duty cycle of the high level in the pulse signal. By adjusting the duty cycle, the time proportion of the high level in a single clock cycle can be achieved. Therefore, a pulse width modulation circuit can be configured in the pulse clock generation module 200 to achieve the duty cycle adjustment of the first level and obtain the required pulse clock signal. The pulse width modulation circuit can refer to the prior art and will not be expanded here.

[0079] In another embodiment, the pulse clock generation module 200 includes: an edge cutting circuit, which can also be called a signal jump circuit. The edge cutting circuit is used to generate an edge cutting signal, and perform logic processing on the source clock signal according to the edge cutting signal during the first level duration of the source clock signal, so as to generate a falling edge during the first level period of the source clock signal, and keep the low level unchanged until the next rising edge arrives, so as to obtain a pulse clock signal.

[0080] In this embodiment, the cutting edge circuit is mainly used to perform logic processing on the source clock signal to reduce the duration of the first level. For example, the cutting edge circuit generates a cutting edge signal by creating an additional delay path, and then the cutting edge signal and the source clock signal are logically processed. The logic processing can be 1 if the cutting edge signal and the source clock signal are both high levels, otherwise 0, thereby obtaining an adjusted pulse clock signal. For example, assuming that the source clock source signal is 11001100, it becomes 01100110 after delay, and the logic processing becomes 01000100, and the corresponding pulse signal is obtained in a similar manner.

[0081] For example, see Fig. 9 , Fig. 9 A pulse clock generation module 200 including a cutting edge circuit is provided in an embodiment of the present application, wherein SCLK represents a source clock signal, CKP and CKN represent opposite pulse clock signals, and RS-Latch represents a latch.

[0082] The pulse clock generation module 200 includes an input unit, an edge cutting unit, a feedback delay unit and an output unit, wherein the edge cutting unit includes a latch unit, an edge cutting subcircuit and a feedback delay unit. The source clock signal is output to the edge cutting subcircuit and the latch unit respectively through the input unit, and after the feedback delay unit and the latch unit generate the edge cutting signal, the source clock of the edge cutting subcircuit performs edge cutting to obtain a pulse clock signal, and outputs it through the output unit, wherein, since the semi-dynamic latch requires two opposite clock signals, the output unit can process the pulse clock signal to obtain two opposite pulse clock signals.

[0083] The specific principles and implementation structure of the edge cutting circuit can refer to the existing technology. The above is only an example and should not be a limitation to the present application.

[0084] Accordingly, see Figure 7 In an embodiment of the present application, the number of semi-dynamic registers 100 in the data storage structure 10 may be greater than or equal to 2, each semi-dynamic register 100 is respectively connected to a pulse clock generation module 200, and the clock ends of the first dynamic latch structure 110 and the second static latch structure 120 in each semi-dynamic register 100 are connected to the pulse clock generation module 200 corresponding to the semi-dynamic register 100.

[0085] The pulse clock generation module can thus set multiple semi-dynamic registers 100 in the data storage structure 10 to meet the needs of data storage in different scenarios.

[0086] In the embodiment of the present application, the chip area required is reduced by the first dynamic latch structure 110 in the semi-dynamic register 100, and the stability of data storage is improved by the second static latch structure 120, so that the chip area occupied by the semi-dynamic register 100 and the data storage structure 10 and the data storage stability can have a better effect, meeting the use requirements of more scenarios. And through the pulse clock generation module 200, the influence of leakage on data storage is further reduced, and the stability of data storage is improved.

[0087] Based on the same concept, an embodiment of the present application further provides a chip, which may include the data storage structure 10 provided in any of the above embodiments.

[0088] The chip can be a data processing core of a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an AI (Artificial Intelligence), etc. It can also be a chip used in some scenarios such as large-scale data computing.

[0089] Based on the same concept, the present application may also provide an electronic device, which may include the chip provided in the above embodiment. The electronic device may be a computer, a server or other device with a processing core.

[0090] The technical features of the above embodiments can be freely combined without conflict, and the embodiments obtained by the combination are included in the protection scope of this application.

[0091] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0092] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the article or device including the element.

Claims

1. A data storage structure, characterized in that: include: A semi-dynamic register, comprising a first dynamic latch structure and a second static latch structure, wherein the first dynamic latch structure and the second static latch structure are data-connected; The first dynamic latch structure stores charge based on parasitic capacitance at an electrode node; The second static latch structure includes a data transmission path and a feedback loop; the second static latch structure stores data based on the feedback loop; The first dynamic latch structure occupies a smaller chip area than the second static latch structure.

2. The data storage structure according to claim 1, characterized in that: The data storage structure also includes: A pulse clock generation module, used for connecting with a clock source; The pulse clock generation module is used to receive the source clock signal output by the clock source, and adjust the source clock signal to obtain a pulse clock signal; the pulse clock signal includes a first level and a second level; the first level is less than half of the signal period of the source clock signal and greater than the minimum pulse width condition for storing data in the first dynamic latch structure; The pulse clock generation module is also connected to the clock end of the first dynamic latch structure and the clock end of the second static latch structure respectively, so as to output the pulse clock signal to the first dynamic latch structure and the second static latch structure; The first level is used to make the electrode node of the first dynamic latch structure be in a state of storing data; the second level is used to make the second static latch structure temporarily store data.

3. The data storage structure according to claim 2, characterized in that: The pulse clock generation module includes a pulse width modulation circuit; The pulse width modulation circuit is used to modulate the duty cycle of the first level in the source clock signal to obtain the pulse clock signal.

4. The data storage structure according to claim 2, characterized in that: The pulse clock generation module comprises: an edge cutting circuit; The cutting edge circuit is used to generate a cutting edge signal, and perform logic processing on the source clock signal according to the cutting edge signal during the first level duration of the source clock signal to generate a falling edge during the first level period of the source clock signal to obtain the pulse clock signal.

5. The data storage structure according to claim 1, characterized in that: A data output terminal of the first dynamic latch structure is connected to a data input terminal of the second static latch structure; Alternatively, the data input terminal of the first dynamic latch structure is connected to the data output terminal of the second static latch structure.

6. The data storage structure according to any one of claims 1 to 5, characterized in that: The first dynamic latch structure includes a transmission gate; the transmission gate includes a first NMOS and a first PMOS; the gates of the first NMOS and the first PMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the sources of the first NMOS and the first PMOS are connected to the port of input data, and the drains of the first NMOS and the first PMOS are used to output data.

7. The data storage structure according to any one of claims 1 to 5, characterized in that: The second static latch structure includes a transmission unit and a feedback loop, wherein the transmission unit includes a second PMOS, a third PMOS, a third NMOS, and a second NMOS; The source of the second PMOS is connected to a power supply, the source of the second NMOS is grounded, the drain of the second PMOS is connected to the source of the third PMOS, the drain of the third PMOS is connected to the drain of the third NMOS, and the source of the third NMOS is connected to the drain of the second NMOS; The second NMOS and the gate of the second NMOS are used for inputting data; The gates of the third PMOS and the third NMOS are respectively connected to different clock terminals, and the different clock terminals are used to output opposite clock signals; The feedback loop includes: a fifth PMOS, a sixth PMOS, a seventh PMOS, a fifth NMOS, a sixth NMOS and a seventh NMOS; The gates of the fifth NMOS and the fifth PMOS are connected to the drain of the third PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth PMOS is connected to a power supply; and the source of the fifth NMOS is grounded; The drain of each device in the sixth PMOS, the seventh PMOS, the seventh NMOS and the sixth NMOS is connected to the source of the next device; the source of the sixth PMOS is connected to the power supply; the source of the sixth NMOS is grounded; the drain of the seventh PMOS and the drain of the seventh NMOS are connected to the drain of the third PMOS; The sixth PMOS and the third NMOS are connected to the same clock terminal; the sixth NMOS and the third PMOS are connected to the same clock terminal.

8. The data storage structure according to any one of claims 1 to 5, characterized in that: The second static latch structure includes a transmission unit and a feedback loop, wherein the transmission unit includes a tenth PMOS, an eleventh PMOS, a tenth NMOS, and an eleventh NMOS; The source of the tenth PMOS is connected to a power supply, and the source of the tenth NMOS is grounded; the drain of the tenth PMOS is connected to the source of the eleventh PMOS, the drain of the eleventh PMOS is connected to the drain of the eleventh NMOS, and the drain of the tenth NMOS is connected to the source of the eleventh NMOS; The gates of the eleventh PMOS and the eleventh NMOS are used for inputting data; The gates of the tenth PMOS and the tenth NMOS are respectively connected to different clock terminals, and the different clock terminals are used to output opposite clock signals; The feedback loop includes: a fifth PMOS, a sixth PMOS, a seventh PMOS, a fifth NMOS, a sixth NMOS and a seventh NMOS; The gates of the fifth NMOS and the fifth PMOS are connected to the drain of the eleventh PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth PMOS is connected to a power supply; and the source of the fifth NMOS is grounded; The drain of each device among the sixth PMOS, the seventh PMOS, the seventh NMOS and the sixth NMOS is connected to the source of the next device; the source of the sixth PMOS is connected to the power supply; the source of the sixth NMOS is grounded; the drain of the seventh PMOS and the drain of the seventh NMOS are connected to the drain of the eleventh PMOS; The sixth PMOS and the tenth NMOS are connected to the same clock terminal; the sixth NMOS and the tenth PMOS are connected to the same clock terminal.

9. The data storage structure according to any one of claims 1 to 5, characterized in that: The first dynamic latch structure includes a three-state gate; the three-state gate includes an eighth NMOS, a ninth NMOS, an eighth PMOS and a ninth PMOS; the gates of the ninth NMOS and the ninth PMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the gates of the eighth NMOS and the eighth PMOS are connected to the port for inputting data, and the drain of the ninth NMOS is connected to the drain of the ninth PMOS for outputting data; the drain of the eighth PMOS is connected to the source of the ninth PMOS, and the source of the ninth NMOS is connected to the drain of the eighth NMOS; the source of the eighth PMOS is connected to a power supply; and the source of the eighth NMOS is grounded.

10. A chip, characterized in that: include: A data storage structure as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: Comprising the chip as claimed in claim 10.

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