Semiconductor device structure

Abstract

A semiconductor device structure is provided. In some embodiments, a semiconductor device structure includes an interconnect structure, a plurality of active devices, a first substrate layer, and a cooling substrate layer. A plurality of active devices disposed over the interconnect structure, wherein the first substrate layer includes a semiconductor material having a first thermal conductivity; the first substrate layer is arranged on the interconnection structure; a cooling substrate layer is disposed over and in contact with the entire top surface of the first substrate layer, where the cooling substrate layer includes a material having a second thermal conductivity greater than the first thermal conductivity.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device structure, and more particularly to a semiconductor device structure having a cooling substrate layer. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. During the evolution of integrated circuits, functional density (that is, the number of interconnected devices per chip area) has generally increased while geometry size (that is, the smallest component (or line) that can be produced using a process) has decreased. This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. This miniaturization also increases the complexity of manufacturing integrated circuits.

[0003] Whenever an integrated circuit operates, energy is lost as current passes through impedances (e.g., components, interconnects, wiring, or redistribution layers). This energy loss manifests itself in the form of heat. As the gates of semiconductor device components shrink to the nanometer scale, millions of gates are formed on a single die, forming billions of transistors. While each new generation of smaller and faster devices provides more components to work with, these devices generate more heat in the same component footprint. Utility Model Content

[0004] The present disclosure aims to provide a semiconductor device structure to solve at least one of the above problems.

[0005] The disclosed embodiment provides a method for forming a semiconductor device structure, comprising: depositing an etch stop layer on a substrate; depositing a first substrate layer on the etch stop layer; forming a plurality of active devices on the first substrate layer; forming an interconnect structure on the active devices; flipping the substrate; removing the substrate; removing the etch stop layer to expose the first substrate layer; and forming a cooling substrate layer on the exposed first substrate layer, wherein the thermal conductivity of the cooling substrate layer is substantially greater than the thermal conductivity of the substrate.

[0006] The presently disclosed embodiment provides a method for forming a semiconductor device structure, comprising: depositing an etch stop layer on a substrate, wherein the substrate comprises a first semiconductor material, and the etch stop layer comprises a second semiconductor material different from the first semiconductor material; depositing a first substrate layer on the etch stop layer, wherein the first substrate layer comprises the first semiconductor material; forming a plurality of active devices on the first substrate layer; flipping the substrate; removing the substrate; removing the etch stop layer; depositing a cooling substrate layer on the first substrate layer, wherein the cooling substrate layer comprises a material different from the first semiconductor material; and depositing a second substrate layer on the cooling substrate layer, wherein the second substrate layer comprises the first semiconductor material.

[0007] An embodiment of the present disclosure provides a semiconductor device structure, comprising: an interconnect structure; a plurality of active devices disposed on the interconnect structure; a first substrate layer disposed on the interconnect structure, wherein the first substrate layer comprises a semiconductor material having a first thermal conductivity; and a cooling substrate layer disposed on the entire top surface of the first substrate layer and in contact with the entire top surface of the first substrate layer, wherein the cooling substrate layer comprises a material having a second thermal conductivity, the second thermal conductivity being greater than the first thermal conductivity.

[0008] According to one embodiment of the present disclosure, a second substrate layer is further included, which is disposed on an entire top surface of the cooling substrate layer and contacts the entire top surface of the cooling substrate layer.

[0009] According to one embodiment of the present disclosure, the thickness of the cooling substrate layer is 50 μm to 200 μm.

[0010] According to one embodiment of the present disclosure, the thickness of the second substrate layer is 200 μm to 500 μm.

[0011] According to one embodiment of the present disclosure, the interconnect structure further includes a plurality of metal layers.

[0012] According to one embodiment of the present disclosure, each of the metal layers further includes: a dielectric layer; and a plurality of metal lines extending horizontally through the dielectric layer.

[0013] According to one embodiment of the present disclosure, a dielectric is further included, which encapsulates the metal layer.

[0014] According to one embodiment of the present disclosure, each of the active devices further includes: a plurality of source / drain regions; a plurality of gate stacks disposed between adjacent source / drain regions; and a plurality of channel regions disposed between adjacent source / drain regions.

[0015] According to one embodiment of the present disclosure, each of the channel regions further includes a plurality of fins, wherein at least three surfaces of each of the fins are surrounded by the gate stack.

[0016] According to one embodiment of the present disclosure, each of the gate stacks further includes a gate electrode layer disposed on the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present disclosure.

[0018] Figure 1-Figure 11 Various stages for manufacturing a wafer arrangement are shown according to an embodiment.

[0019] Fig.12 FIG. 1 is a heat dissipation comparison between a conventional chip device and a chip device with improved heat dissipation.

[0020] Fig.13A , Fig. 13B as well as Fig.14 Various types of packaging of wafer arrangements for different applications are shown.

[0021] Fig.15 A process flow is provided for a method for forming a wafer device with improved heat dissipation and improved wafer integrity during post-fab processing.

[0022] The reference numerals are as follows:

[0023] 10:Substrate

[0024] 12: Etch stop layer

[0025] 14: Substrate layer / semiconductor layer

[0026] 16: Channel Area

[0027] 18: Source / drain region

[0028] 23: Gate stack

[0029] 24: Gate spacer

[0030] 26: Gate dielectric layer

[0031] 28: Gate electrode layer

[0032] 30:CESL

[0033] 32: Conductive contact

[0034] 40: Active device

[0035] 50: Interconnection structure

[0036] 52:Metal layer

[0037] 54:ILD

[0038] 56: Contact pad

[0039] 60: Wafer carrier / bonding material

[0040] 62: Bonding / peeling layer (surface treated carrier)

[0041] 70: Cooling substrate layer

[0042] 80: Additional substrate layer / substrate layer

[0043] 100: Device chip

[0044] 104: Source / drain region

[0045] 110: Die / Chip / SoC

[0046] 110a: Chip Die / Low Power Die

[0047] 110b: Chip die / high power consumption die

[0048] 112: DRAM

[0049] 120:SRAM+IO structure

[0050] 124: Protective material / molding compound

[0051] 130:RDL

[0052] 131:Metal wiring

[0053] 132: Contact

[0054] 134:Intermediate RDL

[0055] 136:TSV

[0056] 138:TIV

[0057] 140:TIV / TMV / RDL

[0058] 142: Wiring structure

[0059] 143: Contact

[0060] 150a: First chip

[0061] 150b: Second chip

[0062] 152: Bottom grain

[0063] a, b: part

[0064] S501, S501, S502, S503, S501, S504, S505, S506, S507, S508, S509, S510, S511, S512, S513, S514: Steps DETAILED DESCRIPTION

[0065] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0066] Furthermore, spatially relative terms may be used, such as "under", "below", "lower", "above", "over", "above", "top", "higher" and the like, to facilitate description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0067] Overheating of a semiconductor device can have a variety of effects on the operation of the device. The properties of the semiconductor material itself change with temperature due to electron migration. When the temperature limit of the semiconductor material is exceeded, the performance of the device may not meet its specifications and may malfunction. When the semiconductor device is bonded to the die substrate through the redistribution layer, the integrity of the bond may be affected at high temperatures. When the device is turned on, off, or subjected to pulsed loading effects, heat stress effects may occur. The die may experience rapid changes in temperature when changing states. When a semiconductor device composed of a die is bonded to an insulating substrate connected to a copper base plate, thermal stress may distort different film layers within the semiconductor device. The various materials used to manufacture the device have different expansion rates. The material may crack or delaminate, or stress may be applied to the die due to the expansion of the packaging material. This can cause premature device failure and adversely affect reliability.

[0068] The manufacturing of semiconductor chips can be divided into three stages of process, including the front-end-of-line (FEOL) stage, the middle-of-line (MOL) stage and the back-end-of-line (BEOL) stage. FEOL covers the process of the active part of the chip, that is, the transistors are usually formed at the bottom of the chip. The transistor acts as an electrical switch and operates using a gate, a source and a drain. The current in the conductive channel between the source and the drain is turned on and off by the gate voltage control. In BEOL, the interconnect is a complex wiring scheme that distributes clock pulses or other signals, forms interconnects to provide power and ground and transmit electrical signals from one transistor to another. The structure during BEOL is organized by different metal layers, local, intermediate, semi-global and global wires. Each of these metal layers contains metal wires and dielectric layers located in a horizontal plane. The metal wires of different metal layers are vertically interconnected through via structures. FEOL and BEOL are connected together by MOL. The structures formed in the MOL may be made of metal structures to serve as contacts to the source, drain, and gate of the transistor.

[0069] According to some embodiments, a semiconductor chip is formed using a substrate that provides more efficient heat dissipation for the heat generated by the transistors. During the FEOL stage, the substrate is provided and processed to form various devices thereon. After the BEOL stage, and before the semiconductor chip is packaged, the substrate is further processed. Figures 1 to 12 A substrate structure with improved heat dissipation is described in detail.

[0070] exist Figure 1 In the embodiment, a substrate 10 is provided. The substrate 10 includes a single crystal semiconductor layer at least on the surface of the substrate 10. The substrate 10 may include a single crystal semiconductor material, such as but not limited to silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium arsenide antimony, indium phosphide. In this embodiment, the substrate 10 is made of silicon. In some embodiments, the substrate 10 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one embodiment, the insulating layer is an oxide.

[0071] exist Figure 2In the embodiment of the present invention, an etch stop layer 12 is formed on the substrate 10. When the substrate 10 is made of silicon, a material having a different etching rate to silicon, such as silicon germanium, is selected to form the etch stop layer 12. The etch stop layer 12 can be formed by using any suitable process, such as chemical vapor deposition (CVD), atmospheric pressure chemical vapor deposition (APCVD), or molecular beam epitaxy (MBE). In some embodiments, silicon germanium can be epitaxially grown on the silicon substrate 10 as the etch stop layer 12.

[0072] exist Figure 3 In the embodiment, substrate layer 14 is formed on etching stop layer 12. Substrate layer 14 may include a single crystal semiconductor layer located at least on the surface of etching stop layer. Substrate layer 14 may include single crystal semiconductor material, such as but not limited to silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, indium phosphide. In this embodiment, substrate layer 14 is made of silicon. Substrate layer 14 may be made of silicon formed by CVD, APCVD, MBE or any other suitable process. According to some embodiments, silicon substrate layer 14 may be epitaxially grown on etching stop layer 12 made of silicon germanium. One or more buffer layers (not shown) may be formed on the surface of substrate layer 14. Buffer layers may be used to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain (S / D) region to be grown on substrate layer 14. The buffer layer may be formed of epitaxially grown single crystal semiconductor materials such as, but not limited to, silicon, germanium, germanium tin, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium arsenide antimony, gallium nitride, indium phosphide. In one embodiment, the substrate layer 14 includes a silicon germanium buffer layer epitaxially grown on the silicon substrate layer 14. The germanium concentration of the silicon germanium buffer layer may increase from 30 atomic percent germanium in the bottom buffer layer to 70 atomic percent germanium in the top buffer layer. The substrate layer 14 may include various regions suitably doped with impurities (e.g., p-type or n-type impurities). For example, for an n-type field effect transistor (NFET), the dopant is boron, and for a p-type field effect transistor (PFET), the dopant is phosphorus.

[0073] Various elements and devices may be formed on the stack of substrate 10, etch stop layer 12, and substrate layer 14 during the FEOL stage. For example, semiconductor devices may include both active and passive devices formed on substrate layer 14, such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. In some embodiments, active devices include transistors, such as planar field effect transistors, fin field effect transistors (FinFETs), nanostructured field effect transistors, or other suitable transistors. Nanostructured field effect transistors may include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor with a gate electrode surrounding the channel. Examples of devices formed between substrate layer 14 and the interconnect structure to be formed during the BEOL stage may be as follows: Figure 4 The fin field effect transistor shown in FIG. 1 may include source / drain regions 18 and a gate stack 23 disposed between adjacent source / drain regions 18 . A channel region 16 is formed between adjacent source / drain regions 18 .

[0074] The source / drain region 18 may include a semiconductor material such as silicon or germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or other suitable semiconductor materials. Exemplary source / drain regions 18 may include, but are not limited to, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, gallium arsenide phosphide, silicon phosphide, indium arsenide, aluminum arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum phosphide, gallium phosphide, or the like. The source / drain region 18 may include a p-type dopant such as boron; an n-type dopant such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. The source / drain region 104 may be formed by an epitaxial growth method using CVD, atomic layer deposition (ALD), or MBE. In the present disclosure, source region and drain region may be used interchangeably, and the structures of the two are substantially the same. In addition, the source / drain region may refer to a source or a drain, individually or collectively depending on the context. The channel region 16 may include one or more semiconductor materials, such as silicon, germanium, germanium tin, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium arsenide antimony, gallium nitride, gallium phosphide, indium phosphide. In some embodiments, the channel region 16 includes the same semiconductor material as the substrate layer 14. In some embodiments, the device is a fin field effect transistor, and the channel region 16 is a plurality of fins, each of which has at least three surfaces surrounded by the gate stack 23. In some other embodiments, the device is a nanosheet transistor, and the channel region 16 includes two or more nanosheets surrounded by the gate stack 23.

[0075] Each gate stack 23 includes a gate electrode layer 28 disposed on the channel region 16 or partially / completely surrounding the channel region 16. The gate electrode layer 28 may be a metal-containing material, such as tungsten, cobalt, aluminum, ruthenium, copper, multiple layers thereof, or the like, and may be deposited by ALD, plasma enhanced chemical vapor deposition (PECVD), molecular beam deposition (MBD), physical vapor deposition (PVD), or any suitable deposition technique. Each gate stack 23 also includes a gate dielectric layer 26, and the gate electrode layer 28 is formed on the gate dielectric layer 26. The gate dielectric layer 26 may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material; a high-k material having a dielectric constant k value higher than that of silicon dioxide; or multiple layers thereof. The gate dielectric layer 26 may be formed by any suitable method, such as CVD, PECVD, or ALD.

[0076] One or more gate spacers 24 are formed along the sidewalls of the gate stack 23 (e.g., the sidewalls of the gate dielectric layer 26). The gate spacers 24 may include silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, the like, multiple layers thereof, or combinations thereof, and may be deposited by CVD, PVD, ALD, or other suitable deposition techniques. Figure 4 In the illustrated embodiment, a substrate layer 14 has been formed on the etch stop layer 12 and the substrate 10 , and a transistor device including a gate stack 23 , source / drain regions 18 and a channel region 16 is formed on the substrate layer 14 .

[0077] A contact etch stop layer (CESL) 30 is formed on the source / drain regions 18. The CESL 30 may be conformally deposited on the surface of the source / drain regions 18. The CESL 30 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, silicon carbide, or the like or a combination thereof, and may be deposited by CVD, PECVD, PVD, ALD, or any suitable deposition technique. A conductive contact 32 is disposed on the CESL 30. The conductive contact 32 may include a material having one or more of ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, or tantalum nitride, and may be formed by any suitable method, such as electro-chemical plating (ECP) or PVD.

[0078] Once a predetermined number of active devices 40 are formed, for example: Figure 4 In the semiconductor device shown in FIG. 1 and other devices, electrical contacts (not shown) of the active device 40 are formed in the MOL process. Then, BEOL is performed to form metallization, that is, Figure 5 The interconnect structure 50 is shown. As described above, the interconnect structure 50 may include a plurality of metal layers 52. Each metal layer 52 includes metal lines and dielectric layers, and the metal lines extend horizontally through the dielectric layers. Vias may be formed to interconnect the metal layers 52 in a vertical direction. The metal layers 52 are encapsulated by an interlayer dielectric (ILD) 54, and the ILD 54 is formed with contact pads 56, and the contact pads 56 are exposed to electrically connect to external devices.

[0079] like Figure 5As shown, device wafer 100 includes interconnect structures 50 formed on active devices 40, which are supported by a stack of substrate 10, etch stop layer 12, and substrate layer 14. According to one embodiment, both substrate 10 and substrate layer 14 are made of silicon, and etch stop layer 12 is made of silicon germanium. After BEOL, post-production processes include performing wafer testing, die separation, die testing, IC packaging, and final device testing.

[0080] In traditional post-production processes, device wafers are cut into individual dies prior to the IC packaging process. The need for continued size reduction of semiconductor dies or chips has created a need for new package designs that can provide greater bandwidth and a higher number of pins to interconnect these chips. In the semiconductor industry, methods have been developed to reduce the size of device wafers before performing complex back-end processes. For example, wafer-level packaging (WLP) has been developed to replace traditional die-level packaging, which cuts device wafers into individual dies prior to IC packaging. In the WLP process, the device wafer is thinned by removing a portion of the substrate before the wafer is cut into individual dies or chips.

[0081] Ultra-thin chip designs have the benefits of better heat dissipation, reduced form factor, increased performance, and reduced power consumption. However, ultra-thin chips need to be properly supported during the manufacturing process. Temporary bonding technology provides a reliable solution for handling ultra-thin chips by attaching the device chip to a stable carrier without interrupting the back-end process. In the temporary bonding process, the chip device is reversibly mounted to the carrier. In some embodiments, a glass carrier is used as a carrier to carry the device chip. The silicon substrate of the chip device supported by the glass carrier is then thinned to the desired thickness. The thinned chip device is then separated from the glass carrier by a de-bonding step, and the chip device is then cut into individual dies for individual packaging.

[0082] In addition to the thinning process, subsequent backside processes may also include performing deposition, dry etching, wet etching, electroplating, and cleaning. A carrier made of glass may not be sufficient to withstand these backside processes during the temporary bonding process and may cause damage to the device wafer. Therefore, alternative materials may be selected as carriers. In some embodiments, a carrier wafer may replace a glass carrier to mechanically support the device wafer during the backside process. The device wafer may be bonded to a carrier using bonding / debonding materials. The properties of the bonding / debonding material greatly control the stability of the entire structure during thinning and other processes.

[0083] In order to provide a more reliable support for the device wafer during the temporary bonding process, such as Figure 6 As shown, the device wafer 100 is temporarily bonded to the wafer carrier 60 and then flipped over so that the substrate 10 is on top and the interconnect structure 50 is on the bottom. The bonding / peeling layer 62 is used to bond the interconnect structure 50 to the wafer device 60. Polymer materials are generally used to form the bonding / peeling layer 62. In some embodiments, tantalum nitride, which exhibits characteristics such as high melting point, high hardness, and chemical inertness, can be used to form the bonding / peeling layer 62. Tantalum nitride can provide improved wafer integrity and reduce costs compared to polymer materials.

[0084] Semiconductor devices generate a lot of heat on the substrate, and the substrate is one of the key elements for effective heat dissipation of chip devices. Thermal conductivity κ is a temperature-dependent parameter measured in W / mK, which is the heat energy per meter per temperature difference (calculated in degrees Celsius). The thermal conductivity κ of silicon is about 150 W / mK, which is usually too low to effectively dissipate the heat energy generated by semiconductor devices carried by the substrate, especially when the device wafer contains a large number of nanoscale devices. Therefore, it is expected that materials with higher thermal conductivity κ can replace silicon to provide improved heat dissipation efficiency. Figure 7 As shown, not only a portion of the silicon substrate 10 is removed, but the substrate 10 is completely removed until the etching stop layer 12 is exposed. An etching process can be performed to remove the substrate. When the substrate 10 is made of silicon and the etching stop layer 12 is made of silicon germanium, during the etching process, the etching selectivity of silicon to silicon germanium is controlled by adjusting the appropriate etching temperature and etching pressure and selecting a suitable etchant. For example, isotropic etching using plasma based on CF4 / O2 / N2 and NF3 / O2 / N can achieve high selectivity of silicon to silicon germanium.

[0085] The etch stop layer 12 is then removed until the semiconductor layer 14 is exposed. The semiconductor layer 14 serves as an etch stop for removing the etch stop layer 12. In embodiments where the etch stop layer 12 is made of silicon germanium and the semiconductor layer 14 is made of silicon, a higher etch rate or selectivity of silicon germanium to silicon is desired as opposed to the etching step for removing the substrate 10. A wet etching process using a wet etchant such as ammonium hydroxide, tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), potassium hydroxide solution or other suitable etchants may be used to selectively etch silicon germanium over silicon. Removal of the substrate 10 and the etch stop layer 12 exposes the remaining semiconductor layer 14 in the form of a substrate mesa, and the remaining semiconductor layer 14 is located above the active device 40 of the inversely disposed wafer device 100, such as Figure 7 shown.

[0086] exist Figure 8 In the embodiment of the present invention, a cooling substrate layer 70 having sufficiently high thermal conductivity is formed on the semiconductor layer 14. In some embodiments, the cooling substrate layer 70 covers the entire top surface of the semiconductor layer 14. The cooling substrate layer 70 is made of a material having a higher thermal conductivity than silicon. In one embodiment, the cooling substrate layer 70 may be made of copper, and the thermal conductivity κ of copper is greater than about 200 W / mK, for example, about 200 W / mK to about 400 W / mK. When simulated with a central processing unit (CPU) power of 20 W, the cooling substrate layer 70 made of copper can reduce the temperature of the silicon substrate from about 62.7° C. to about 58.6° C. That is, a 6.5% heat reduction can be achieved using the copper cooling substrate layer 70. Although copper has a higher thermal conductivity than silicon, copper is easily deformed due to thermal stress, which reduces the integrity of the chip. The thickness of a conventional silicon substrate is about 400 μm to about 600 μm without affecting the integrity of the chip, while the thickness limit of the copper cooling substrate layer 70 is generally about 100 μm. Other materials with thermal conductivity between 200 W / mK and 400 W / mK, such as silicon carbide and aluminum, can be used as substitutes for copper to form the cooling substrate layer 70. The thickness of the cooling substrate layer 70 using the substitute material can be between 50 μm and 200 μm.

[0087] In addition to copper, the cooling substrate layer 70 can be formed of other high-thermal conductivity (high-κ) materials. For example, a material with a thermal conductivity κ of up to about 800W / mK or higher, or in some embodiments, a material with a thermal conductivity κ higher than 1000W / mK can be used to form the cooling substrate layer 70. High thermal conductivity materials include diamond-like carbon (DLC), cubic boron nitride (c-BN), boron arsenide, and other materials with similar physical properties. The cooling substrate layer 70 formed of these high thermal conductivity materials can be made to a thickness greater than about 200μm without affecting chip integrity. Empirical data shows that the cooling substrate layer 70 made of high thermal conductivity materials can reduce the temperature of the silicon substrate from 62.7°C to 51.4°C. That is, when simulated with a CPU power of 20W, the high thermal conductivity cooling substrate can achieve an 18% heat reduction.

[0088] Although ultra-thin wafers provide various benefits as described above, they become fragile and difficult to handle due to increased flexibility. In certain applications, it may be necessary to increase the thickness of the device wafer 100 without reducing heat dissipation. Therefore, according to some embodiments, such as Figure 8 The single film layer / single material structure of the cooling substrate layer 70 shown may be modified to a multi-layer structure to increase the overall substrate thickness. The overall substrate thickness can be customized based on the specific needs of the application. Fig. 9 As shown, the overall substrate thickness can be greater than 200 μm, for example, between about 200 μm and about 500 μm, by adding an additional substrate layer 80 on the cooling substrate layer 70 . In some embodiments, the additional substrate layer 80 contacts the entire top surface of the cooling substrate layer 70 .

[0089] In some embodiments, the cooling substrate layer 70 may be a copper cooling substrate layer, and the additional substrate layer 80 may be made of silicon. The additional substrate layer 80 may include a single crystal structure, which has a higher thermal conductivity than other forms of silicon, such as polycrystalline silicon or amorphous silicon. The additional substrate layer 80 may be formed by bonding other wafers to the cooling substrate layer 70. To bond the single crystal silicon wafer to the copper cooling substrate layer, a thin bonding film (not shown) may be used. However, when the additional substrate layer 80 is made of other forms of silicon, such as polycrystalline silicon, this bonding layer is not necessary. In operation, the additional substrate layer 80 is unlikely to cause a significant reduction in heat dissipation because most of the heat is effectively dissipated by the cooling substrate layer 70 before reaching the additional substrate layer 80. The additional substrate layer 80 relaxes the thickness limit of the single copper cooling substrate layer 70 to further ensure chip integrity without significantly affecting heat dissipation efficiency.

[0090] The additional substrate layer 80 may also be formed on the cooling substrate layer 70 made of alternative materials, such as silicon carbide and aluminum. In some embodiments, the cooling substrate layer 70 using copper, silicon carbide or aluminum may be made to a thickness between about 20 μm and about 200 μm, and the additional substrate layer 80 may be made to a thickness between about 200 μm and about 500 μm. The additional substrate layer 80 may also be formed on the cooling substrate layer 70 made of a high thermal conductivity material as described above. The increased substrate thickness may protect the chip device from mechanical or thermal stress during the packaging process. In some embodiments, the additional substrate layer 80 may be made of another high thermal conductivity material according to other embodiments. In some embodiments, the cooling substrate layer 70 and the additional substrate layer 80 have the same size as the semiconductor wafer. For example, the diameter of the cooling substrate layer 70 and the additional substrate layer 80 is about 200 mm, 300 mm, 450 mm, or any suitable number.

[0091] like Fig.10 As shown, the bonding / peeling layer 62 and the wafer carrier 60 are removed from the device wafer 100 by a peeling process. Depending on the material used to form the bonding / peeling layer 62, three main peeling modes including slide peeling, optical peeling, and mechanical peeling can be used to remove in the peeling process.

[0092] Sliding peeling takes advantage of the reversible softening properties of thermoplastic bonding materials. In this mode, the bonded structure is heated to above the softening temperature of the bonding material, and opposite shear forces are applied to the device and the device carrier to slide them apart until the structure is separated. In the optical peeling mode, a laser-sensitive material can be selected to make the bonding / peeling layer 62, and when the laser-sensitive material is exposed to laser radiation, the laser-sensitive material will ablate, that is, decompose. Mechanical peeling is sometimes called peel separation. In this mode, peeling does not refer to removing the film layer from the device wafer. Instead, it refers to separating the structure located between the bonding material 60 and the surface-treated carrier 62. The peeling process includes inducing a crack between the two film layers at the edge of the structure, and then using very small forces to propagate the crack across the interface between the entire film layers. In most cases of mechanical peeling, it is preferred to use a thermoplastic bonding material and a low-surface-energy polymeric release layer, which can be a curable or thermoplastic composition.

[0093] Can be used for Fig. 9 The bonded structure in the device wafer with multi-layer cooling substrate is shown, and the same debonding process is applied. Fig.11 The device wafer 100 with the multi-layer substrate is shown after the bonding / peeling layer 62 and the wafer carrier 60 are removed by a peeling process.

[0094] exist Fig.12 In the present invention, a wafer device having a known silicon substrate 90 is provided ( Fig.12 a) and a wafer device having a substrate of a high thermal conductivity material ( Fig.12 FIG. 4 shows a comparison of heat dissipation in FIG. 4 (a) and (b) of FIG. 4 (b). As shown in the figure, the high thermal conductivity material of the cooling substrate layer 70 enhances heat dissipation in the in-plane and out-of-plane directions. As shown in the figure, the heat generated from the active device 40 is conducted to the known silicon substrate 90 / cooling substrate layer 70. For the known silicon substrate 90, the low thermal conductivity κ of silicon cannot effectively dissipate heat. Therefore, most of the heat accumulates in the wafer device and may damage the semiconductor device. In contrast, the cooling substrate layer 70 made of high thermal conductivity material provides sufficient paths in the in-plane and out-of-plane directions. Heat can thus be dissipated from the wafer device without damaging its semiconductor device.

[0095] After the temporary bonding process, a dicing process is performed to cut the device wafer 100 into individual dies or chips 110. The individual chips can be used in various applications, for example, a CPU for a mobile device or a CPU for a computer. The integrated cooling substrate is formed independently of the subsequent packaging process. That is, the integrated cooling substrate can be used for all packaging types used in various applications.

[0096] According to some embodiments, Fig.13A as well as Fig. 13B Figure 1 shows an integrated fan-out multi-chip module (InFO MCM) in mobile applications and an InFO 3D package in mobile applications. In semiconductor packaging, "fan-out" can be broadly defined as any package with connections fanning out from the chip surface, thereby enabling more external inputs / outputs (I / Os). For example, Fig.13A As shown, the fanned-out structure includes at least a system on chip (SoC) 110 or a stack of SoC 110 and a dynamic random-access memory (DRAM) 112 arranged side by side on a redistribution layer (RDL) 130. DRAM 112 and SoC 110 are encapsulated by a protective material (e.g., molding compound) 124. SoC 110 has a substrate with a thickness of about 600 μm. The substrate may include Fig.10 The cooling substrate layer 70 shown in FIG. 1 has the same structure as or includes a multi-layer structure, for example, referring to Fig.10 as well as Fig.11 The RDL 130 is a stack of a cooling substrate layer 70 and an additional substrate layer 80. In some embodiments, the protective material 124 is in contact with the top surface and the side surface of the cooling substrate layer 70. In some embodiments, the protective material 124 is in contact with the top surface of the additional substrate layer 80, and is in contact with the side surface of the additional substrate layer 80 and the side surface of the cooling substrate layer 70. The SoC 110 and the DRAM 112 are electrically connected to the contact 132 through the metal wiring 131 formed in the RDL 130. In other words, the connection of the SoC 110 and the DRAM 112 is redistributed through the RDL 130.

[0097] like Fig. 13BAs shown, a mobile application of the InFO 3D package may include multiple dies stacked on top of an RDL 130. The top layer of the die includes a stack of four DRAMs 112 and two wafer dies, which are arranged side by side on one side of the middle RDL 134. For example, both the wafer die 110a and the wafer die 110b may include a cooling substrate layer 70 or a combination of a cooling substrate layer 70 and an additional substrate layer 80. In one embodiment, the two wafer dies may include a low-power die (LP) 110a and a high-power die (HP) 110b arranged side by side with each other. The thickness of both the low-power die 110a and the high-power die 110b may be approximately 600 μm. The bottom layer of the die may include static random-access memory (SRAM) and input / output (SRAM+IO) structures 120 between the middle RDL 134 and the bottom RDL 130. The connection between the DRAM 112 and the contact 132 located below the RDL 130 may be achieved through the formation of the middle RDL 134 and through mold vias (TMV) or through insulator vias (TIV) 140. The connection between the low power die 110a and the high power die 110b and the contact 132 may be achieved through the routing of TIV 138 and / or through silicon vias (TSV) 136. In some embodiments, after placing the DRAM 112, the low power die 110a, and the high power die 110b on a carrier wafer (not shown), an intermediate RDL 134 is formed on the DRAM 112, the low power die 110a, and the high power die 110b. Then, the SRAM+IO structure 120 is placed on the intermediate RDL 134, and the TSV 138 of the SRAM+IO structure 120 is aligned to the contact of the intermediate RDL 134. A molding compound 124 may be formed to encapsulate the SRAM+IO structure. A TIV (or TMV) 140 may be formed to extend through the molding compound 124 to provide a connection path from the DRAM 112, the low power die 110a, and the high power die 110b to the external contact 132 of the RDL 130.

[0098] According to one embodiment, Fig.14A CPU application of a small outline integrated circuit (SoIC) package is shown. In SoIC, the interaction is vertical, rather than horizontal like in 2D and 2.5D packages. SoIC, with its reduced size and increased performance, advances the field of heterogenous chiplet integration. It features ultra-high-density vertical stacking to achieve high performance, low power consumption, and minimal resistance-inductance-capacitance (RLC). SoIC integrates active and passive chips into an integrated system-on-chip (SoC), which has the same electrical characteristics as the native SoC to achieve a better form factor. This 3D integrated circuit inter-chip stacking technology allows the integration of chiplets with multiple layers, multiple chip sizes, and multiple functions.

[0099] The use of cooling substrate layer 70 or cooling substrate layer 70 together with additional substrate layer 80 (70+80) provides further scalability and reliability of wafer handling in post-production processes. Fig.14 As shown, two layers of chips can be stacked on top of RDL140. The top layer includes a first chip 150a and a second chip 150b. The first chip 150a and the second chip 150b can be chips of the same or different types with the same or different functions. The first chip 150a and / or the second chip 150b include a cooling substrate layer 70 having a thickness of approximately 400 μm, or the thickness of the cooling substrate layer 70 together with the additional substrate layer 80 is approximately 400 μm. The bottom layer may include a bottom die 152 having a function similar to or different from that of the first chip 150a and / or the second chip 150b. The connection between the bottom die 152 and the external contact 143 of the RDL140 can be achieved through the external contact pad of the bottom die 152 and the wiring structure 142 formed in the RDL. The first chip 150a and the second chip 150b can be connected to the external contact 143 by TSVs extending through the bottom die 152 and the wiring structure 142 extending through the RDL.

[0100] Fig.15Steps of a method for fabricating a semiconductor die having improved thermal characteristics and improved wafer integrity are shown. The method begins by forming a substrate stack, including providing a substrate, such as substrate 10, in step S501; forming an etch stop layer, such as etch stop layer 12, on the substrate in step S502; and forming a substrate layer, such as substrate layer 14, on the etch stop layer in step S503. Some embodiments utilize the easily controllable etch selectivity between silicon and silicon germanium and mature and cost-effective techniques for growing silicon and silicon germanium on each other to form silicon-silicon germanium-silicon as a substrate stack. It should be understood that other materials with similar physical properties can also be used to form the substrate, etch stop layer, and substrate layer of the substrate stack.

[0101] In step S504, various active and passive devices, such as active device 40, are formed on the substrate stack. In step S505, metal wiring connecting various devices is performed by MOL process, and then BEOL structure, that is, interconnection, is formed in step S506. Then in step S507, the wafer is temporarily bonded to a carrier having a bonding / peeling layer. In one embodiment, the carrier is a carrier wafer, and the bonding / peeling layer is made of tantalum nitride, which shows potential sustainability for subsequent backside processes and can be obtained at low cost. Next, in step S508, the wafer is turned over so that the substrate stack is on top and the BEOL structure is on the bottom. In step S509, wet isotropic etching is performed to remove the substrate. The etchant and etching parameters (e.g., etching temperature and etching pressure) are selected to cause high etching selectivity of the substrate to the etching stop layer. In step S510, the etching stop layer is removed with the substrate layer as an etching stop. Wet etching using an etchant is performed under predetermined etching conditions to etch the etching stop layer having high etching selectivity to the substrate layer. In step S511, a cooling substrate layer is formed on the substrate layer using a material having high thermal conductivity. The thermal conductivity of the cooling substrate layer is higher than the thermal conductivity of the removed substrate to provide efficient heat dissipation of the device produced from the device wafer. The cooling substrate layer can be a cooling substrate layer 70 or a cooling substrate layer 70 and a silicon substrate layer 80. In step S512, the device wafer is peeled off from the carrier, and then in step S513, the device wafer is cut into individual dies. The process of using the cooling substrate layer to replace the substrate and the bonding process of the device wafer are independent of the application. In step S514, the individual dies can be used for all package types in various applications, such as mobile applications and personal computer (CPU) applications.

[0102] One embodiment is a method for forming a semiconductor device structure. The method for forming a semiconductor device structure includes depositing an etch stop layer on a substrate; depositing a first substrate layer on the etch stop layer; forming a plurality of active devices on the first substrate layer; forming an interconnect structure on the active device; flipping the substrate; removing the substrate; removing the etch stop layer to expose the first substrate layer; and forming a cooling substrate layer on the exposed first substrate layer. The thermal conductivity of the cooling substrate layer is substantially greater than the thermal conductivity of the substrate. In some embodiments, the method for forming a semiconductor device structure, wherein the substrate comprises silicon, the etch stop layer comprises silicon germanium, and the first substrate layer comprises silicon. In some embodiments, the method for forming a semiconductor device structure further includes bonding the interconnect structure to a carrier using a bonding / peeling layer before the step of flipping the substrate. In some embodiments, the method for forming a semiconductor device structure, wherein the bonding / peeling layer comprises tantalum nitride. In some embodiments, the method for forming a semiconductor device structure, wherein the thermal conductivity of the cooling substrate layer is between about 200 W / mK and about 400 W / mK. In some embodiments, the method for forming a semiconductor device structure, wherein the cooling substrate layer comprises copper, silicon carbide, aluminum, diamond-like carbon, cubic boron nitride, or boron arsenide. In some embodiments, the method for forming a semiconductor device structure, wherein the thickness of the cooling substrate layer is between about 50 μm and about 200 μm. In some embodiments, the method for forming a semiconductor device structure further comprises forming a second substrate layer on the cooling substrate layer. In some embodiments, the method for forming a semiconductor device structure, wherein the second substrate layer comprises a silicon layer.

[0103] Another embodiment is a method for forming a semiconductor device structure. The method for forming a semiconductor device structure includes depositing an etch stop layer on a substrate. The substrate includes a first semiconductor material, and the etch stop layer includes a second semiconductor material different from the first semiconductor material. The method also includes depositing a first substrate layer on the etch stop layer, wherein the first substrate layer includes the first semiconductor material. The method for forming a semiconductor device structure also includes forming a plurality of active devices on the first substrate layer; flipping the substrate; removing the substrate; removing the etch stop layer; depositing a cooling substrate layer on the first substrate layer. The cooling substrate layer includes a material different from the first semiconductor material. The method for forming a semiconductor device structure also includes depositing a second substrate layer on the cooling substrate layer, wherein the second substrate layer includes the first semiconductor material. In some embodiments, the method for forming a semiconductor device structure, wherein the etch stop layer is epitaxially grown on the substrate. In some embodiments, the method for forming a semiconductor device structure, wherein the first substrate layer is epitaxially grown on the etch stop layer. In some embodiments, the method for forming a semiconductor device structure, wherein the active device includes a transistor having a source / drain region and a gate electrode layer. In some embodiments, the method for forming a semiconductor device structure, wherein the substrate is removed by a plasma etching process. In some embodiments, the method for forming a semiconductor device structure, wherein the etch stop layer is removed by a wet etching process.

[0104] Yet another embodiment is a semiconductor device structure. The semiconductor device structure includes an interconnect structure; a plurality of active devices disposed on the interconnect structure; and a first substrate layer disposed on the interconnect structure. The first substrate layer includes a semiconductor material having a first thermal conductivity. The semiconductor device structure also includes a cooling substrate layer disposed on the entire top surface of the first substrate layer and in contact with the entire top surface of the first substrate layer, and the cooling substrate layer includes a material having a second thermal conductivity, the second thermal conductivity being greater than the first thermal conductivity. In some embodiments, the semiconductor device structure also includes a second substrate layer disposed on the entire top surface of the cooling substrate layer and in contact with the entire top surface of the cooling substrate layer. In some embodiments, the semiconductor device structure, wherein the cooling substrate layer includes copper, silicon carbide, aluminum, diamond-like carbon, cubic boron nitride, or boron arsenide. In some embodiments, the semiconductor device structure, wherein the second substrate layer includes a semiconductor material. In some embodiments, the semiconductor device structure, wherein the second substrate layer includes a material having a second thermal conductivity.

[0105] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that: include: an interconnect structure; A plurality of active devices are disposed on the interconnect structure; A first substrate layer is disposed on the interconnect structure, wherein the first substrate layer comprises a semiconductor material having a first thermal conductivity; and A cooling substrate layer is disposed on and in contact with an entire top surface of the first substrate layer, wherein the cooling substrate layer comprises a material having a second thermal conductivity greater than the first thermal conductivity.

2. The semiconductor device structure according to claim 1, wherein: The invention also includes a second substrate layer which is disposed on an entire top surface of the cooling substrate layer and contacts the entire top surface of the cooling substrate layer.

3. The semiconductor device structure according to claim 1 or 2, wherein: The thickness of the cooling substrate layer is 50 μm to 200 μm.

4. The semiconductor device structure according to claim 2, wherein: The thickness of the second substrate layer is 200 μm to 500 μm.

5. The semiconductor device structure according to claim 1, wherein: The interconnect structure also includes a plurality of metal layers.

6. The semiconductor device structure according to claim 5, wherein: Each of the metal layers further comprises: a dielectric layer; and A plurality of metal lines extend horizontally through the dielectric layer.

7. The semiconductor device structure according to claim 5, wherein: A dielectric is also included, which encapsulates the metal layer.

8. The semiconductor device structure according to claim 1, wherein: Each of the active devices further comprises: multiple source / drain regions; A plurality of gate stacks are disposed between adjacent source / drain regions; and A plurality of channel regions are arranged between adjacent source / drain regions.

9. The semiconductor device structure according to claim 8, wherein: Each of the channel regions further includes a plurality of fins, wherein at least three surfaces of each of the fins are surrounded by the gate stack.

10. The semiconductor device structure according to claim 8, wherein: Each of the gate stacks further includes a gate electrode layer disposed on the channel region.

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