Low-voltage double-direct-current power supply hot backup power supply circuit

Abstract

A low-voltage double-direct-current power supply hot backup power supply circuit comprises a first backup power supply VINA, a second backup power supply VINB, a circuit output end VOUT and a grounding end GND, and further comprises a comparator U1, a first backup circuit and a second backup circuit. A backup power supply VINA and a backup power supply VINB are both connected with a power supply for supplying power in the conventional time, for example, the voltage of the backup power supply VINA and the backup power supply VINB is 24V, and in the two paths of power supplies, generally, voltage deviation exists, and the scene that the voltages of the two backup power supplies are absolutely equal almost does not exist. When the voltages of the two paths of power supplies are not equal, only the path of power supply with high voltage actually supplies power to a post-stage circuit. When one power supply is powered off or an output short-circuit fault occurs, the circuit can quickly turn off the PMOS tube of the fault power supply to prevent current from flowing to the fault power supply from the output end VOUT, and meanwhile, the other fault-free power supply quickly substitutes up to supply power to a post-stage circuit, and seamless connection is achieved.

Description

Technical Field

[0001] The utility model relates to the field of a backup power supply circuit with automatic conversion, in particular to a low-voltage dual direct current power supply hot backup power supply circuit. Background Art

[0002] In the field of online monitoring, data storage, power distribution and dispatching technology for new energy photovoltaic and energy storage systems, the reliability requirements of the measurement and control system are very high. If the measurement and control system is powered off and shut down, it may cause damage to photovoltaic and energy storage system equipment, resulting in heavy losses. At the same time, due to the power outage, the operation data, fault data, system status and other data information cannot be saved, and the equipment manufacturer cannot analyze and understand the working status of the equipment before the power outage.

[0003] In order to ensure the stable power supply of the measurement and control system, equipment manufacturers generally use two independent DC power supplies to connect to the equipment at the same time in design, forming a dual DC power backup power supply utility model. The currently existing dual DC power backup circuits: one part uses a dual DC power cold backup utility model, which is switched on and off by relays or switches. When one of the DC power supplies fails and loses power, the other DC power supply takes a long time to be put into use (usually more than 100ms). During the power switching, there is a risk of power failure in the subsequent load circuit, so it is necessary to add a large-capacity capacitor to the circuit to maintain the normal operation of the subsequent circuit. This utility model is large in size and high in cost; one part uses a dual DC power hot backup utility model, which is achieved by simply connecting diodes in series on the two DC power supply lines. This utility model is designed The design is simple and low in cost, but the diode voltage drop is high, the loss is large, and the heat dissipation is difficult, so it cannot be used in high-current power supply scenarios; some utility models use dual DC power supply hot backup, which requires the use of an ideal diode controller, and the circuit design and debugging are complex and costly; there are also some utility models that use dual DC power supply hot backup, which use PNP transistors plus resistors to control two PMOSs respectively to achieve hot backup, but the switching of the two PMOSs in this utility model has a dead zone due to the existence of the Vbe of the transistor. When the input voltage difference between the two power supplies is small, there is a risk that one power supply fails and the PMOS cannot be turned off, thereby pulling the other power supply to death. Utility Model Content

[0004] The utility model provides a low-voltage dual-DC power supply hot backup power supply circuit, which solves the technical problem of low reliability of the backup power supply circuit in the prior art.

[0005] The utility model provides a low-voltage dual DC power hot backup power supply circuit, which includes a first backup power supply VIN_A, a second backup power supply VIN_B, a circuit output terminal VOUT and a ground terminal GND, and also includes a first backup circuit and a second backup circuit; the first backup power supply VIN_A is connected to the first backup circuit; the second backup power supply VIN_B is connected to the second backup circuit;

[0006] When the first backup power source VIN_A and the second backup power source VIN_B have the same voltage and operate normally, the first backup circuit and the second backup circuit are connected in parallel to the circuit output terminal VOUT and the ground terminal GND;

[0007] When there is a voltage difference between the first backup power source VIN_A and the second backup power source VIN_B, and both the first backup power source VIN_A and the second backup power source VIN_B are operating normally, the backup circuit with a higher voltage is connected in series to the circuit output terminal VOUT and the ground terminal GND, and the circuit with a lower voltage is turned off;

[0008] When the first backup power source VIN_A works normally and the second backup power source VIN_B fails, the first backup circuit is connected in series to the circuit output terminal VOUT and the ground terminal GND, and the second backup circuit is turned off;

[0009] When the first backup power source VIN_A fails and the second backup power source VIN_B works normally, the first backup circuit is turned off, and the second backup circuit is connected in series to the circuit output terminal VOUT and the ground terminal GND.

[0010] Further optimized to further include a comparator U1; the comparator U1 is a single-chip dual-channel comparator, including a first backup circuit comparator U1_2 and a second backup circuit comparator U1_1, the power supply pin of the comparator U1 is connected to the circuit output terminal VOUT and the ground terminal GND; the reverse input terminals of the first backup circuit comparator U1_2 and the second backup circuit comparator U1_1 are respectively connected to the circuit output terminal VOUT through a resistor R13; the reverse input terminals of the first backup circuit comparator U1_2 and the second backup circuit comparator U1_1 are respectively connected to the ground terminal GND through a resistor R14; the first backup circuit is connected to the first backup circuit comparator U1_2; the second backup circuit is connected to the second backup circuit comparator U1_1;

[0011] The first backup circuit includes a first PMOS transistor Q1, a first NMOS transistor Q4, a resistor R7, a resistor R11 and a resistor R12; the drain of the first PMOS transistor Q1 is connected to the first backup power supply VIN_A; the source of the first PMOS transistor Q1 is connected to the circuit output terminal VOUT; the first backup power supply VIN_A is connected to the same-direction input terminal of the first backup circuit comparator U1_2 through the resistor R11; the same-direction input terminal of the first backup circuit comparator U1_2 is connected to the ground terminal GND through the resistor R12; the output terminal of the first backup circuit comparator U1_2 is connected to the circuit output terminal VOUT through the resistor R7, and the output terminal of the first backup circuit comparator U1_2 is connected to GND through the resistor R8; the gate of the first PMOS transistor Q1 is connected to the circuit output terminal VOUT through the series resistor R3; the gate of the first PMOS transistor Q1 is connected to the drain of the first NMOS transistor Q4 through the series resistor R2; the output terminal of the first backup circuit comparator U1_2 is connected to the gate of the first NMOS transistor Q4;

[0012] The second backup circuit includes a second PMOS transistor Q2, a second NMOS transistor Q3, a resistor R5, a resistor R9 and a resistor R10; the drain of the second PMOS transistor Q2 is connected to the backup power supply VIN_B; the source of the second PMOS transistor Q2 is connected to the circuit output terminal VOUT; the second backup power supply VIN_B is connected to the in-phase input terminal of the second backup circuit comparator U1_1 through the series resistor R9; the in-phase input terminal of the second backup circuit comparator U1_1 is connected to the ground terminal GND through the resistor R10; the gate of the second PMOS transistor Q2 is connected to the drain of the second NMOS transistor Q3 through the series resistor R1; the gate of the second PMOS transistor Q2 is connected to the circuit output terminal VOUT through the series resistor R4; the output terminal of the second backup circuit comparator U1_1 is connected to the circuit output terminal VOUT through the resistor R5, and the output terminal of the second backup circuit comparator U1_1 is connected to GND through the resistor R6; the output terminal of the second backup circuit comparator U1_1 is connected to the gate of the second NMOS transistor Q3.

[0013] Further optimization is that a resistor R3 is connected between the gate of the first PMOS tube Q1 and the circuit output terminal VOUT; a resistor R2 is connected between the gate of the first PMOS tube Q1 and the drain of the first NMOS tube Q4; the source of the first NMOS tube Q4 is connected to the ground terminal GND; a resistor R8 is connected between the output terminal of the first backup circuit comparator U1_2 and the ground terminal GND; and the source of the first NMOS tube Q4 is connected to the ground terminal GND.

[0014] Further optimization is as follows: a resistor R4 is connected between the gate of the second PMOS tube Q2 and the circuit output terminal VOUT; a resistor R1 is connected between the gate of the second PMOS tube Q2 and the drain of the second NMOS tube Q3; the source of the second NMOS tube Q3 is connected to the ground terminal GND; the output end of the second backup circuit comparator U1_1 is connected to the circuit output terminal VOUT through the resistor R5; a resistor R6 is connected between the output end of the comparator U1_1 and the ground terminal GND; the source of the second NMOS tube Q3 is connected to the ground terminal GND.

[0015] It is further optimized that the resistance accuracy of the resistor R9 , the resistor R10 , the resistor R11 , the resistor R12 , the resistor R13 and the resistor R14 is 0.1%.

[0016] It is further optimized that the resistance accuracy of the resistors R1 , R2 , R3 , R4 , R5 , R6 , R7 and R8 is 1%.

[0017] Further optimization is that the resistance values ​​of the resistors R1 , R2 , R3 and R4 ensure that the voltage between the gate and the source of the PMOS after the resistor voltage division is within the safe operating voltage of the PMOS tube.

[0018] Further optimization is that the resistance values ​​of the resistors R5 , R6 , R7 and R8 ensure that the voltage between the gate and the source of the NMOS after the resistor voltage division is within the safe operating voltage of the NMOS tube.

[0019] Further optimization is that a diode D1 is connected between the power output terminal VOUT and the ground terminal GND; the anode of the diode D1 is connected to the ground terminal GND, and the cathode is connected to the circuit output terminal VOUT.

[0020] Beneficial effects of the utility model:

[0021] The utility model provides a low-voltage dual DC power hot backup power supply circuit. When one of the power supplies is powered off or the output is short-circuited, the circuit can quickly shut down the PMOS tube of the faulty power supply to prevent current from flowing from the output terminal VOUT to the faulty power supply. At the same time, another fault-free power supply quickly substitutes to supply power to the subsequent circuit, seamlessly connecting. At the same time, since the PMOS tube of the faulty power supply is turned off, the substitute power supply will not be pulled to death by the faulty power supply, ensuring the safety of the subsequent power supply. By properly matching the resistance value in the circuit, hot backup power supply with a wide power supply range can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A circuit diagram of a low-voltage dual DC power supply hot backup power supply circuit described in the utility model; DETAILED DESCRIPTION

[0023] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0024] A low-voltage dual DC power hot backup power supply circuit comprises a first PMOS tube Q1, a second PMOS tube Q2, a first NMOS tube Q3, a second NMOS tube Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a diode D1, and a comparator U1. The comparator U1 is a single-chip dual-channel comparator, comprising two parts: a second backup circuit comparator U1_1 and a first backup circuit comparator U1_2.

[0025] The first backup power source VIN_A is connected to the drain of the first PMOS tube Q1, and the voltage V+_2 is obtained after voltage division through the resistors R11 and R12, and the divided signal is connected to the non-inverting input terminal of the first backup circuit comparator U1_2; the second backup power source VIN_B is connected to the drain of the second PMOS tube Q2, and the voltage V+_1 is obtained after voltage division through the resistors R9 and R10, and the divided signal is connected to the non-inverting input terminal of the second backup circuit comparator U1_1; the sources of the first PMOS tube Q1 and the second PMOS tube Q2 are both connected to the circuit output terminal VOUT; the gate of the first PMOS tube Q1 is connected to the circuit output terminal VOUT through the series resistor R3, and the gate of the first PMOS tube Q1 is also connected to the drain of the first NMOS tube Q4 through the series resistor R2.

[0026] The gate of the second PMOS tube Q2 is connected to the circuit output terminal VOUT through a series resistor R4, and the gate of the second PMOS tube Q2 is also connected to the drain of the second NMOS tube Q3 through a series resistor R1; the source of the second NMOS tube Q3 and the first NMOS tube Q4 are connected to the ground terminal GND; the output terminal VOUT obtains a voltage V- through a voltage division of resistors R13 and R14, and is connected to the inverting input terminal of the second backup circuit comparator U1_1 and the second backup circuit comparator U1_2; the output terminal of the second backup circuit comparator U1_1 is connected to the circuit output terminal VOUT through a resistor R5, and the output terminal of the second backup circuit comparator U1_1 is connected to the ground terminal GND through a resistor R6. The output end of the second backup circuit comparator U1_1 is directly connected to the gate of the second NMOS tube Q3; the output end of the first backup circuit comparator U1_2 is connected to the circuit output end VOUT through the resistor R7, the output end of the first backup circuit comparator U1_2 is connected to the ground terminal GND through the resistor R8, and the output end of the first backup circuit comparator U1_2 is directly connected to the gate of the first NMOS tube Q4; the anode of the diode D1 is connected to GND, and the cathode is connected to the output end VOUT of the hot backup circuit; the power supply pin VCC of the comparator U1 is connected to the circuit output end VOUT; the GND pin of the comparator U1 is connected to the ground terminal GND. The resistors R9, R10, R11, R12, R13, and R14 are required to be 0.1% precision resistors.

[0027] In this embodiment, the normal working voltage of the first backup power supply VIN_A and the second backup power supply VIN_B are both 24V, and the output current is I _P =2A, the resistance of resistors R1, R2, R3, R4, R5, R6, R7 and R8 is 10kΩ. The V sd_P =1.3V,R dson_P =65mΩ,V gs_P =-12V. V of the first NMOS tube and the second NMOS tube gs_N =12V,

[0028] R dson_N =6Ω. The supply voltage of comparator U1 is VOUT=24V. Among them, V sd_P Represents the conduction voltage drop of the body diode between the source and drain of the PMOS tube, V gs_P It indicates the actual voltage value applied between the gate and source when the PMOS tube is turned on. dson_P Indicates that the PMOS tube is at V gs_P＝ On-resistance at -12V. V gs_N Represents the actual voltage value applied between the gate and source when the NMOS tube is turned on, Rdson_N Indicates that the NMOS tube is at V gs_N =The on-resistance under the condition of 12V. Resistors R9, R10, R11, R12, R13 and R14 are 10kΩ resistors with 0.1% accuracy. V+_1 represents the voltage division value of R9 and R10 on VIN_B, which is input to the non-inverting input terminal of comparator U1_1. V+_2 represents the voltage division value of R11 and R12 on VIN_A, which is input to the non-inverting input terminal of comparator U1_2. V f =0.3V is the forward conduction voltage drop of diode D1.

[0029] In the specific practice of this embodiment, there are three normal working scenarios and one abnormal wiring scenario:

[0030] Scenario 1:

[0031] When the first backup power source VIN_A and the second backup power source VIN_B are powered on normally, ideally VIN_A = VIN_B = 24V, the body diodes of the first PMOS tube Q1 and the second PMOS tube Q2 are turned on, and the conduction voltage drops are both V sd_P =1.3V, in the initial stage of power-on, the circuit output voltage VOUT = VIN_A-V sd_P =VIN_B-V sd_P . As the circuit output voltage VOUT increases, when VOUT is greater than the minimum operating voltage of the comparator U1, the comparator U1 starts to work normally. At this time, the inverting input voltage V- of the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2 is V-=VOUT, and the non-inverting input voltage V+_1=VIN_B and V+_2=VIN_A of the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2. The non-inverting input voltage of the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2 is higher than the inverting input voltage. Both the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2 output a high level. The output voltage value of the comparator U1 is determined by the resistor R5, the resistor R6, the resistor R7, and the resistor R8. The voltage value is V gs_N =VOUT / 2, at this time, the first NMOS tube Q3 and the second NMOS tube Q4 are turned on, due to the on-resistance R dson_N =6Ω, which is negligible compared to the resistance values ​​of resistors R1, R2, R3, and R4. When the first NMOS tube Q3 and the second NMOS tube Q4 are turned on, they are equivalent to short circuits. Therefore, the V gs_P The voltage is determined by the voltage divider value of VOUT of resistors R1, R4, R2, and R3. The voltage value is V gs_P= -VOUT / 2, the first NMOS tube Q3 and the second NMOS tube Q4 are turned on, and the on-state voltage impedance is R dson_P =65mΩ. When the power supply is powered on, the output voltage VOUT = VIN_A-Rd son_P *I _P =VIN_B-R dson_P *I _P =24-0.065*2=23.87V. Compared with the dual DC power supply hot backup solution realized by a simple diode in the prior art, the voltage difference between the output voltage and the input voltage is very small, only 130mV.

[0032] When VIN_A fails and VIN_B is normal, the input voltage of VIN_A starts to drop. When the input voltage drops to slightly lower than the VOUT voltage, the comparator U1_2 outputs a low level, and the V gs_N = 0V, Q4 is turned off, and the V gs_P =0V, the first PMOS tube Q1 is turned off. At this time, whether the VIN_A power supply is powered off or the output is short-circuited, the VIN_B power supply input will not be turned off, and the fault will not spread.

[0033] When VIN_B fails and VIN_A is normal, the input voltage of VIN_B starts to drop. When the input voltage drops to slightly lower than the VOUT voltage, the second backup circuit comparator U1_1 outputs a low level, and the V gs_N = 0V, Q3 is turned off, and the V gs_P =0V, Q2 is turned off. At this time, whether the VIN_B power supply is powered off or the output is short-circuited, the VIN_A power supply input will not be turned off, and the fault will not spread.

[0034] Scenario 2:

[0035] When VIN_A and VIN_B are powered on normally, there is a voltage difference between the two power supplies under non-ideal conditions, such as VIN_A = 24V, VIN_B = 23.5V, the first PMOS tube Q1 body diode is turned on, and the conduction voltage drop is V sd_P =1.3V, in the initial stage of power-on, the circuit output voltage VOUT = VIN_A-V sd_P. As the circuit output voltage VOUT increases, when VOUT is greater than the minimum operating voltage of the comparator, the comparator starts to work normally. At this time, the inverting input voltage V- of the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2 is V-=VOUT2 / 2, and the non-inverting input voltage V+_1=VIN_B / 2 and V+_2=VIN_A / 2 of the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2. The voltage at the non-inverting input of the first backup circuit comparator U1_2 is higher than that at the inverting input, and the first backup circuit comparator U1_2 outputs a high level. The output voltage value of the first backup circuit comparator U1_2 is determined by the resistance voltage divider of resistors R7 and R8, and the voltage values ​​are both V gs_N =VOUT / 2, at this time, the first NMOS tube Q4 is turned on, due to the on-resistance Rd of the first NMOS tube Q4 son_N =6Ω, which is negligible compared to the resistance of resistors R2 and R3. When the first NMOS tube Q4 is turned on, it is equivalent to a short circuit. Therefore, the V gs_P The voltage is determined by the voltage divider value of the circuit output VOUT of resistor R2 and resistor R3, and the voltage value is V gs_P =-VOUT / 2, the first PMOS tube Q1 is turned on, and the on-resistance is R dson_P =65mΩ. After the power supply is powered on, the output voltage VOUT = VIN_A-R dson_P *I _P =24-0.065*2=23.87V. Compared with the dual DC power supply hot backup solution realized by a simple diode in the prior art, the voltage difference between the output voltage and the input voltage is very small, only 130mV. At the same time, since the voltage V+_1 of the in-phase input terminal of the second backup circuit comparator U1_1 is VIN_B / 2=11.75V, which is lower than the voltage V- of the inverting input terminal VOUT / 2=11.935V, the second backup circuit comparator U1_1 outputs a low level, the second NMOS tube Q3 is turned off, and the V gs_P =0V, the second PMOS tube Q2 is also turned off.

[0036] When VIN_A fails and VIN_B is normal, the input voltage of VIN_A starts to drop. When the input voltage drops to slightly lower than the voltage of the circuit output terminal VOUT, the second backup circuit comparator U1_2 outputs a low level, and the V gs_N =0V, the first NMOS tube Q4 is turned off, and the V gs_P=0V, the first PMOS tube Q1 is turned off. At the same time, when the VIN_A voltage drops below the VIN_B voltage, the voltage at the in-phase input terminal of the second backup circuit comparator U1_1 is higher than the voltage at the inverting input terminal, the comparator outputs a high level, the second NMOS tube Q3 is turned on, and the V gs_P The voltage is V gs_P =-12V, the second PMOS tube Q2 is turned on, and during the power switching process, the circuit output voltage VOUT will not lose power. Since the first PMOS tube Q1 corresponding to the VIN_A power supply is turned off in time, the fault will not spread.

[0037] When VIN_B fails and VIN_A is normal, the input voltage of VIN_B begins to drop. Since the voltage at the circuit output terminal VOUT is always higher than the voltage of VIN_B, the second PMOS tube Q2 always remains in the off state, while the first PMOS tube Q1 corresponding to the VIN_A power supply always remains in the on state. At this time, whether the VIN_B power supply is powered off or has an output short circuit fault, the second PMOS tube Q2 will never open, and will not pull the VIN_A power supply input to a dead end, and the fault will not spread.

[0038] Scenario 3:

[0039] When VIN_A and VIN_B are powered on normally, there is a voltage difference between the two power supplies under non-ideal conditions, such as VIN_A = 23.5V, VIN_B = 24V, the second PMOS tube Q2 body diode is turned on, and the conduction voltage drop is V sd_P =1.3V, in the initial stage of power-on, the circuit output VOUT = VIN_B-V sd_P . As the circuit output voltage VOUT increases, when the circuit output voltage VOUT is greater than the minimum operating voltage of the comparator U1, the comparator U1 starts to work normally. At this time, the inverting input voltage V- of the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2 is V-=VOUT / 2, and the non-inverting input voltage V+_1=VIN_B / 2 and V+_2=VIN_A / 2 of the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2. The voltage at the non-inverting input of the comparator U1_1 is higher than that at the inverting input, and the second backup circuit comparator U1_1 outputs a high level. The output voltage value of the second backup circuit comparator U1_1 is determined by the voltage divider of the resistors R5 and R6, and the voltage value is V gs_N =VOUT / 2, at this time, the second NMOS tube Q3 is turned on, due to the conduction impedance R dson_N =6Ω, which is negligible compared to the resistance of resistor R1 and resistor R4. When the second NMOS transistor Q3 is turned on, it is equivalent to a short circuit. Therefore, the V gs_PThe voltage is determined by the voltage divider value of the circuit output VOUT of resistor R1 and resistor R4, and the voltage value is V gs_P =-VOUT / 2, the second PMOS tube Q2 is turned on, and the on-state voltage impedance is R dson_P =65mΩ. After the power supply is powered on, the circuit output voltage VOUT = VIN_A-R dson_P *I _P =24-0.065*2=23.87V. Compared with the dual DC power supply hot backup solution realized by a simple diode in the prior art, the voltage difference between the output voltage and the input voltage is very small, only 130mV. At the same time, since the voltage V+_2=VIN_A / 2=11.75V of the in-phase input terminal of the first backup circuit comparator U1_2 is lower than the voltage V-=VOUT / 2=11.935V of the inverting input terminal, the first backup circuit comparator U1_2 outputs a low level, the first NMOS tube Q4 is turned off, and the V gs_P =0V, the first PMOS tube Q1 is also turned off.

[0040] When VIN_A is normal and VIN_B is faulty, the input voltage of VIN_B starts to drop. When the input voltage drops to slightly lower than the voltage at the circuit output terminal VOUT, the second backup circuit comparator U1_1 outputs a low level, and the V gs_N =0V, the second NMOS tube Q3 is turned off, and the V gs_P =0V, the second PMOS tube Q2 is turned off. At the same time, when the VIN_B voltage drops below the VIN_A voltage, the voltage at the non-inverting input terminal of the first backup circuit comparator U1_2 is higher than the voltage at the inverting input terminal, the second backup circuit comparator U1_1 outputs a high level, the first NMOS tube Q4 is turned on, and the V gs_P The voltage is V gs_P =-12V, the first PMOS tube Q1 is turned on, and during the power switching process, the circuit output voltage VOUT will not lose power. Since the PMOS corresponding to the VIN_A power supply is turned off in time, the fault will not spread.

[0041] When VIN_A fails and VIN_B is normal, the input voltage of VIN_A starts to drop. Since the VOUT voltage is always higher than the VIN_A voltage, the first PMOS tube Q1 always remains in the off state, while the second PMOS tube Q2 corresponding to the VIN_B power supply always remains in the on state. At this time, whether the VIN_A power supply is powered off or has an output short circuit fault, the first PMOS tube Q1 will never open, and the VIN_A power supply input will not be pulled to a dead end, and the fault will not spread.

[0042] Abnormal wiring scenario:

[0043] When the VIN_A power supply is positively connected and VIN_B is reversely connected, the first PMOS tube Q1 is turned on because the voltage at the non-inverting input terminal of the first backup circuit comparator U1_2 is greater than the voltage at the inverting input terminal. At the same time, the second PMOS tube Q2 is turned off because its input voltage VIN_B is lower than the GND voltage and the voltage at the non-inverting input terminal of the second backup circuit comparator U1_1 is less than the voltage at the inverting input terminal.

[0044] When the VIN_A power supply is reversely connected and VIN_B is forwardly connected, the voltage at the non-inverting input terminal of the second backup circuit comparator U1_1 is greater than the voltage at the inverting input terminal, and the second PMOS tube Q2 is turned on. At the same time, the first PMOS tube Q1, because its input voltage VIN_A is lower than the voltage at the ground terminal GND, the voltage at the non-inverting input terminal of the first backup circuit comparator U1_2 is less than the voltage at the inverting input terminal, and the first PMOS tube Q1 is turned off.

[0045] When the power supply VIN_A and the power supply VIN_B are both reversely connected, the second backup circuit comparator U1_1 and the first backup circuit comparator U1_2 do not work due to normal power supply. Due to the existence of diode D1, the power supply voltage of comparator U1, the V gs_P The voltage is clamped below 0.3V, which can ensure that the first PMOS tube Q1 and the second PMOS tube Q2 will not be turned on, play an anti-reverse role, and protect the comparator and subsequent electrical equipment from being damaged by reverse voltage.

[0046] During normal operation, two power supplies are supplied at the same time or one of them is supplied. When one of the power supplies fails, the hot backup circuit can switch to the other power supply. The switching time is in the microsecond level. During the switching process, the output port VOUT will not lose power, and the current will not flow back from the output port to the faulty power port, which can effectively ensure the power supply safety of the electrical equipment. Since the devices used in the circuit are all cheap devices, except for the PMOS devices used in all hot backup circuits, the total cost of the remaining devices is less than 1 yuan.

Claims

1. A low-voltage dual DC power hot backup power supply circuit, comprising a first backup power supply VIN_A, a second backup power supply VIN_B, a circuit output terminal VOUT and a ground terminal GND, characterized in that: It also includes a first backup circuit and a second backup circuit; the first backup power source VIN_A is connected to the first backup circuit; the second backup power source VIN_B is connected to the second backup circuit; When the first backup power source VIN_A and the second backup power source VIN_B have the same voltage and operate normally, the first backup circuit and the second backup circuit are connected in parallel to the circuit output terminal VOUT and the ground terminal GND; When there is a voltage difference between the first backup power source VIN_A and the second backup power source VIN_B, and both the first backup power source VIN_A and the second backup power source VIN_B are operating normally, the backup circuit with a higher voltage is connected in series to the circuit output terminal VOUT and the ground terminal GND, and the circuit with a lower voltage is turned off; When the first backup power source VIN_A works normally and the second backup power source VIN_B fails, the first backup circuit is connected in series to the circuit output terminal VOUT and the ground terminal GND, and the second backup circuit is turned off; When the first backup power source VIN_A fails and the second backup power source VIN_B works normally, the first backup circuit is turned off, and the second backup circuit is connected in series to the circuit output terminal VOUT and the ground terminal GND.

2. A low voltage dual DC power supply hot backup power supply circuit according to claim 1, characterized in that: It also includes a comparator U1; the comparator U1 is a single-chip dual-channel comparator, including a first backup circuit comparator U1_2 and a second backup circuit comparator U1_1, the power supply pin of the comparator U1 is connected to the circuit output terminal VOUT and the ground terminal GND; the reverse input terminals of the first backup circuit comparator U1_2 and the second backup circuit comparator U1_1 are respectively connected to the circuit output terminal VOUT through a resistor R13; the reverse input terminals of the first backup circuit comparator U1_2 and the second backup circuit comparator U1_1 are respectively connected to the ground terminal GND through a resistor R14; the first backup circuit is connected to the first backup circuit comparator U1_2; the second backup circuit is connected to the second backup circuit comparator U1_1; The first backup circuit includes a first PMOS transistor Q1, a first NMOS transistor Q4, a resistor R7, a resistor R11 and a resistor R12; the drain of the first PMOS transistor Q1 is connected to the first backup power supply VIN_A; the source of the first PMOS transistor Q1 is connected to the circuit output terminal VOUT; the first backup power supply VIN_A is connected to the non-inverting input terminal of the first backup circuit comparator U1_2 through the resistor R11; the non-inverting input terminal of the first backup circuit comparator U1_2 is connected to the ground terminal GND through the resistor R12; the output terminal of the first backup circuit comparator U1_2 is connected to the circuit output terminal VOUT through the resistor R7, and the output terminal of the first backup circuit comparator U1_2 is connected to GND through the resistor R8; the gate of the first PMOS transistor Q1 is connected to the circuit output terminal VOUT through the series resistor R3; the gate of the first PMOS transistor Q1 is connected to the drain of the first NMOS transistor Q4 through the series resistor R2; the output terminal of the first backup circuit comparator U1_2 is connected to the gate of the first NMOS transistor Q4; The second backup circuit includes a second PMOS tube Q2, a second NMOS tube Q3, a resistor R5, a resistor R9 and a resistor R10; the drain of the second PMOS tube Q2 is connected to the backup power supply VIN_B; the source of the second PMOS tube Q2 is connected to the circuit output terminal VOUT; the second backup power supply VIN_B is connected to the in-phase input terminal of the second backup circuit comparator U1_1 through the series resistor R9; the in-phase input terminal of the second backup circuit comparator U1_1 is connected to the ground terminal GND through the resistor R10; the gate of the second PMOS tube Q2 is connected to the drain of the second NMOS tube Q3 through the series resistor R1; the gate of the second PMOS tube Q2 is connected to the circuit output terminal VOUT through the series resistor R4; the output terminal of the second backup circuit comparator U1_1 is connected to the circuit output terminal VOUT through the resistor R5, and the output terminal of the second backup circuit comparator U1_1 is connected to GND through the resistor R6; the output terminal of the second backup circuit comparator U1_1 is connected to the gate of the second NMOS tube Q3.

3. A low voltage dual DC power supply hot backup power supply circuit according to claim 2, characterized in that: A resistor R3 is connected between the gate of the first PMOS tube Q1 and the circuit output terminal VOUT; a resistor R2 is connected between the gate of the first PMOS tube Q1 and the drain of the first NMOS tube Q4; the source of the first NMOS tube Q4 is connected to the ground terminal GND; a resistor R8 is connected between the output terminal of the first backup circuit comparator U1_2 and the ground terminal GND; the source of the first NMOS tube Q4 is connected to the ground terminal GND.

4. A low voltage dual DC power supply hot backup power supply circuit according to claim 2, characterized in that: A resistor R4 is connected between the gate of the second PMOS tube Q2 and the circuit output terminal VOUT; a resistor R1 is connected between the gate of the second PMOS tube Q2 and the drain of the second NMOS tube Q3; the source of the second NMOS tube Q3 is connected to the ground terminal GND; the output end of the second backup circuit comparator U1_1 is connected to the circuit output terminal VOUT through the resistor R5; a resistor R6 is connected between the output end of the comparator U1_1 and the ground terminal GND; the source of the second NMOS tube Q3 is connected to the ground terminal GND.

5. A low voltage dual DC power supply hot backup power supply circuit according to claim 2, characterized in that: The resistance accuracy of the resistors R9 , R10 , R11 , R12 , R13 and R14 is 0.1%.

6. The dual low voltage dual DC power supply hot backup power supply circuit according to any one of claims 2 to 4, characterized in that: The resistance accuracy of the resistors R1 , R2 , R3 , R4 , R5 , R6 , R7 and R8 is 1%.

7. A low voltage dual DC power supply hot backup power supply circuit according to claim 6, characterized in that: The resistance values ​​of the resistors R1 , R2 , R3 and R4 ensure that the voltage between the gate and the source of the PMOS after the resistor voltage division is within the safe operating voltage of the PMOS tube.

8. A low voltage dual DC power supply hot backup power supply circuit according to claim 6, characterized in that: The resistance values ​​of the resistors R5 , R6 , R7 and R8 ensure that the voltage between the gate and the source of the NMOS after the resistor voltage division is within the safe operating voltage of the NMOS tube.

9. The low-voltage dual DC power supply hot backup power supply circuit according to claim 1, characterized in that: A diode D1 is connected between the power output terminal VOUT and the ground terminal GND; the anode of the diode D1 is connected to the ground terminal GND, and the cathode is connected to the circuit output terminal VOUT.

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