Power semiconductor device

Abstract

The utility model discloses a power semiconductor device. The power semiconductor device comprises a semiconductor substrate; a plurality of trenches in the semiconductor substrate, the plurality of trenches including a first trench, a second trench and a third trench; a first shield conductor located at a lower portion of the first trench; a gate conductor on an upper portion of the first trench; a second shield conductor located at a lower portion of the second trench; a gate wiring on an upper portion of the second trench; a shield wiring in the third trench, the shield wiring electrically connected with the first shield conductor and the second shield conductor; a body region in the semiconductor substrate; the source region is located in the body region of the first region; a first contact region, a second contact region and a third contact region; a source electrode electrically connected to the source region via the first contact region; a gate electrode electrically connected to the gate wiring via a second contact region; a shield electrode electrically connected to the shield wiring via a third contact region; and the drain electrode is positioned on the surface of one side, far away from the body region, of the semiconductor substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Art

[0002] In power semiconductor devices, lower conduction loss and switching loss are important indicators for evaluating device performance. The trench process changes the channel from horizontal to vertical, eliminating the influence of the parasitic JFET resistance of the planar structure, greatly reducing the cell size. On this basis, increasing the cell density and increasing the total width of the channel per unit area can increase the channel width-to-length ratio of the device on a unit silicon wafer, thereby increasing the current, reducing the on-resistance, and optimizing related parameters, achieving the goal of having a smaller die with greater power and higher performance. Therefore, the trench process is increasingly used in new power semiconductor devices.

[0003] As the cell density increases, the inter-electrode resistance will increase, and the switching loss will increase accordingly. The gate-drain capacitance Cgd is directly related to the switching characteristics of the device. The SGT (Split Gate Trench) structure reduces the gate-drain capacitance Cgd because the gate conductor extends to the drift region and the gate conductor and the drain are separated by a thick oxide layer, thereby increasing the switching speed and reducing the switching loss. At the same time, due to the special structure of SGT, the shield conductor under the gate conductor and the source are usually connected together and grounded together, introducing a charge balance effect, so that the vertical direction of the device has a RESURF (Reduced SURface Field, reducing the surface electric field) effect, further reducing the on-resistance Rdson and reducing the conduction loss.

[0004] In the prior art, the gate conductor is higher than the substrate surface. When the trench width is reduced to a certain size, this structure will increase the difficulty of the subsequent planarization process and photolithography process, and easily cause parameter failure, resulting in low yield and reliability risks. How to reduce photolithography, reduce manufacturing costs, and optimize the structure and manufacturing process of power semiconductor devices is the content that people in this technical field need to study. Utility Model Content

[0005] In view of the above problems, the purpose of the present application is to provide a power semiconductor device to improve the reliability of the device.

[0006] According to one aspect of the present invention, a power semiconductor device is provided, comprising: a semiconductor substrate of a first doping type; a plurality of trenches located in the semiconductor substrate, the plurality of trenches comprising a first trench located in a first region, a second trench located in a second region, and a third trench located in a third region of the semiconductor substrate; a first shielding conductor located in a lower portion of the first trench, the first shielding conductor and the semiconductor substrate being isolated via a shielding dielectric layer; a gate conductor located in an upper portion of the first trench, the gate conductor and the semiconductor substrate being isolated via a gate dielectric layer, and the gate conductor and the first shielding conductor being isolated via a first insulating layer; a second shielding conductor located in a lower portion of the second trench, the second shielding conductor and the semiconductor substrate being isolated via the shielding dielectric layer; a gate wiring located in an upper portion of the second trench, the gate wiring and the semiconductor substrate being isolated via the gate dielectric layer, and the gate wiring and the second shielding conductor being isolated via a second insulating layer; a shielding wiring; line, located in the third trench, the shielding wiring is isolated from the semiconductor substrate via the shielding dielectric layer, and the shielding wiring is electrically connected to the first shielding conductor and the second shielding conductor; a body region, located in the semiconductor substrate, the body region is adjacent to the upper part of the first trench, the second trench and the third trench, and is of a second doping type, and the second doping type is opposite to the first doping type; a source region, located in the body region of the first region, the source region is of a first doping type; a first contact region, a second contact region and a third contact region, the first contact region is located in the body region and the source region of the first region, the second contact region is located in the gate wiring, and the third contact region is located in the shielding wiring; a source electrode, electrically connected to the source region via the first contact region; a gate electrode, electrically connected to the gate wiring via the second contact region; a shielding electrode, electrically connected to the shielding wiring via the third contact region; and a drain electrode, located on a side surface of the semiconductor substrate away from the body region.

[0007] Optionally, the gate dielectric layer covers the upper sidewalls of the first trench and the upper sidewalls of the second trench; the gate conductor is flush with the surface of the semiconductor substrate, and the gate wiring is flush with the surface of the semiconductor substrate.

[0008] Optionally, the gate dielectric layer covers the upper side wall of the first trench, the surface of the semiconductor substrate in the first region, the upper side wall of the second trench and the surface of the semiconductor substrate in the second region; the gate conductor is flush with the surface of the gate dielectric layer on the semiconductor substrate, and the gate wiring is flush with the surface of the gate dielectric layer on the semiconductor substrate.

[0009] Optionally, the first shielding conductor includes a first portion surrounded by the shielding dielectric layer in the first groove and a second portion higher than the shielding dielectric layer in the first groove, and the width of the second portion of the first shielding conductor is smaller than the width of the first portion of the first shielding conductor; the second shielding conductor includes a first portion surrounded by the shielding dielectric layer in the second groove and a second portion higher than the shielding dielectric layer in the second groove, and the width of the second portion of the second shielding conductor is smaller than the width of the first portion of the second shielding conductor.

[0010] Optionally, the width of the upper portion of the first groove is greater than the width of the lower portion of the first groove, and the width of the upper portion of the second groove is greater than the width of the lower portion of the second groove; or the width of the upper portion of the first groove is consistent with the width of the lower portion of the first groove, and the width of the upper portion of the second groove is consistent with the width of the lower portion of the second groove.

[0011] Optionally, the first shielding conductor is surrounded by the shielding dielectric layer in the first groove, the top of the first shielding conductor is flush with the top of the shielding dielectric layer in the first groove, and the first insulating layer is located on the top of the first shielding conductor; the second shielding conductor is surrounded by the shielding dielectric layer in the second groove, the top of the second shielding conductor is flush with the top of the shielding dielectric layer in the second groove, and the second insulating layer is located on the top of the second shielding conductor.

[0012] Optionally, a mask layer is further included, and the mask layer is located in the third region. In the third region, the mask layer covers the surface of the shielding dielectric layer above the semiconductor substrate and the surface of the shielding wiring.

[0013] Optionally, a top of the shielding conductor in the first trench is higher than a top of the shielding conductor in the second trench.

[0014] Optionally, a doped region is further provided in the semiconductor substrate of the second region, and a depth of the doped region at least reaches an extension depth of the gate dielectric layer of the sidewall of the second trench.

[0015] Optionally, it also includes an interlayer dielectric layer, which is located above the semiconductor substrate, above the gate conductor, above the gate wiring and above the shielding wiring, and the source electrode, the gate electrode and the shielding electrode respectively penetrate the interlayer dielectric layer and are electrically connected to the first contact area, the second contact area and the third contact area.

[0016] Optionally, the source electrode is located in the first region, the gate electrode is located in the second region, the shielding electrode is located in the third region, and the source electrode, the gate electrode and the shielding electrode are separated from each other.

[0017] The power semiconductor device provided by the embodiment of the utility model sets the gate wiring inside the groove. Compared with the traditional technology of setting the gate wiring above the semiconductor substrate, the core size of the power semiconductor device of this embodiment can be further compressed, the structure and manufacturing process of the power semiconductor device are optimized, the difficulty of the manufacturing process is reduced, parameter failure is reduced, the yield is improved, the reliability risk is reduced, and the process steps are saved.

[0018] Furthermore, the source electrode, the gate electrode and the shield electrode are electrically connected to the source region, the gate wiring and the shield wiring via the first contact region, the second contact region and the third contact region respectively, which can reduce the contact resistance and enhance the EAS (single pulse avalanche breakdown energy).

[0019] Furthermore, the gate wiring can be formed in the same step as the gate conductor, thereby reducing the number of photolithography steps and lowering the manufacturing cost.

[0020] Furthermore, since the gate wiring is arranged inside the groove and its top is flush with the surface of the semiconductor substrate or the surface of the gate dielectric layer on the semiconductor substrate, the depth of the contact holes of the source electrode, the gate electrode and the shielding electrode can be set to the same and can be formed through the same etching step.

[0021] In a preferred embodiment, the top of the shield conductor is oxidized to further reduce the width and height of the top of the shield conductor, increase the distance between the bottom of the gate electrode and the top of the shield conductor, avoid gate-source leakage and gate-source short circuit, and improve reliability. In a preferred embodiment, the top of the shield conductor is completely oxidized to form an insulating layer, further increasing the distance between the shield conductor and the bottom of the gate electrode.

[0022] In a preferred embodiment, during the oxidation process of the top of the shielding conductor, the first oxide layer of the trench sidewall is retained to protect the trench sidewall and prevent the size of the upper portion of the trench from being affected during the oxidation process of the top of the shielding conductor. This keeps the upper and lower widths of the trench consistent, reduces the difficulty of alignment in subsequent contact hole and other lithography processes, improves the device's withstand voltage, on-resistance and other parameter levels, and reduces reliability risks.

[0023] In a preferred embodiment, in the third region, the surface of the shielding dielectric layer on the semiconductor substrate and the surface of the shielding wiring can also be provided with a mask layer. Due to the presence of the mask layer, the shielding dielectric layer below the mask layer can be ensured to remain intact, reducing the risk of subsequent parameter abnormalities such as gate short circuits, and reducing the quality control risk caused by process fluctuations. Furthermore, the mask layer covers the shielding dielectric layer and shielding wiring in the third region, which can reduce parasitic voltage, improve withstand voltage, and prevent water vapor and enhance reliability.

[0024] In a preferred embodiment, the height of the top of the shielding conductor in the second groove is lower than the height of the top of the shielding conductor in the first groove, so that the distance between the top of the shielding conductor in the second groove and the first surface of the semiconductor substrate is further increased, thereby further increasing the distance between the top of the shielding conductor in the second groove and the bottom of the gate electrode, further avoiding gate-source leakage and gate-source short circuit, reducing parameter failures, and improving yield and reliability.

[0025] Furthermore, a doped region is formed in the semiconductor substrate in the second region, the depth of the doped region at least reaching the extension depth of the gate dielectric layer on the side wall of the second trench, and the doped region can make the gate dielectric layer on the side wall of the second trench withstand greater voltage resistance and avoid damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0027] Figure 1 A schematic cross-sectional view of a power semiconductor device according to a first embodiment of the present application is shown;

[0028] Figures 2a to 2j shows cross-sectional views of various stages in the process of preparing a power semiconductor device according to the first embodiment of the present application;

[0029] Figure 3a A schematic cross-sectional view of a power semiconductor device according to a second embodiment of the present application is shown;

[0030] Figure 3b Shows Figure 3a An enlarged schematic diagram of the internal structure of the second groove;

[0031] Figure 3c A schematic cross-sectional view of another power semiconductor device according to a second embodiment of the present application is shown;

[0032] Figure 3d Shows Figure 3c An enlarged schematic diagram of the internal structure of the second groove;

[0033] Figures 4a to 4l shows cross-sectional views of various stages in the preparation process of a power semiconductor device according to a second embodiment of the present application;

[0034] Figure 5a A schematic cross-sectional view of a power semiconductor device according to a third embodiment of the present application is shown;

[0035] Figure 5b Shows Figure 5a An enlarged schematic diagram of the internal structure of the second groove;

[0036] Figure 5c A schematic cross-sectional view showing another power semiconductor device according to a third embodiment of the present application;

[0037] Figure 5d Shows Figure 5c An enlarged schematic diagram of the internal structure of the second groove;

[0038] Figures 6a to 6l shows cross-sectional views of various stages in the preparation process of a power semiconductor device according to a third embodiment of the present application;

[0039] Figure 7a A schematic cross-sectional view of a power semiconductor device according to a fourth embodiment of the present application is shown;

[0040] Figure 7b Shows Figure 7a An enlarged schematic diagram of the internal structure of the second groove;

[0041] Figure 7c A schematic cross-sectional view of another power semiconductor device according to a fourth embodiment of the present application is shown;

[0042] Figure 7d Shows Figure 7c An enlarged schematic diagram of the internal structure of the second groove;

[0043] Figures 8a to 8k The cross-sectional views at various stages in the preparation process of the power semiconductor device according to the fourth embodiment of the present application are shown. DETAILED DESCRIPTION

[0044] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0045] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this disclosure are only for the purpose of describing specific embodiments and are not intended to limit this disclosure. The term "and / or" used in this disclosure includes any and all combinations of one or more related listed items.

[0046] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0047] Unless otherwise specified below, the various layers or regions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors, such as silicon carbide (SiC), etc., II-VI compound semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and IV semiconductors, such as silicon (Si), germanium (Ge), etc. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni 3 Si, Pt, Ru, W, and a combination of various conductive materials. The gate dielectric layer can be made of SiO 2 Or the dielectric constant is greater than SiO 2 The gate dielectric may be formed of materials such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric may be formed of materials known to those skilled in the art, and may also be formed of materials developed in the future for use as gate dielectrics.

[0048] In the present disclosure, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

[0049] The specific implementation of the present disclosure is further described in detail below in conjunction with the drawings and examples.

[0050] Figure 1FIG. 1 shows a schematic cross-sectional view of a power semiconductor device according to a first embodiment of the present application. Figure 1 As shown, the power semiconductor device includes a semiconductor substrate 201 and a first trench 220 a located in a first region z21 , a second trench 220 b located in a second region z22 , and a third trench 220 c located in a third region z23 of the semiconductor substrate 201 .

[0051] The semiconductor substrate 201 may be a silicon substrate, a germanium silicon substrate, a III-V group element compound substrate, or other semiconductor material substrates known to those skilled in the art. In this embodiment, a silicon substrate is used. More specifically, semiconductor devices such as MOS field effect transistors, IGBT insulated gate bipolar transistors, and Schottky diodes may be formed in the semiconductor substrate used in this embodiment. The semiconductor substrate 201 has a first doping type. The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. In this embodiment, the first doping type is, for example, N-type doping.

[0052] The semiconductor substrate 201 has a first surface and a second surface opposite to each other, and the first to third grooves 220a to 220c extend from the first surface of the semiconductor substrate 201 to the inside thereof, and reach a predetermined depth in the semiconductor substrate 201. The width of the first to third grooves 220a to 220c is determined according to the structure and process capability of the product, and the depth is matched according to the parameters of the product such as epitaxy, withstand voltage, doping, and gate oxide thickness. In this embodiment, the widths of the first to third grooves 220a to 220c are consistent. In one embodiment, the widths of the first to third grooves 220a to 220c are 0.1 micrometers to 5 micrometers, and the depths are 0.5 micrometers to 20 micrometers.

[0053] Furthermore, a gate conductor 224a and a shield conductor 222a (first shield conductor) are formed in the first trench 220a, a gate wiring 224b and a shield conductor 222b (second shield conductor) are formed in the second trench 220b, and a shield wiring 222c is formed in the third trench 220c.

[0054] Specifically, the first trench 220a includes a shielding dielectric layer 221 located at the bottom and lower side wall of the first trench 220a, a shielding conductor 222a located at the lower portion of the first trench 220a, a gate dielectric layer 2231 located at the upper side wall of the first trench 220a, a gate conductor 224a located at the upper portion of the first trench 220a, and a first insulating layer 2232 between the gate conductor 224a and the shielding conductor 222a. The shielding conductor 222a is isolated from the semiconductor substrate 201 via the shielding dielectric layer 221, the gate conductor 224a is isolated from the semiconductor substrate 201 via the gate dielectric layer 2231, and the shielding conductor 222a is isolated from the gate conductor 224a via the first insulating layer 2232.

[0055] In the first trench 220a, the shield conductor 222a includes a first portion surrounded by the shield dielectric layer 221 and a second portion higher than the shield dielectric layer 221. The first insulating layer 2232 covers the top and sidewalls of the second portion of the shield conductor 222a. The top of the shield conductor 222a is at a certain distance from the top of the first trench 220a. The gate conductor 224a is located at the upper portion of the first trench 220a and covers the first insulating layer 2232, and is isolated from the shield conductor 222a by the first insulating layer 2232.

[0056] The second trench 220b includes a shielding dielectric layer 221 located at the bottom and lower side wall of the second trench 220b, a shielding conductor 222b located at the lower portion of the second trench 220b, a gate dielectric layer 2231 located at the upper side wall of the second trench 220b, a gate wiring 224b located at the upper portion of the second trench 220b, and a second insulating layer 2233 between the gate wiring 224b and the shielding conductor 222a. The shielding conductor 222b is isolated from the semiconductor substrate 201 via the shielding dielectric layer 221, the gate wiring 224b is isolated from the semiconductor substrate 201 via the gate dielectric layer 2231, and the gate wiring 224b is isolated from the shielding conductor 222b via the second insulating layer 2233.

[0057] In the second trench 220b, the shield conductor 222b includes a first portion surrounded by the shield dielectric layer 221 and a second portion higher than the shield dielectric layer 221. The second insulating layer 2233 covers the top and sidewalls of the second portion of the shield conductor 222b. The top of the shield conductor 222b is at a certain distance from the top of the second trench 220b. The gate wiring 224b is located at the upper portion of the second trench 220b and covers the second insulating layer 2233, and is isolated from the shield conductor 222b by the second insulating layer 2233.

[0058] The third trench 220 c includes a shielding dielectric layer 221 located at the bottom and sidewalls of the third trench 220 c and a shielding wiring 222 c located in the third trench 220 c . The shielding wiring 222 c is isolated from the semiconductor substrate 201 via the shielding dielectric layer 221 .

[0059] The power semiconductor device includes a body region 250 of a second doping type and a source region 260 of a first doping type, wherein the second doping type is opposite to the first doping type. The body region 250 is located in the semiconductor substrate 201, extending downward from the first surface of the semiconductor substrate 201, the body region 250 is located in the first region z21, the second region z22 and the third region z23, and is adjacent to the sidewalls of the first trench 220a, the second trench 220b and the third trench 220c, respectively, and the source region 260 is located in the body region 250 of the first region z21.

[0060] The power semiconductor device includes an interlayer dielectric layer 270, a source electrode 281, a gate electrode 282, and a shielding electrode 283. The interlayer dielectric layer 270 covers the first surface of the semiconductor substrate 201. The power semiconductor device also includes first to third contact regions 271 to 273, wherein the first contact region 271 is located in the body region 250 and the source region 260 of the first region z21. The second contact region 272 is located in the gate wiring 224b, and the third contact region 273 is located in the shielding wiring 222c. The source electrode 281 penetrates the interlayer dielectric layer 270, extends to the first contact region 271 in the first region z21, and is electrically connected to the source region 260 in the first region z21 via the first contact region 271; the gate electrode 282 penetrates the interlayer dielectric layer 270, extends to the inside of the gate wiring 224b in the second region z22, and is electrically connected to the gate wiring 224b in the second region z22 via the second contact region 272; the shielding electrode 283 penetrates the interlayer dielectric layer 270, extends to the shielding wiring 222c in the third region z23, and is electrically connected to the shielding wiring 222c in the third region z23 via the third contact region 273. The first contact region 271, the second contact region 272, and the third contact region 273 can reduce the contact resistance and enhance the EAS (single pulse avalanche breakdown energy).

[0061] Although not shown, it should be known that the power semiconductor device of this embodiment further includes a drain electrode, which is located on the second surface of the semiconductor substrate 201 (the surface away from the body region 250 ).

[0062] It should be noted that although Figure 1 In the embodiment, the shielding conductors 222a, 222b and the shielding wiring 222c in different grooves are isolated from each other, and the gate conductor 224a and the gate wiring 224b are isolated from each other. However, in an actual power semiconductor device, the shielding conductors 222a, 222b and the shielding wiring 222c in the above-mentioned different grooves are connected to each other, and the gate conductor 224a and the gate wiring 224b are connected to each other.

[0063] Furthermore, in the present embodiment, the gate dielectric layer 2231 covers the upper side wall of the first trench 220a, the first surface of the semiconductor substrate 201 in the first region, the upper side wall of the second trench 220b and the first surface of the semiconductor substrate 201 in the second region; the top of the gate wiring 224b is flush with the surface of the gate dielectric layer 2231 on the semiconductor substrate 201, and the top of the gate conductor 224a is flush with the surface of the gate dielectric layer 2231 on the semiconductor substrate 201.

[0064] In other embodiments, the gate dielectric layer 2231 covers the upper sidewalls of the first trench 220a and the upper sidewalls of the second trench 220b; the top of the gate wiring 224b is flush with the first surface of the semiconductor substrate 201, and the top of the gate conductor 224a is flush with the first surface of the semiconductor substrate 201.

[0065] In this embodiment, the gate wiring is arranged inside the groove. Compared with the conventional technology of arranging the gate wiring above the semiconductor substrate, the die size of the power semiconductor device of this embodiment can be further compressed, and the top of the gate wiring is flush with the surface of the semiconductor substrate or the surface of the gate dielectric layer on the semiconductor substrate. The gate wiring can be formed in the same step as the gate conductor, reducing the number of photolithography times and reducing manufacturing costs. This embodiment optimizes the structure and manufacturing process of the power semiconductor device, reduces the difficulty of the manufacturing process, reduces parameter failure, improves the yield, reduces reliability risks, and saves process steps.

[0066] Figures 2a to 2j The cross-sectional views of various stages in the preparation process of the power semiconductor device of the first embodiment of the present application are shown. Figures 2a to 2j A method for preparing a power semiconductor device according to the first embodiment of the present application is described.

[0067] like Figure 2a As shown, first to third trenches 220 a to 220 c are formed in first to third regions z21 to z23 of the semiconductor substrate 201 , respectively.

[0068] The semiconductor substrate 201 has a first surface and a second surface relative to each other, and the first to third trenches 220a to 220c extend downward from the first surface of the semiconductor substrate 201 and reach a predetermined depth in the semiconductor substrate 201. The width of the first to third trenches 220a to 220c is determined according to the structure and process capability of the product, and the depth is matched according to parameters such as epitaxy, withstand voltage, doping, gate oxide thickness, etc. of the product. In this embodiment, the first to third trenches 220a to 220c have the same width w20.

[0069] In this embodiment, the widths of the first to third trenches 220a to 220c are all the same, which is w20, and the heights of the first to third trenches 220a to 220c are all the same, which is h20. In one embodiment, the width w20 is 0.1 micrometer to 5 micrometers, and the depth h20 is 0.5 micrometer to 20 micrometers.

[0070] like Figure 2bAs shown, a shielding dielectric layer 221 is formed on the first surface of the semiconductor substrate 201 and the inner walls of the first to third trenches 220a to 220c. After the shielding dielectric layer 221 is formed, a cavity 241 is formed in the area of ​​the first to third trenches 220a to 220c that is not filled by the shielding dielectric layer 221.

[0071] The shielding dielectric layer 221 can be made of undoped silicon dioxide, silicon nitride, silicon oxynitride, or a combination of silicon oxide, silicon nitride, silicon oxynitride, etc. The thickness of the shielding dielectric layer 221 needs to be matched with the product's epitaxy, withstand voltage, doping, trench depth, etc.

[0072] The process of forming the shielding dielectric layer 221 includes an oxidation growth process, a CVD (Chemical Vapor Deposition) process, etc., specifically including one or more combinations of LPCVD (Low Pressure Chemical Vapor Deposition) process, SACVD (Sub Atmospheric Chemical Vapor Deposition) process, HTO (High Temperature Oxidation) process, and SRO (Selective Reactive Oxidation) process.

[0073] In one embodiment, the shielding dielectric layer 221 is a silicon oxide layer, and is formed by a thermal oxidation growth process. The thickness of the shielding dielectric layer 221 is 300 angstroms to 20,000 angstroms.

[0074] like Figure 2c As shown, for example, a deposition process is used to form the first polysilicon layer 222 . The first polysilicon layer 222 is located on the shielding dielectric layer 221 and fills the cavity 241 .

[0075] In one embodiment, the first polysilicon layer 222 is made of in-situ doped polysilicon with a sheet resistance of 3 ohm to 20 ohm and a thickness of 500 angstroms to 20,000 angstroms. The deposition temperature for forming the first polysilicon layer 222 is 500° C. to 580° C.

[0076] like Figure 2d As shown, the first polysilicon layer 222 and a portion of the shielding dielectric layer 221 above the semiconductor substrate 201 are removed.

[0077] The process of removing the first polysilicon layer 222 and part of the shielding dielectric layer 221 includes a combination of one or more methods of dry etching, wet etching, and CMP (Chemical Mechanical Polishing) process. In one embodiment, the first polysilicon layer 222 and part of the shielding dielectric layer 221 are removed by using a CMP process and a dry etching process. In other embodiments, only a dry etching process may be used to remove the first polysilicon layer 222 and part of the shielding dielectric layer 221.

[0078] After removing the first polysilicon layer 222 and part of the shielding dielectric layer 221, a certain thickness of the shielding dielectric layer 221 is retained above the semiconductor substrate 201 to serve as an etching mask for removing the first polysilicon layer 222 in the first trench 220a in the subsequent step. In one embodiment, the thickness of the shielding dielectric layer 221 retained above the semiconductor substrate 201 is 100 angstroms to 2000 angstroms. After removing the first polysilicon layer 222 and part of the shielding dielectric layer 221 above the semiconductor substrate 201, the tops of the first polysilicon layer 222 and the shielding dielectric layer 221 in the first trench 220a to the third trench 220c are flush.

[0079] like Figure 2e As shown, a patterned mask layer 228 is formed on the surface of the semiconductor structure to cover the third region z23 of the semiconductor substrate 201 and expose the first region z21 and the second region z22 of the semiconductor substrate 201. In this embodiment, the mask layer 228 is, for example, a photoresist mask layer.

[0080] The exposed first polysilicon layer 222 is etched through the opening of the mask layer 228 to remove a portion of the first polysilicon layer 222 in the first trench 220a and the second trench 220b. The process of removing the first polysilicon layer 222 includes a combination of dry etching, wet etching or one or more other methods.

[0081] For the follow-up Figure 2f The shielding dielectric layer 221 in the step shown is etched to a desired depth. In this embodiment, the first polysilicon layer 222 in the first trench 220a and the second trench 220b is first etched. The etching depth h21 of the first polysilicon layer 222 needs to be determined in combination with the subsequent etching. Figure 2f The etching depth h22 of the shielding dielectric layer 221 in the step shown is determined by In one embodiment, the etching depth h21 of the first polysilicon layer 222 is 0.2 micrometers to 3 micrometers.

[0082] like Figure 2fAs shown, the shielding dielectric layer 221 exposed by etching through the opening of the mask layer 228 is continued to be removed to remove the shielding dielectric layer 221 above the semiconductor substrate 201 in the first area z21 and the second area z22 and part of the shielding dielectric layer 221 above the first trench 220a and the second trench 220b.

[0083] The process of removing part of the shielding dielectric layer 221 includes a combination of one or more methods of dry etching and wet etching. In this embodiment, for example, wet etching is used to remove the shielding dielectric layer 221. Figure 2e In the steps shown, the first polysilicon layer 222 has been etched to a certain depth to form a cavity at the top of the first trench 220a and the second trench 220b. According to the isotropic etching characteristics of wet etching, the wet etching liquid simultaneously etches the shielding dielectric layer 221 from the surface of the shielding dielectric layer 221 above the semiconductor substrate 201 and the cavity at the top of the first trench 220a and the second trench 220b in the horizontal and vertical directions, so that the shielding dielectric layer 221 on the surface of the semiconductor substrate 201 is removed to expose the surface of the semiconductor substrate 201, and at the same time, the shielding dielectric layer 221 on the top sidewalls of the first trench 220a and the second trench 220b is etched to a certain depth, so that the top sidewalls of the first trench 220a and the second trench 220b are exposed. Further, the etching depth h22 of the shielding dielectric layer 221 in the first trench 220a and the second trench 220b is, for example, 0.3 micrometers to 5 micrometers.

[0084] in, Figure 2f After the steps shown, a portion of the shielding dielectric layer 221 in the first trench 220a and the second trench 220a is removed, and the remaining shielding dielectric layer 221 covers the bottom and lower side walls of the first trench 220a and the second trench 220b, a portion of the first polysilicon layer 222 in the first trench 220a and the second trench 220b is removed, and the remaining first polysilicon layer 222 forms shielding conductors 222a and 222b, and a cavity 242a is formed in the upper part of the first trench 220a, and a cavity 242b is formed in the upper part of the second trench 220b. The shielding dielectric layer 221 and the first polysilicon layer 222 in the third groove 220c are retained, the retained shielding dielectric layer 221 covers the bottom and side walls of the third groove 220c, and covers the surface of the semiconductor substrate 201 in the third region z23, and the retained first polysilicon layer 222 forms a shielding wiring 222c, the top of which is flush with the surface of the shielding dielectric layer 221 above the semiconductor substrate 201.

[0085] Further, after the cavity 242a is formed, the shielding conductor 222a includes a first portion surrounded by the shielding dielectric layer 221 and a second portion higher than the shielding dielectric layer 221. After the cavity 242b is formed, the shielding conductor 222b includes a first portion surrounded by the shielding dielectric layer 221 and a second portion higher than the shielding dielectric layer 221.

[0086] Furthermore, after the cavity 242 a and the cavity 242 b are formed, the mask layer 228 is removed.

[0087] like Figure 2g As shown, a gate dielectric layer 2231 , a first insulating layer 2232 and a second insulating layer 2233 are formed.

[0088] In this step, for example, an oxidation growth process is used to form a gate dielectric layer 2231, a first insulating layer 2232, and a second insulating layer 2233. In the first region z21, the gate dielectric layer 2231 covers the first surface of the semiconductor substrate 201 and the sidewalls of the upper portion of the first trench 220a; the first insulating layer 2232 covers the top and exposed sidewalls of the shielding conductor 222a in the first trench 220a. In the second region z21, the gate dielectric layer 2231 covers the first surface of the semiconductor substrate 201 and the sidewalls of the upper portion of the second trench 220b, and the second insulating layer 2233 covers the top and exposed sidewalls of the shielding conductor 222b in the second trench 220b.

[0089] In this embodiment, the gate dielectric layer 2231, the first insulating layer 2232 and the second insulating layer 2233 are formed simultaneously. Due to the characteristics of polysilicon, the thickness of the first insulating layer 2232 and the second insulating layer 2233 grown on the surface of the shield conductors 222a and 222b (polysilicon) under the same conditions is thicker than the thickness of the gate dielectric layer 2231 grown on the surface of the semiconductor substrate 201 (silicon) and the sidewalls of the first trench 220a and the second trench 220b (silicon). In one embodiment, the thickness of the gate dielectric layer 2231 is 50 angstroms to 1000 angstroms.

[0090] Although not shown, it should be understood that an insulating layer is also formed on the top of the shielding wiring 222c.

[0091] like Figure 2h As shown, a gate conductor 224a and a gate wiring 224b are formed.

[0092] In this step, for example, a deposition process is used to form a second polysilicon layer, which fills the cavity 242a and the cavity 242b and covers the surface of the gate dielectric layer 2231 and the shielding dielectric layer 221 above the semiconductor substrate 201. Next, the second polysilicon layer on the surface of the gate dielectric layer 2231 and the shielding dielectric layer 221 above the semiconductor substrate 201 is removed, and the remaining second polysilicon layer in the first trench 220a forms a gate conductor 224a, and the remaining second polysilicon layer in the second trench 220b forms a gate wiring 224b. The surface of the gate conductor 224a and the gate wiring 224b is flush with the surface of the gate dielectric layer 2231.

[0093] The second polysilicon layer is made of in-situ doped polysilicon with a sheet resistance of 3 ohm to 20 ohm and a thickness of 500 angstroms to 20,000 angstroms. The deposition temperature for forming the second polysilicon layer is 500° C. to 580° C.

[0094] The process of removing the second polysilicon layer includes a combination of one or more methods of dry etching, wet etching, and CMP (Chemical Mechanical Polishing) process. In one embodiment, the second polysilicon layer is removed by using a CMP process and a dry etching process. In other embodiments, the second polysilicon layer may also be removed by only using a dry etching process.

[0095] like Figure 2i As shown, a body region 250 is formed in a semiconductor substrate 201 , and a source region 260 is formed in the body region 250 .

[0096] The process for forming the body region 250 and the source region 260 is, for example, ion implantation. Different types of doped regions are formed by selecting appropriate dopants for implantation, and then thermal annealing is performed to activate the impurities. In the ion implantation, the gate conductor 224a, the gate wiring 224b and the shield wiring 222b are used as hard masks to define the lateral positions of the body region 250 and the source region 260, thereby eliminating the need for a photoresist mask. By controlling the energy of the ion implantation, the implantation depth of the body region 250 and the source region 260 can be defined. The body region 250 is of the second doping type, and the source region 260 is of the first doping type.

[0097] like Figure 2j As shown, an interlayer dielectric layer 270 and a source electrode 281 , a gate electrode 282 and a shielding electrode 283 are formed.

[0098] In this step, an interlayer dielectric layer 270 is formed to cover the surface of the semiconductor structure. Specifically, the interlayer dielectric layer 270 covers the gate dielectric layer 2231, the shielding dielectric layer 221, and the gate conductor 224a, the gate wiring 224b, and the shielding wiring 222c in the trench on the first surface of the semiconductor substrate 201. Next, a plurality of contact holes reaching the source region 260, the gate wiring 224b, and the shielding wiring 222c are formed in the interlayer dielectric layer 270. The process for forming the contact holes is, for example, dry etching.

[0099] Next, ion implantation is performed to form first to third contact regions 271 to 273 at the bottom of the plurality of contact holes. In the ion implantation, the interlayer dielectric layer 270 is used as a hard mask to define the lateral positions of the first to third contact regions 271 to 273, thereby eliminating the need for a photoresist mask.

[0100] Next, a source electrode 281, a gate electrode 282, and a shield electrode 283 are formed. This step includes, for example, depositing a metal layer and patterning. The metal layer is, for example, composed of one selected from Ti, TiN, TiSi, W, Al, AlSi, AlSiCu, Cu, Ni, or an alloy thereof. The metal layer is patterned into a source electrode 281, a gate electrode 282, and a shield electrode 283 by etching. The source electrode 281, the gate electrode 282, and the shield electrode 283 are isolated from each other.

[0101] In the first region z21 of the semiconductor substrate 201, the source electrode 281 is electrically connected to the source region 260 via the first contact region 271. In the second region z22 of the semiconductor substrate 201, the gate electrode 282 is electrically connected to the gate wiring 224b via the second contact region 272. In the third region z23 of the semiconductor substrate 201, the shielding electrode 283 is electrically connected to the shielding wiring 222c via the third contact region 273.

[0102] Since the gate wiring 224b is arranged inside the second groove 220b and its top is flush with the surface of the gate dielectric layer 2231 above the semiconductor substrate 201, the depth of the contact holes of the source electrode 281, the gate electrode 282 and the shielding electrode 283 can be set to the same and can be formed through the same etching step.

[0103] Furthermore, according to the needs of the product, a passivation layer can be added to protect the front structure of the power semiconductor device. After a series of post-processing such as thinning, back gold, and dicing, the final structure of the device is completed.

[0104] It should be noted that although in the above-mentioned cross-sectional view, the shielding conductors 222a, 222b and the shielding wiring 222c in different grooves are isolated from each other, and the gate conductor 224a and the gate wiring 224b are isolated from each other, in an actual power semiconductor device, the shielding conductors 222a, 222b and the shielding wiring 222c in the above-mentioned different grooves can be connected to each other, and the gate conductor 224a and the gate wiring 224b can also be connected to each other.

[0105] Figure 3a A schematic cross-sectional view of a power semiconductor device according to a second embodiment of the present application is shown. Figure 3b Shows Figure 3a An enlarged schematic diagram of the internal structure of the second groove.

[0106] Different from the first embodiment, in this embodiment, the width w23 of the upper portion of the first groove 220a is greater than the width w20 of the lower portion thereof, the shielding conductor 222a in the first groove 220a includes a first portion surrounded by the shielding dielectric layer 221 and a second portion protruding from the shielding dielectric layer 221, the width w22 of the second portion of the shielding conductor 222a is less than the width w21 of the first portion thereof, and relative to the first embodiment, in this embodiment, the distance h26 between the top of the second portion of the shielding conductor 222a and the first surface of the semiconductor substrate 201 is increased, the thickness T22 of the first insulating layer 2232 at the top of the second portion of the shielding conductor 222a is increased, and the distance T23 between the top of the second portion of the shielding conductor 222a and the bottom of the contact hole is increased. The width w23 of the upper portion of the second groove 220b is greater than the width w20 of the lower portion thereof. The shielding conductor 222b in the second groove 220b includes a first portion surrounded by the shielding dielectric layer 221 and a second portion protruding from the shielding dielectric layer 221. The width w22 of the second portion of the shielding conductor 222b is less than the width w21 of the first portion thereof. In addition, relative to the first embodiment, in this embodiment, the distance h26 between the top of the second portion of the shielding conductor 222b and the first surface of the semiconductor substrate 201 is increased, the thickness T22 of the second insulating layer 2233 at the top of the second portion of the shielding conductor 222b is increased, and the distance T23 between the top of the second portion of the shielding conductor 222b and the bottom of the contact hole is increased.

[0107] In one embodiment, the distance h26 between the top of the second portion of the shielding conductor 222a and the first surface of the semiconductor substrate 201 is, for example, 0.2 microns to 3 microns; the distance between the bottom of the contact hole and the first surface of the semiconductor substrate 201 is h28, the distance T23 between the top of the second portion of the shielding conductor 222a and the bottom of the contact hole is h26-h28, and the distance T23 between the top of the second portion of the shielding conductor 222a and the bottom of the contact hole is, for example, 0.1 microns to 2.5 microns.

[0108] Specifically, the gate wiring 224b is located at the upper portion of the second trench 220b, and the depth of the upper portion of the second trench 220b (channel length of the power semiconductor device) is h24. The gate wiring 224b is isolated from the semiconductor substrate 201 via the gate dielectric layer 2231, and the thickness of the gate dielectric layer 2231 is as follows: Figure 3b In one embodiment, the thickness T21 of the gate dielectric layer 2231 is, for example, 50 angstroms to 1000 angstroms. The gate wiring 224b is isolated from the shield conductor 222b by the second insulating layer 2233. The thickness of the insulating layer 2223 is as follows: Figure 3b T22 in, usually T22>T21.

[0109] In this embodiment, due to the reduction in the width and height of the second part of the shielding conductor 222b, relative to the first embodiment, in this embodiment, the distance T23 between the bottom of the gate electrode 282 and the top of the shielding conductor 222b is increased, thereby avoiding gate-source leakage and gate-source short circuit and improving reliability.

[0110] Figure 3c A schematic cross-sectional view of another power semiconductor device according to the second embodiment of the present application is shown. Figure 3d Shows Figure 3c An enlarged schematic diagram of the internal structure of the second groove.

[0111] and Figure 3a and Figure 3b The device structure shown is different in that Figure 3c and Figure 3d In the device shown, since the width and height of the second part of the shielding conductor 222a are reduced, the second part of the shielding conductor 222a is completely oxidized to form a first insulating layer 2232, that is, the shielding conductor 222a only includes the part surrounded by the shielding dielectric layer 221, and the first insulating layer 2232 covers the shielding conductor 222a.

[0112] Similarly, in the second trench 220b, since the width and height of the second portion of the shielding conductor 222b are reduced, the second portion of the shielding conductor 222b is completely oxidized to form the second insulating layer 2233, that is, the shielding conductor 222b only includes the portion surrounded by the shielding dielectric layer 221, and the second insulating layer 2233 covers the shielding conductor 222b. Since the second portion of the shielding conductor 222b is completely replaced by the second insulating layer 2233, the distance T23 between the bottom of the gate electrode 282 and the top of the shielding conductor 222b is further increased, which can further avoid gate-source leakage and gate-source short circuit, thereby improving reliability.

[0113] Figures 4a to 4l The cross-sectional views of various stages in the preparation process of the power semiconductor device of the second embodiment of the present application are shown. Figures 4a to 4lA method for preparing a power semiconductor device according to the second embodiment of the present application is described.

[0114] in Figures 4a to 4d The steps shown are similar to those in the first embodiment. Figure 2a to Figure 2d The steps shown are the same and will not be repeated here in this embodiment.

[0115] like Figure 4e As shown, a patterned mask layer 228 is formed on the surface of the semiconductor structure to cover the third region z23 of the semiconductor substrate 201 and expose the first region z21 and the second region z22 of the semiconductor substrate 201. In this embodiment, the material of the mask layer 228 is, for example, one or a combination of multiple materials selected from silicon nitride and silicon oxynitride. In one embodiment, the thickness of the mask layer 228 is 100 angstroms to 10,000 angstroms.

[0116] The exposed first polysilicon layer 222 is etched through the opening of the mask layer 228 to remove a portion of the first polysilicon layer 222 in the first trench 220a and the second trench 220b. The process of removing the first polysilicon layer 222 includes a combination of dry etching, wet etching or one or more other methods.

[0117] For the follow-up Figure 4f The shielding dielectric layer 221 in the step shown is etched to a desired depth. In this embodiment, the first polysilicon layer 222 in the first trench 220a and the second trench 220b is first etched. The etching depth h21 of the first polysilicon layer 222 needs to be determined in combination with the subsequent etching. Figure 4f The etching depth h22 of the shielding dielectric layer 221 in the step shown is determined by In one embodiment, the etching depth h21 of the first polysilicon layer 222 is 0.2 micrometers to 3 micrometers.

[0118] like Figure 4f As shown, the shielding dielectric layer 221 exposed by etching through the opening of the mask layer 228 is continued to be removed to remove the shielding dielectric layer 221 above the semiconductor substrate 201 in the first area z21 and the second area z22 and part of the shielding dielectric layer 221 above the first trench 220a and the second trench 220b.

[0119] In this embodiment, for example, wet etching is used to remove the shielding dielectric layer 221. Figure 4eIn the steps shown, the first polysilicon layer 222 has been etched to a certain depth to form a cavity at the top of the first trench 220a and the second trench 220b. According to the isotropic etching characteristics of wet etching, the wet etching liquid simultaneously etches the shielding dielectric layer 221 from the surface of the shielding dielectric layer 221 above the semiconductor substrate 201 and the cavity at the top of the first trench 220a and the second trench 220b in the horizontal and vertical directions, so that the shielding dielectric layer 221 on the surface of the semiconductor substrate 201 is removed to expose the surface of the semiconductor substrate 201, and at the same time, the shielding dielectric layer 221 on the top sidewalls of the first trench 220a and the second trench 220b is etched to a certain depth, so that the top sidewalls of the first trench 220a and the second trench 220b are exposed. Further, the etching depth h22 of the shielding dielectric layer 221 in the first trench 220a and the second trench 220b is, for example, 0.3 micrometers to 5 micrometers.

[0120] in, Figure 4f After the steps shown, a portion of the shielding dielectric layer 221 in the first trench 220a and the second trench 220a is removed, and the remaining shielding dielectric layer 221 covers the bottom and lower side walls of the first trench 220a and the second trench 220b, a portion of the first polysilicon layer 222 in the first trench 220a and the second trench 220b is removed, and the remaining first polysilicon layer 222 forms shielding conductors 222a and 222b, and a cavity 242a is formed in the upper part of the first trench 220a, and a cavity 242b is formed in the upper part of the second trench 220b. The shielding dielectric layer 221 and the first polysilicon layer 222 in the third groove 220c are retained, the retained shielding dielectric layer 221 covers the bottom and side walls of the third groove 220c, and covers the surface of the semiconductor substrate 201 in the third region z23, and the retained first polysilicon layer 222 forms a shielding wiring 222c, the top of which is flush with the surface of the shielding dielectric layer 221 above the semiconductor substrate 201.

[0121] Further, after the cavity 242a is formed, the shielding conductor 222a includes a first portion surrounded by the shielding dielectric layer 221 and a second portion higher than the shielding dielectric layer 221. After the cavity 242b is formed, the shielding conductor 222b includes a first portion surrounded by the shielding dielectric layer 221 and a second portion higher than the shielding dielectric layer 221.

[0122] The top width w21 of the shield conductor 222a in the cavity 242a and the top width w21 of the shield conductor 222b in the cavity 242b are affected by the widths of the first trench 220a and the second trench 220b and the thickness of the shield dielectric layer 221 in the first trench 220a and the second trench 220b. In one embodiment, w21 is, for example, 500 angstroms to 20,000 angstroms.

[0123] Different from the first embodiment, in this embodiment, after the cavity 242 a and the cavity 242 b are formed, the mask layer 228 is retained.

[0124] like Figure 4g As shown, the exposed surfaces of the semiconductor substrate 201 and the exposed surfaces of the shielding conductors 222a and 222b in the first region z21 and the second region z22 are oxidized via the mask layer 228 to form an oxide layer 223a.

[0125] In this step, for example, an oxidation growth process is used to form an oxide layer 223a. In the first region z21, the oxide layer 223a covers the first surface of the semiconductor substrate 201, the sidewalls of the upper portion of the first trench 220a, and the top and exposed sidewalls of the shielding conductor 222a in the first trench 220a. In the second region z21, the oxide layer 223a covers the first surface of the semiconductor substrate 201, the sidewalls of the upper portion of the second trench 220b, and the top and exposed sidewalls of the shielding conductor 222b in the second trench 220b.

[0126] In this embodiment, due to the characteristics of polysilicon, the thickness of the oxide layer 223a grown on the surface of the shield conductors 222a, 222b (polysilicon) is thicker than the thickness of the oxide layer 223a grown on the surface of the semiconductor substrate 201 (silicon) and the sidewalls of the first trench 220a and the second trench 220b (silicon) under the same conditions. In one embodiment, the thickness of the oxide layer 223a is 50 angstroms to 1000 angstroms.

[0127] like Figure 4h As shown, the oxide layer 223a is removed, and a cavity 243a and a cavity 243b are formed in the upper portions of the first trench 220a and the second trench 220b, respectively.

[0128] Specifically, after removing the oxide layer 223a, a cavity 234a is formed at the top of the first trench 220a, and a cavity 243b is formed at the top of the second trench 220b. After removing the oxide layer 223a, the width w23 of the upper portion of the first trench 220a is greater than the width w20 of the lower portion thereof, i.e., w23>w20. Further, after removing the oxide layer 223a, the width w22 of the second portion of the shielding conductor 222a is less than the width w21 of the first portion thereof, i.e., w22<w21, and the distance h23 between the top of the shielding conductor 222a and the first surface of the semiconductor substrate 201 increases, i.e., h23>h21. The distance between the top of the shielding dielectric layer 221 in the cavity 243a and the first surface of the semiconductor substrate 201 is h24.

[0129] Similarly, after removing the oxide layer 223a, the width w23 of the upper portion of the second trench 220b is greater than the width w20 of the lower portion thereof, i.e., w23>w20. Further, after removing the oxide layer 223a, the width w22 of the second portion of the shielding conductor 222b is less than the width w21 of the first portion thereof, i.e., w22<w21, and the distance h23 between the top of the shielding conductor 222b and the first surface of the semiconductor substrate 201 increases, i.e., h23>h21. The distance between the top of the shielding dielectric layer 221 in the cavity 243b and the first surface of the semiconductor substrate 201 is h24.

[0130] Furthermore, after the cavities 243 a and 243 b are formed, the mask layer 228 is removed.

[0131] like Figure 4i As shown, a gate dielectric layer 2231 , a first insulating layer 2232 , a second insulating layer 2233 and a third insulating layer 2234 are formed.

[0132] In this step, for example, an oxidation growth process is used to form a gate dielectric layer 2231, a first insulating layer 2232, a second insulating layer 2233 and an insulating layer 2234. In the first region z21, the gate dielectric layer 2231 covers the first surface of the semiconductor substrate 201 and the sidewalls of the upper portion of the first trench 220a; the first insulating layer 2232 covers the top and exposed sidewalls of the shielding conductor 222a in the first trench 220a. In the second region z21, the gate dielectric layer 2231 covers the first surface of the semiconductor substrate 201 and the sidewalls of the upper portion of the second trench 220b, and the second insulating layer 2233 covers the top and exposed sidewalls of the shielding conductor 222b in the second trench 220b. In the third region z23, the third insulating layer 2234 covers the top of the shielding wiring 222c.

[0133] In this embodiment, the gate dielectric layer 2231, the first insulating layer 2232, the second insulating layer 2233 and the third insulating layer 2234 are formed simultaneously. Due to the characteristics of polysilicon, the thickness of the first insulating layer 2232, the second insulating layer 2233 and the third insulating layer 2234 grown on the surface of the shield conductors 222a, 222b (polysilicon) and the surface of the shield wiring 222c under the same conditions is thicker than the thickness of the gate dielectric layer 2231 on the surface of the semiconductor substrate 201 (silicon) and the sidewalls of the first trench 220a and the second trench 220b (silicon). The thickness of the first insulating layer 2232, the second insulating layer 2233 and the third insulating layer 2234 is, for example, more than twice the thickness of the gate dielectric layer 2231. In one embodiment, the thickness of the gate dielectric layer 2231 is 50 angstroms to 1000 angstroms.

[0134] In other embodiments, if the Figure 4g to Figure 4hIn the step of, since the width of the second portion of the shield conductors 222a, 222b is further reduced relative to the width of the first portion thereof, Figure 4i In the step of, the second portion of the shield conductor 222a in the first trench 220a is completely oxidized to form a first insulating layer 2232, and the second portion of the shield conductor 222b in the second trench 220b is completely oxidized to form a second insulating layer 2233. Figure 3c and Figure 3d shown.

[0135] Furthermore, if Figure 4j to Figure 4l As shown, a gate conductor 224a, a gate wiring 224b, a body region 250, a source region 260, an interlayer dielectric layer 270, a first contact region 271 to a third contact region 273, a source electrode 281, a gate electrode 282 and a shielding electrode 283 are formed. Figure 4j to Figure 4l The steps shown are similar to those in the first embodiment. Figure 2h to Figure 2j The steps shown are the same and will not be repeated here in this embodiment.

[0136] Figure 5a A schematic cross-sectional view of a power semiconductor device according to a third embodiment of the present application is shown. Figure 5b Shows Figure 5a An enlarged schematic diagram of the internal structure of the second groove. Figure 5c A schematic cross-sectional view of another power semiconductor device according to the third embodiment of the present application is shown, Figure 5d Shows Figure 5c An enlarged schematic diagram of the internal structure of the second groove.

[0137] Different from the second embodiment, in this embodiment, the upper widths of the first trench 220a and the second trench 220b maintain the design requirements and will not become wider, that is, the upper widths of the first trench 220a and the second trench 220b are consistent with the lower widths, thereby reducing the difficulty of alignment in subsequent contact hole and other lithography processes, improving the device's withstand voltage, on-resistance and other parameter levels, and reducing reliability risks.

[0138] Furthermore, in the third region z23, a mask layer 228 may be provided on the surface of the shielding dielectric layer 221 and the surface of the shielding wiring 222c on the semiconductor substrate 201. The mask layer 228 covers the shielding dielectric layer 221 and the shielding wiring 222c above the semiconductor substrate 201 in the third region z23, which can reduce parasitic voltage, improve withstand voltage, block water vapor, and enhance reliability.

[0139] Figures 6a to 6l The following is a cross-sectional view of each stage in the preparation process of the power semiconductor device of the third embodiment of the present application. Figures 6a to 6l A method for preparing a power semiconductor device according to the third embodiment of the present application is described.

[0140] in Figure 6a and Figure 6e The steps shown are similar to those in the second embodiment. Figure 4a and Figure 4e The steps shown are the same and will not be repeated here in this embodiment.

[0141] like Figure 6f As shown, the exposed shielding dielectric layer 221 is continuously etched through the opening of the mask layer 228 to remove a certain thickness of the shielding dielectric layer 221 .

[0142] Different from the second embodiment, Figure 6f In the step, a certain thickness of the shielding dielectric layer 221 is retained above the semiconductor substrate 201 and on the upper side walls of the first trench 220a and the second trench 220b. The remaining shielding dielectric layer 221 on the upper side walls of the first trench 220a and the second trench 220b protects the upper side walls of the first trench 220a and the second trench 220b to prevent the upper side walls of the first trench 220a and the second trench 220b from being oxidized and causing the width to increase during the subsequent step of oxidizing the second part of the shielding conductors 222a and 222b.

[0143] Further, after the cavity 242a is formed, the shielding conductor 222a includes a first portion surrounded by the shielding dielectric layer 221 and a second portion higher than the shielding dielectric layer 221. After the cavity 242b is formed, the shielding conductor 222b includes a first portion surrounded by the shielding dielectric layer 221 and a second portion higher than the shielding dielectric layer 221.

[0144] The top width w21 of the shield conductor 222a in the cavity 242a and the top width w21 of the shield conductor 222b in the cavity 242b are affected by the widths of the first trench 220a and the second trench 220b and the thickness of the shield dielectric layer 221 in the first trench 220a and the second trench 220b. In one embodiment, w21 is, for example, 500 angstroms to 20,000 angstroms.

[0145] Furthermore, the thickness T41 of the shielding dielectric layer 221 remaining on the first surface of the semiconductor substrate 201 and the shielding dielectric layer 221 remaining on the upper sidewalls of the first trench 220 a and the second trench 220 b is, for example, 50 angstroms to 1500 angstroms.

[0146] like Figure 6g As shown, the surfaces of the shield conductors 222a and 222b exposed in the first region z21 and the second region z22 are oxidized via the mask layer 228 to form an oxide layer 223a.

[0147] In this step, for example, an oxidation growth process is used to form the oxide layer 223a. Due to the characteristics of polysilicon, under the same conditions, the thickness of the oxide layer grown on the surface of the shielding dielectric layer 221 is much thinner than the thickness of the oxide layer 223a grown on the surface of the shielding conductors 222a and 222b, and can be ignored. In one embodiment, the thickness of the oxide layer 223a is 50 angstroms to 1000 angstroms.

[0148] Since a certain thickness of the shielding dielectric layer 221 is retained on the upper side walls of the first trench 220a and the second trench 220b, according to the oxide layer growth principle, in this step, the oxide layer growth of the upper side walls of the first trench 220a and the second trench 220b is limited, and the width of the silicon consumption of the upper side walls of the first trench 220a and the second trench 220b is limited. Therefore, the upper width of the first trench 220a and the second trench 220b can be maintained at the design requirements and will not become wider, thereby reducing the difficulty of subsequent contact hole and other lithography process deviations, improving the device's voltage resistance, on-resistance and other parameter levels, and reducing reliability risks.

[0149] like Figure 6h As shown, the oxide layer 223a, the shielding dielectric layer 221 on the upper side wall of the first trench 220a, the shielding dielectric layer 221 on the upper side wall of the second trench 220b, and the shielding dielectric layer 221 on the first surface of the semiconductor substrate 201 in the first area z21 and the second area z22 are removed to form a cavity 234a at the top of the first trench 220a and a cavity 243b at the top of the second trench 220b.

[0150] After this step, the width w22 of the second portion of the shielding conductor 222a is smaller than the width w21 of the first portion thereof, i.e., w22<w21, and the distance h23 between the top of the shielding conductor 222a and the first surface of the semiconductor substrate 201 increases, i.e., h23>h21. The distance between the top of the shielding dielectric layer 221 in the cavity 243a and the first surface of the semiconductor substrate 201 is h24.

[0151] Similarly, the width w22 of the second portion of the shielding conductor 222b in the second trench 220b is smaller than the width w21 of the first portion thereof, i.e., w22<w21, and the distance h23 between the top of the shielding conductor 222b and the first surface of the semiconductor substrate 201 increases, i.e., h23>h21. The distance between the top of the shielding dielectric layer 221 in the cavity 243b and the first surface of the semiconductor substrate 201 is h24.

[0152] Furthermore, due to the existence of the mask layer 228, it can be ensured that the shielding dielectric layer 221 below the mask layer 228 remains intact, reducing the risk of subsequent parameter abnormalities such as gate short circuits, and reducing quality control risks caused by process fluctuations.

[0153] Furthermore, the mask layer 228 can be removed or retained after this step. In this embodiment, the mask layer 228 is retained, and the mask layer 228 covers the shielding dielectric layer 221 and the shielding wiring 222c in the third region z23, which can reduce parasitic voltage, improve withstand voltage, and prevent water vapor and enhance reliability.

[0154] like Figure 6i As shown, a gate dielectric layer 2231 , a first insulating layer 2232 and a second insulating layer 2233 are formed.

[0155] In this step, for example, an oxidation growth process is used to form a gate dielectric layer 2231, a first insulating layer 2232, and a second insulating layer 2233. In the first region z21, the gate dielectric layer 2231 covers the first surface of the semiconductor substrate 201 and the sidewalls of the upper portion of the first trench 220a; the first insulating layer 2232 covers the top and exposed sidewalls of the shielding conductor 222a in the first trench 220a. In the second region z21, the gate dielectric layer 2231 covers the first surface of the semiconductor substrate 201 and the sidewalls of the upper portion of the second trench 220b, and the second insulating layer 2233 covers the top and exposed sidewalls of the shielding conductor 222b in the second trench 220b.

[0156] In this embodiment, the gate dielectric layer 2231, the first insulating layer 2232 and the second insulating layer 2233 are formed simultaneously. Due to the characteristics of polycrystalline silicon, the thickness of the first insulating layer 2232 and the second insulating layer 2233 grown on the surface of the shield conductors 222a and 222b (polycrystalline silicon) under the same conditions is thicker than the thickness of the gate dielectric layer 2231 on the surface of the semiconductor substrate 201 (silicon) and the sidewalls of the first trench 220a and the second trench 220b (silicon). The thickness of the first insulating layer 2232 and the second insulating layer 2233 is, for example, more than twice the thickness of the gate dielectric layer 2231. In one embodiment, the thickness of the gate dielectric layer 2231 is 50 angstroms to 1000 angstroms.

[0157] In other embodiments, if the Figure 6g to Figure 6h In the step of, since the width of the second portion of the shield conductors 222a, 222b is further reduced relative to the width of the first portion thereof, Figure 6i In the step of, the second portion of the shield conductor 222a in the first trench 220a is completely oxidized to form a first insulating layer 2232, and the second portion of the shield conductor 222b in the second trench 220b is completely oxidized to form a second insulating layer 2233. Figure 5c and Figure 5d shown.

[0158] Furthermore, if Figure 6j to Figure 6lAs shown, a gate conductor 224a, a gate wiring 224b, a body region 250, a source region 260, an interlayer dielectric layer 270, a first contact region 271 to a third contact region 273, a source electrode 281, a gate electrode 282 and a shielding electrode 283 are formed. Figure 6j to Figure 6l The steps shown are similar to those in the second embodiment. Figure 4j to Figure 4l The steps shown are the same and will not be repeated here in this embodiment.

[0159] Figure 7a A schematic cross-sectional view of a power semiconductor device according to a fourth embodiment of the present application is shown. Figure 7b Shows Figure 7a An enlarged schematic diagram of the internal structure of the second groove. Figure 7c A schematic cross-sectional view of another power semiconductor device according to a fourth embodiment of the present application is shown, Figure 7d Shows Figure 7c An enlarged schematic diagram of the internal structure of the second groove.

[0160] Different from the first embodiment, in this embodiment, the height of the top of the shielding conductor 222b in the second groove 220b is lower than the height of the top of the shielding conductor 222a in the first groove 220a, so that the distance h26 between the top of the shielding conductor 222b in the second groove 220b and the first surface of the semiconductor substrate 201 is further increased, thereby further increasing the distance T23 between the top of the shielding conductor 222b in the second groove 220b and the bottom of the gate electrode 282, further avoiding gate-source leakage and gate-source short circuit, reducing parameter failures, and improving yield and reliability.

[0161] In one embodiment, the distance h26 between the top of the second portion of the shielding conductor 222a and the first surface of the semiconductor substrate 201 is, for example, 0.2 microns to 3 microns; the distance between the bottom of the contact hole and the first surface of the semiconductor substrate 201 is h28, the distance T23 between the top of the second portion of the shielding conductor 222a and the bottom of the contact hole is h26-h28, and the distance T23 between the top of the second portion of the shielding conductor 222a and the bottom of the contact hole is, for example, 0.1 microns to 2.5 microns.

[0162] Furthermore, in this embodiment, a doped region 290 is formed in the semiconductor substrate 201 in the second region z22, and the depth of the doped region 290 at least reaches the extension depth h23a of the gate dielectric layer 2231 on the side wall of the second trench 220b. The doped region 290 can enable the gate dielectric layer 2231 on the side wall of the second trench 220b to withstand a greater withstand voltage and avoid damage.

[0163] Figures 8a to 8k The cross-sectional views of various stages in the preparation process of the power semiconductor device of the fourth embodiment of the present application are shown. Figures 8a to 8kA method for preparing a power semiconductor device according to a fourth embodiment of the present application is described.

[0164] Figures 8a to 8d The steps shown are similar to those in the first embodiment. Figure 2a to Figure 2d The steps shown are the same and will not be repeated here in this embodiment.

[0165] like Figure 8e As shown, a patterned mask layer is formed on the surface of the semiconductor structure to cover the first region z21 and the third region z23 of the semiconductor substrate 201 and expose the second region z22 of the semiconductor substrate 201. In this embodiment, the mask layer is, for example, a photoresist mask.

[0166] The first polysilicon layer 222 in the second trench 220b is etched through the opening of the mask layer to remove a portion of the first polysilicon layer 222 in the second trench 220b. The process of removing the first polysilicon layer 222 includes a combination of one or more of dry etching and wet etching. In one embodiment, the etching depth h21 of the first polysilicon layer 222 in the second trench 220b is 0.2 micrometers to 1 micrometer.

[0167] Next, ion implantation is performed on the semiconductor substrate 201 in the second region z22 through the opening of the mask layer to form a doped region 290 in the semiconductor substrate 201 in the second region z22. The depth of the doped region 290 at least reaches the subsequent etching depth h23a of the shielding dielectric layer 221. The doped region 290 can enable the gate dielectric layer 2231 on the sidewall of the second trench 220b to withstand a greater withstand voltage and avoid damage. Next, the mask layer is removed.

[0168] like Figure 8f As shown, a patterned mask layer 228 is formed to cover the third region z23 of the semiconductor substrate 201 and expose the first region z21 and the second region z22 of the semiconductor substrate 201. In this embodiment, the mask layer 228 is, for example, a photoresist mask layer.

[0169] The exposed first polysilicon layer 222 is etched through the opening of the mask layer 228 to remove portions of the first polysilicon layer 222 in the first trench 220 a and the second trench 220 b .

[0170] For the follow-up Figure 8g The etching depth of the shielding dielectric layer 221 in the step shown in the figure reaches the expected depth. In this embodiment, the first polysilicon layer 222 in the first trench 220a and the second trench 220b is first etched. After this step, the etching depth of the first polysilicon layer 222 in the first trench 220a is h22a. The etching depth h22a needs to be combined with Figure 8gThe etching depth of the first oxygen insulating layer 221 in the first trench 220a in the step shown is determined. In one embodiment, the etching depth h22a of the first polysilicon layer 222 in the first trench 220a is 0.2 micrometers to 3 micrometers.

[0171] Since the first polysilicon layer 222 in the second groove 220b has been etched to a certain depth h21, in this step, the etching depth of the first polysilicon layer 222 in the second groove 220b may be smaller than the etching depth of the first polysilicon layer 222 in the first groove 220a, and the total etching depth of the first polysilicon layer 222 in the second groove 220b is h22b, h22b≤h22a+h21.

[0172] In one embodiment, a total etching depth h22b of the first polysilicon layer 222 in the second trench 220b is, for example, 0.6 micrometers to 4 micrometers.

[0173] like Figure 8g As shown, the shielding dielectric layer 221 exposed by etching through the opening of the mask layer 228 is continued to be removed to remove the shielding dielectric layer 221 above the semiconductor substrate 201 in the first area z21 and the second area z22 and part of the shielding dielectric layer 221 above the first trench 220a and the second trench 220b.

[0174] The process of removing part of the shielding dielectric layer 221 includes a combination of one or more methods of dry etching and wet etching. In this embodiment, for example, wet etching is used to remove the shielding dielectric layer 221. Figure 8e and Figure 8f In the steps shown, the first polysilicon layer 222 has been etched to a certain depth to form a cavity at the top of the first trench 220a and the second trench 220b. According to the isotropic corrosion characteristics of wet etching, the wet etching liquid simultaneously etches the shielding dielectric layer 221 in the horizontal and vertical directions from the surface of the shielding dielectric layer 221 above the semiconductor substrate 201 and the cavity at the top of the first trench 220a and the second trench 220b, so that the shielding dielectric layer 221 on the surface of the semiconductor substrate 201 is removed to expose the surface of the semiconductor substrate 201, and at the same time, the shielding dielectric layer 221 on the upper side walls of the first trench 220a and the second trench 220b is etched to a certain depth, so that the top side walls of the first trench 220a and the second trench 220 are exposed. Since the etching depth of the first polysilicon layer 222 in the second trench 220b is greater than that in the first trench 220a, in this step, the etching depth h23b of the shielding dielectric layer 221 in the second trench 220b is greater than that h23a of the shielding dielectric layer 221 in the first trench 220a.

[0175] in, Figure 8gAfter the steps shown, a portion of the shielding dielectric layer 221 in the first trench 220a and the second trench 220a is removed, and the remaining shielding dielectric layer 221 covers the bottom and lower side walls of the first trench 220a and the second trench 220b; a portion of the first polysilicon layer 222 in the first trench 220a and the second trench 220b is removed, and the remaining first polysilicon layer 222 forms shielding conductors 222a and 222b, and a cavity 242a is formed in the upper part of the first trench 220a, and a cavity 242b is formed in the upper part of the second trench 220b. The shielding dielectric layer 221 and the first polysilicon layer 222 in the third groove 220c are retained, the retained shielding dielectric layer 221 covers the bottom and side walls of the third groove 220c, and covers the surface of the semiconductor substrate 201 in the third region z23, and the retained first polysilicon layer 222 forms a shielding wiring 222c, the top of which is flush with the surface of the shielding dielectric layer 221 above the semiconductor substrate 201.

[0176] After forming the cavities 242 a and 242 b , the mask layer 228 is removed.

[0177] In other embodiments, if Figure 8h Before the step, repeat Figure 4g to Figure 4h In the step of, since the width of the second portion of the shield conductors 222a, 222b is further reduced relative to the width of the first portion thereof, the second portion of the shield conductor 222a in the first trench 220a is completely oxidized to form a first insulating layer 2232, and the second portion of the shield conductor 222b in the second trench 220b is completely oxidized to form a second insulating layer 2233, as shown in FIG. Figure 7c and Figure 7d shown.

[0178] like Figure 8h to Figure 8k As shown, a gate conductor 224a, a gate wiring 224b, a body region 250, a source region 260, an interlayer dielectric layer 270, a first contact region 271 to a third contact region 273, a source electrode 281, a gate electrode 282 and a shielding electrode 283 are formed. Figure 8h to Figure 8k The steps shown are similar to those in the first embodiment. Figure 2g to Figure 2j The steps shown are the same and will not be repeated here in this embodiment.

[0179] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A power semiconductor device, characterized in that: include: a semiconductor substrate of a first doping type; A plurality of trenches located in the semiconductor substrate, the plurality of trenches comprising a first trench located in a first region, a second trench located in a second region, and a third trench located in a third region of the semiconductor substrate; A first shielding conductor is located at a lower portion of the first trench, and the first shielding conductor is isolated from the semiconductor substrate via a shielding dielectric layer; A gate conductor, located at an upper portion of the first trench, wherein the gate conductor is isolated from the semiconductor substrate via a gate dielectric layer, and the gate conductor is isolated from the first shielding conductor via a first insulating layer; a second shielding conductor, located at a lower portion of the second trench, wherein the second shielding conductor and the semiconductor substrate are isolated from each other via the shielding dielectric layer; a gate wiring, located at an upper portion of the second trench, wherein the gate wiring and the semiconductor substrate are isolated via the gate dielectric layer, and the gate wiring and the second shielding conductor are isolated via a second insulating layer; a shielding wiring, located in the third groove, the shielding wiring being isolated from the semiconductor substrate via the shielding dielectric layer, and the shielding wiring being electrically connected to the first shielding conductor and the second shielding conductor; a body region located in the semiconductor substrate, the body region being adjacent to upper portions of the first trench, the second trench and the third trench, and being of a second doping type, the second doping type being opposite to the first doping type; A source region, located in the body region of the first region, the source region being of a first doping type; a first contact region, a second contact region and a third contact region, wherein the first contact region is located in the body region and the source region of the first region, the second contact region is located in the gate wiring, and the third contact region is located in the shield wiring; a source electrode, electrically connected to the source region via the first contact region; a gate electrode electrically connected to the gate wiring via the second contact region; a shielding electrode electrically connected to the shielding wiring via the third contact region; as well as The drain electrode is located on a surface of the semiconductor substrate that is away from the body region.

2. The power semiconductor device according to claim 1, characterized in that: The gate dielectric layer covers the upper sidewall of the first trench and the upper sidewall of the second trench; The gate conductor is flush with the surface of the semiconductor substrate, and the gate wiring is flush with the surface of the semiconductor substrate.

3. The power semiconductor device according to claim 1, characterized in that: The gate dielectric layer covers the upper sidewall of the first trench, the surface of the semiconductor substrate in the first region, the upper sidewall of the second trench and the surface of the semiconductor substrate in the second region; The gate conductor is flush with the surface of the gate dielectric layer on the semiconductor substrate, and the gate wiring is flush with the surface of the gate dielectric layer on the semiconductor substrate.

4. The power semiconductor device according to claim 1, characterized in that: The first shielding conductor comprises a first portion surrounded by the shielding dielectric layer in the first trench and a second portion higher than the shielding dielectric layer in the first trench, wherein a width of the second portion of the first shielding conductor is smaller than a width of the first portion of the first shielding conductor; The second shielding conductor includes a first portion surrounded by the shielding dielectric layer in the second trench and a second portion higher than the shielding dielectric layer in the second trench, wherein a width of the second portion of the second shielding conductor is smaller than a width of the first portion of the second shielding conductor.

5. The power semiconductor device according to claim 1, characterized in that: The width of the upper portion of the first groove is greater than the width of the lower portion of the first groove, and the width of the upper portion of the second groove is greater than the width of the lower portion of the second groove; Alternatively, the width of the upper portion of the first groove is consistent with the width of the lower portion of the first groove, and the width of the upper portion of the second groove is consistent with the width of the lower portion of the second groove.

6. The power semiconductor device according to claim 1, characterized in that: The first shielding conductor is surrounded by the shielding dielectric layer in the first groove, the top of the first shielding conductor is flush with the top of the shielding dielectric layer in the first groove, and the first insulating layer is located on the top of the first shielding conductor; The second shielding conductor is surrounded by the shielding dielectric layer in the second groove, the top of the second shielding conductor is flush with the top of the shielding dielectric layer in the second groove, and the second insulating layer is located on the top of the second shielding conductor.

7. The power semiconductor device according to claim 1, characterized in that: The invention also includes a mask layer, wherein the mask layer is located in the third region, and in the third region, the mask layer covers a surface of the shielding dielectric layer above the semiconductor substrate and a surface of the shielding wiring.

8. The power semiconductor device according to claim 1, characterized in that: A top portion of the shield conductor in the first trench is higher than a top portion of the shield conductor in the second trench.

9. The power semiconductor device according to claim 8, wherein: A doped region is further disposed in the semiconductor substrate of the second region, and a depth of the doped region at least reaches an extension depth of the gate dielectric layer of the sidewall of the second trench.

10. The power semiconductor device according to claim 1, characterized in that: It also includes an interlayer dielectric layer, which is located above the semiconductor substrate, above the gate conductor, above the gate wiring and above the shielding wiring, and the source electrode, the gate electrode and the shielding electrode respectively penetrate the interlayer dielectric layer and are electrically connected to the first contact area, the second contact area and the third contact area.

11. The power semiconductor device according to claim 1, characterized in that: The source electrode is located in the first region, the gate electrode is located in the second region, the shield electrode is located in the third region, and the source electrode, the gate electrode, and the shield electrode are separated from each other.

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