Semiconductor device

Abstract

The present disclosure proposes a semiconductor device comprising a substrate, a plurality of channel layers vertically stacked and suspended over the substrate, and a gate structure surrounding each of the channel layers, wherein a height measurement of the gate structure over a top surface of a topmost one of the channel layers has a first gate critical dimension, an edge measurement of the topmost one of the channel layers has a second gate critical dimension, and an edge measurement of a bottommost one of the channel layers has a third gate critical dimension, wherein the second gate critical dimension is greater than the first gate critical dimension, and the third gate critical dimension is greater than the second gate critical dimension.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to semiconductor technology, and more particularly, to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in integrated circuit materials and design have resulted in several generations of integrated circuits, each with smaller and more complex circuits than the previous one. During the evolution of integrated circuits, functional density (that is, the number of interconnected devices per unit chip area) has generally increased while geometry size (that is, the smallest component (or line) that can be produced using a process) has decreased. This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. This miniaturization has also increased the complexity of manufacturing integrated circuits.

[0003] Recently, multi-gate semiconductor devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). One such multi-gate semiconductor device that has been introduced is a gate-all-around (GAA) transistor. The GAA device gets its name from the gate structure that extends around the channel region, providing access to the channel region from four sides, thereby allowing the channel region to achieve more complete depletion and less short-channel effect due to steeper sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL). The GAA device provides a channel region in the form of stacked channel layers. However, as transistor dimensions continue to shrink to process nodes below 3 nanometers, it may be challenging to maintain gate control and mitigate SCE and DIBL. Although current approaches have been satisfactory in many aspects, as transistor dimensions continue to shrink, further improvements to multi-gate semiconductor devices are still needed. Utility Model Content

[0004] The present disclosure aims to provide a semiconductor device to solve at least one of the above problems.

[0005] The present disclosure relates to a semiconductor device, the device comprising a substrate, a plurality of channel layers vertically stacked and suspended above the substrate, and a gate structure surrounding each of the channel layers, wherein the gate structure has a first gate critical dimension measured at a height above a top surface of an uppermost channel layer of the channel layers, a second gate critical dimension measured at an edge of the uppermost channel layer of the channel layers, and a third gate critical dimension measured at an edge of a lowermost channel layer of the channel layers, wherein the second gate critical dimension is greater than the first gate critical dimension, and the third gate critical dimension is greater than the second gate critical dimension.

[0006] According to one embodiment of the present disclosure, the gate structure includes a protruding corner located at an intersection area between the gate structure and the plurality of channel layers, and wherein a tip of the protruding corner is above the top surface of the topmost channel layer of the plurality of channel layers.

[0007] According to one embodiment of the present disclosure, the width of the protruding corner is in the range of 0.8 nanometers to 2.8 nanometers.

[0008] According to one embodiment of the present disclosure, the gate structure includes a void captured in the protruding corner.

[0009] According to one embodiment of the present disclosure, the gate structure includes a vertical sidewall terminating on the top surface of the topmost channel layer of the plurality of channel layers and a tapered sidewall starting on the top surface of the topmost channel layer of the plurality of channel layers.

[0010] According to one embodiment of the present disclosure, the height is in the range of 10 nanometers to 20 nanometers.

[0011] According to one embodiment of the present disclosure, the critical dimension of the first gate is in a range of 10 nanometers to 12 nanometers.

[0012] According to one embodiment of the present disclosure, the gate structure includes: a gate dielectric layer surrounding each of the plurality of channel layers; and a gate electrode disposed on the gate dielectric layer.

[0013] According to one embodiment of the present disclosure, the gate dielectric layer has a thickness ranging from 0.5 nanometers to 3 nanometers.

[0014] According to one embodiment of the present disclosure, it further includes: a gate spacer layer, which is disposed on a portion of the sidewall of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following will be in conjunction with the attached drawings to describe various aspects of the present disclosure. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale and are only used for illustration. In fact, the size of the elements can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present disclosure.

[0016] Figure 1 A flow chart of a method for forming a semiconductor structure is shown according to an embodiment of the present disclosure.

[0017] Figures 2 to 12 as well as Fig.19 According to an embodiment of the present disclosure, Figure 1 A perspective view of a semiconductor structure during a manufacturing process.

[0018] Fig.14 FIG. 1 is a diagram showing the relationship between a gate critical dimension profile and a gate height according to an embodiment of the present disclosure.

[0019] Fig.13 , Fig.15 , Fig.23 as well as Fig.24 According to an embodiment of the present disclosure, Figure 1 A cross-sectional view of a method of cutting through a horizontal plane of a semiconductor structure during a manufacturing process.

[0020] Fig.16 , Fig.17 , Fig.18 , Fig. 20 , Fig.21 as well as Fig. 22 According to an embodiment of the present disclosure, Figure 1 A method of manufacturing a semiconductor structure is provided for illustrating a cross-sectional view of a vertical plane cut through a semiconductor structure during a manufacturing process.

[0021] The reference numerals are as follows:

[0022] 10: Methods

[0023] 12 / 14 / 16 / 18 / 20 / 22 / 24 / 26 / 28 / 30 / 32 / 34 / 36 / 38 / 40 / 42 / 44: Operation

[0024] 100:(Semiconductor) device

[0025] 102: Base

[0026] 104: (Epitaxial) Semiconductor Stacking

[0027] 106: First film layer

[0028] 108: Second film layer

[0029] 110: mask layer

[0030] 110S: Mask Strip

[0031] 114: Groove

[0032] 116: Fin base

[0033] 120: Semiconductor Strip Stacking / Nanosheet Stacking

[0034] 120bt: bottom surface

[0035] 122: Fins

[0036] 122t: Top surface / Fin top surface / Fin top

[0037] 126: First nanosheet / channel layer / channel member

[0038] 128: Second nanosheet / sacrificial layer

[0039] 130: Insulation layer

[0040] 130t / 132t: Top surface

[0041] 132: Quarantine

[0042] 140: Virtual gate material stack

[0043] 142: (Patterned) Dummy (Gate) Dielectric Layer

[0044] 144: (Patterned) Virtual (Gate) Electrode Layer

[0045] 144B: Bottom side wall / bottom

[0046] 144M: Middle sidewall / middle

[0047] 144T: Top sidewall / top

[0048] 146: Hard mask layer

[0049] 146a: first hard mask layer

[0050] 146b: second hard mask layer

[0051] 146S: Hard mask strip

[0052] 150a: First reactive ion etching step

[0053] 150b: Second reactive ion etching step

[0054] 150c: Third reactive ion etching step

[0055] 160: Virtual Gate Stack

[0056] 162: Prominent corner

[0057] 164: Gate spacer

[0058] 170: (Source / Drain) Depression

[0059] 172:Internal spacer

[0060] 174: Source / drain component

[0061] 176: Contact etching stop layer

[0062] 178: Interlayer dielectric layer

[0063] 180: Gate trench

[0064] 190:Metal Gate Stack

[0065] 192: Gate dielectric layer

[0066] 194: Gate electrode layer

[0067] 196: Gap

[0068] ΔH: Distance

[0069] CD0 / CD1: Critical Dimension

[0070] H: Height

[0071] T1 / T2:Thickness

[0072] W1: Width DETAILED DESCRIPTION

[0073] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0074] Furthermore, spatially relative terms, such as "under", "below", "lower", "above", "higher" and the like, may be used to facilitate description of the relationship between one (or some) parts or components and another (or some) parts or components in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is rotated to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after rotation. In addition, when "approximately", "approximately", etc. are used to describe a number or a range of numbers, such terms are intended to cover numbers within + / -10% of the number, for example, the term "about 5 nanometers" covers sizes in the range of 4.5 nanometers to 5.5 nanometers.

[0075] The present disclosure generally relates to semiconductor devices and methods of formation, and in particular to forming multi-gate devices having gate structures having footprint profiles that provide tapered (increasing) gate critical dimensions (CDs). These multi-gate devices may include p-type metal oxide semiconductor devices or n-type metal oxide semiconductor devices. Specific embodiments of a type of multi-gate transistor (referred to as a gate-all-around, GAA) device) are provided herein. A GAA device includes any device whose gate structure or a portion thereof is formed on four sides of a channel region (e.g., surrounding a portion of a channel region). The channel region includes a stack of channel layers (or channel members) in the form of nanosheets, nanowires, rods, and / or other suitable channel configurations associated with a single, continuous gate structure. However, the skilled person will understand that this teaching can be applied to a single channel layer (e.g., a single nanowire / nanosheet) or any number of channel layers. The skilled person can understand other examples of semiconductor devices (such as finfield-effect transistors (FinFET) transistors) that can benefit from the various aspects of the present disclosure.

[0076] In some IC designs (such as multi-gate device designs), one advancement achieved as process generations are scaled down is to replace dummy gates (e.g., polysilicon gates) with metal gates (e.g., high-k gates) to improve device performance as feature sizes are reduced. One process for forming a metal gate is called a replacement gate or "gate-last" process, in which a metal gate is "finally" made to replace an earlier formed dummy gate, which allows for a reduction in the number of subsequent processes. In general, the goal of the patterning process for forming a dummy gate is to provide a vertical gate sidewall profile, particularly a dummy gate structure, a fin-shaped epitaxial stack, and a vertical corner profile in intersecting junctions that intersect with the top surface of the substrate (the top of the substrate may include an isolation region, as will be explained in further detail below). The vertical corner profile improves gate critical dimension (CD) uniformity. In comparison, embodiments of the present disclosure intentionally introduce gate CD non-uniformity and introduce "corners" (or "footings") to the gate sidewall profile. In some embodiments, multiple etching steps with different etching strengths are applied during the gate patterning process to form a gate structure with a tapered gate sidewall. The coverage of the tapered gate sidewall forms a "protruding corner". The gate CD at the protruding corner is greater than the gate CD above the top surface of the fin. The larger the gate CD, the stronger the gate drive capability, thereby mitigating short-channel effect (SCE) and drain induced barrier lowering (DIBL).

[0077] Figure 1 1 is a flowchart of a method for forming a semiconductor device 100 (or device 100) according to an embodiment of the present disclosure. Method 10 is merely illustrative and is not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional operations may be provided before, during, and after method 10, and some of the operations described may be replaced, deleted, or moved for additional embodiments of the method. Figures 2 to 24 Method 10 is described. Figures 2 to 24 Show according to Figure 1 Various perspective views and cross-sectional views of the device 100 during the intermediate manufacturing steps of the method 10 of the present invention are provided. The device 100 is provided for the purpose of illustration and does not limit the embodiments of the present disclosure to any number of devices, any number of regions, or any configuration of structures or regions. For example, the device 100 shown in the following embodiments can be applied to, but not limited to, GAA FETs, FinFETs, or other transistors including multi-gate structures.

[0078] Reference Figure 1 as well as Figure 2 At operation 12, method 10 provides or is provided with a device 100 having a substrate 102. In some embodiments, substrate 102 comprises a crystalline silicon substrate (e.g., a chip). Depending on design requirements, substrate 102 may include various doped regions (e.g., a p-type well and / or an n-type well). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with boron or boron difluoride (BF 2 ), n-type dopants such as phosphorus or arsenic, and / or combinations thereof. The doped region may be configured for an n-type transistor, or alternatively, configured for a p-type transistor. In some embodiments, an anti-punch-through (APT) implantation is performed on top of substrate 102 to form an APT region. The conductivity type of the dopant implanted into the APT region is the same as the conductivity type of the doped region (or well). The APT region may extend below a subsequently formed source / drain (S / D) region and is used to reduce leakage from the S / D region to substrate 102. For clarity, Figure 1 In some alternative embodiments, the substrate 102 includes an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, an alloy semiconductor such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

[0079] like Figure 2 As shown, a semiconductor stack 104 is formed on a substrate 102. The semiconductor stack 104 may include a plurality of first layers 106 and a plurality of second layers 108 alternately stacked along the Z direction. Figure 2 Only three first layers 106 and three second layers 108 are shown, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of first layers 106 and second layers 108 can be adjusted as needed, such as one, two, four or more first layers 106 and second layers 108.

[0080] In some embodiments, the first layer 106 and the second layer 108 include different materials, for example, the second layer 108 is a silicon germanium (SiGe) layer having a germanium atomic percentage between about 15% and 40%, and the first layer 106 is a silicon (Si) layer without germanium. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, the first layer 106 and the second layer 108 may have materials with different etching selectivities. In some embodiments, the first layer 106 and the second layer 108 are formed by an epitaxial growth process, such as a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and the like. Therefore, the semiconductor stack 104 may also be referred to as an epitaxial semiconductor stack 104. In this case, the first layer 106 is an epitaxial silicon (Si) layer, and the second layer 108 is an epitaxial silicon germanium (SiGe) layer. In some alternative embodiments, the first layer 106 and the second layer 108 are formed by suitable deposition, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0081] The first layer 106 and the second layer 108 may have the same or different thicknesses. In some embodiments, the first layer 106 has the same thickness T1 and the second layer 108 has the same thickness T2. In some embodiments, the thickness T1 ranges from about 5 nanometers to about 20 nanometers, and the second thickness T2 ranges from about 5 nanometers to about 20 nanometers. Alternatively, the first layer 106 may have different thicknesses from top to bottom, and the second layer 108 may have different thicknesses from top to bottom.

[0082] like Figure 2 As shown, a mask layer 110 is formed on the semiconductor stack 104. The mask layer 110 may include a single-layer structure, a two-layer structure, or a multi-layer structure. For example, the mask layer 110 includes a silicon oxide layer and a silicon nitride layer on the silicon oxide layer. In some embodiments, the mask layer 110 is formed by CVD, ALD, etc.

[0083] Reference Figure 1 as well as Figure 3, in operation 14, the method 10 patterns the mask layer 110 to form a plurality of mask strips 110S. Then, by using the mask strips 110S as a mask, the semiconductor stack 104 and the substrate 102 are patterned to form a plurality of grooves 114. In this case, a plurality of fin bases 116 and a plurality of semiconductor strip stacks 120 on the fin bases 116 are formed between the grooves 114. The grooves 114 extend into the substrate 102 and have longitudinal directions parallel to each other. In this document, the semiconductor strip stack 120 is referred to as a nanosheet stack 120, and the combination of the fin base 116 and the nanosheet stack 120 thereon is referred to as a fin 122 due to the fin-like shape. Figure 3 As shown, the nanosheet stack 120 includes a plurality of first nanosheets 126 (by patterning the first layer 106) and a plurality of second nanosheets 128 (by patterning the second layer 108) alternately stacked in the Z direction and extending in the Y direction. As explained in further detail below, the nanosheets 126 or portions thereof may form a channel layer of a multi-gate device, and the nanosheets 128 may eventually be removed and used to define the vertical distance between the channel layers. The nanosheets 126 may also be referred to as channel layers (or channel members) 126, and the nanosheets 128 may also be referred to as sacrificial layers 128.

[0084] In some embodiments, the fins 122 can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes to create, for example, a pattern with a smaller pitch than that obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as masks to pattern the fins 122.

[0085] although Figure 3 Only two fins 122 are shown in the figure, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of fins 122 can be adjusted as needed, such as 1 fin, 3 fins, 4 fins or more fins. In addition, Figure 3 The mask strip 110S shown has a flat top surface. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, the mask strip 110S may have a dome top surface due to high aspect ratio etching.

[0086] Reference Figure 1 as well as Figure 4, in operation 16, method 10 forms an insulating layer 130 in the trench 114. In some embodiments, an insulating material is formed on the substrate 102 to cover the fin 122 and fill the trench 114. In addition to the fin 122, the insulating material also covers the mask strip 110S. The insulating material may include silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. In this article, a low-k dielectric material is generally a dielectric material with a dielectric constant lower than 3.9. The insulating material can be formed by flowable chemical vapor deposition (FCVD), high-density plasma chemical vapor deposition (HDP-CVD), sub-atmospheric chemical vapor deposition (SACVD), or spin coating. A planarization process can be performed to remove the insulating material and a portion of the mask strip 110S until the fin 122 is exposed. In this case, as Figure 4 As shown, the top surface 122t of the fin 122 (also referred to as the fin top surface or the fin top) is substantially coplanar with the top surface 130t of the planarization insulating layer 130. In some embodiments, the planarization process includes chemical mechanical polishing (CMP), an etch-back process, a combination thereof, and the like.

[0087] Reference Figure 1 as well as Figure 5, in operation 18, the method 10 recesses the insulating layer 130 to form a plurality of isolation regions 132. After the insulating layer 130 is recessed, the fin 122 protrudes from the top surface 132t of the isolation region 132, that is, the top surface 132t of the isolation region 132 may be lower than the top surface 122t of the fin 122. In some embodiments, the nanosheet stack 120 is exposed by the isolation region 132, that is, the top surface 132t of the isolation region 132 may be substantially coplanar with the bottom surface 120bt of the nanosheet stack 120 or lower than the bottom surface 120bt of the nanosheet stack 120. In addition, the top surface 132t of the isolation region 132 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination of the foregoing as shown. In some embodiments, the insulating layer 130 is recessed by using an appropriate etching process (such as a wet etching process using hydrofluoric acid (HF), a dry etching process, or a combination of the foregoing). In some embodiments, the height difference between the top surface 122t of the fin 122 and the top surface 132t of the isolation region 132 is in the range of about 30 nanometers to about 100 nanometers. In some embodiments, the isolation region 132 can be a shallow trench isolation (STI) region, a deep trench isolation (DTI) region, etc.

[0088] Reference Figure 1 as well as Figure 6 , in operation 20, method 10 forms a dummy dielectric layer 142 on substrate 102. In some embodiments, the dummy dielectric layer 142 conformally covers the exposed surface of the fin 122 (nanosheet stack 120) and the top surface 132t of the isolation region 132. The dummy dielectric layer 142 can be formed by thermal oxidation, CVD, sputtering, or any other method known in the art and used to form a dummy dielectric layer. In some embodiments, the dummy dielectric layer 142 can be formed of the same material as the isolation region 132. In other embodiments, the dummy dielectric layer 142 can be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant dielectrics such as carbon-doped oxides, extremely low dielectric constant dielectrics such as porous carbon-doped silicon dioxide, polymers such as polyimide, etc., or combinations of the foregoing. In other embodiments, the dummy dielectric layer 142 includes a dielectric material having a high dielectric constant (k value), for example, greater than 3.9. These materials can include silicon nitride, oxynitride, metal oxides such as hafnium oxide (HfO 2 ), hafnium zirconium oxide (HfZrO x ), hafnium silicon oxide (HfSiO), hafnium titanium oxide (HfTiO x ), hafnium aluminum oxide (Hf AlO x ) etc.) or combinations and multiple layers of the foregoing.

[0089] Reference Figure 1 as well as Figure 7 At operation 22, the method 10 forms a dummy electrode layer 144 covering the dummy dielectric layer 142 and a hard mask layer 146 covering the dummy electrode layer 144. The dummy dielectric layer 142, the dummy electrode layer 144, and the hard mask layer 146 are collectively referred to as a dummy gate material stack 140. The dummy gate material stack 140 is then patterned to form a dummy gate stack, which will be used to define and form source / drain regions. The dummy gate stack will then be removed to allow processing of the fins in the channel region, and a metal gate stack will be formed over the channel region.

[0090] The dummy electrode layer 144 is formed above the dummy dielectric layer 142. In some embodiments, the dummy electrode layer 144 is a conductive material and can be selected from a combination of polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. In one embodiment, the dummy electrode layer 144 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit conductive materials. Other materials, both conductive and non-conductive, can be used. The top surface of the dummy electrode layer 144 typically has a non-flat top surface and can be flattened after deposition.

[0091] Figure 7 Also shown is a hard mask layer 146 formed above the dummy electrode layer 144. The hard mask layer 146 includes one or more mask layers and will be used to pattern the dummy electrode layer 144 to form a dummy gate electrode. In some embodiments, the hard mask layer 146 includes a first hard mask layer 146a and a second hard mask layer 146b. The first hard mask layer 146a can be an oxide layer (e.g., silicon oxide), and the second hard mask layer 146b can be a nitride layer (e.g., silicon nitride). The first hard mask layer 146a and the second hard mask layer 146b can be deposited by a process such as CVD or a spin-on glass (SOG) process, but any acceptable process can be used. In some embodiments, the first hard mask layer 146a can have a thickness of about 10 angstroms. To a thickness of about 50 angstroms, the second hard mask layer 146 b may have a thickness of about 150 angstroms to about 850 angstroms.

[0092] Reference Figure 1 as well as Figure 8 At operation 24, method 10 patterns hard mask layer 146 to form a plurality of hard mask strips 146S. Figure 8A single hard mask strip 146S is shown in the figure, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of hard mask strips 146S can be adjusted as needed, such as two strips, three strips, or more strips. The hard mask strip 146S extends along the X direction perpendicular to the longitudinal direction of the fin 122. As discussed in further detail below, the pattern defined in the hard mask strip 146S will be transferred to the underlying dummy electrode layer 144 and the dummy dielectric layer 142 to form a dummy gate stack across the fin 122.

[0093] In some embodiments, method 10 uses a photolithography process at operation 24, which includes forming a photoresist layer (not shown) over hard mask layer 146 (e.g., by spin coating), performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiation energy (e.g., ultraviolet (UV) light, deep ultraviolet (DUV) light, or extreme ultraviolet (EUV) light), wherein the mask blocks, transmits, and / or reflects radiation to the photoresist layer according to a mask pattern and / or a mask type (e.g., a binary mask, a phase shift mask, or an EUV mask) of the mask, so that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiation energy, the exposed portion of the photoresist layer undergoes a chemical change, and according to the characteristics of the photoresist layer and the characteristics of the developing solution used in the development process, the exposed (or unexposed) portion of the photoresist layer is dissolved in the development process. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the mask. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or a combination of the foregoing. Method 10 then etches the second hard mask layer 146b and the first hard mask layer 146a through the opening defined in the patterned photoresist layer at operation 24. The etching process can include wet etching, dry etching, RIE, ashing and / or other suitable techniques. After forming the hard mask strips 146S, the patterned photoresist layer can be stripped from the device 100.

[0094] in addition, Figure 8 The hard mask strip 146S is shown to have a flat top surface. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, the hard mask strip 146S may have a rounded top surface due to high aspect ratio etching.

[0095] Reference Figure 1 as well as Fig. 9, in operation 26, method 10 etches the top of the dummy electrode layer 144 through the opening defined in the hard mask strip 146S. In this manner, the hard mask strip 146S serves as an etching mask. Generally speaking, the dummy electrode layer 144 is patterned in an anisotropic etching step to expose the fin 122 thereunder, such as in a plasma etching process with high power and high bias to ensure strong etching directionality. The patterned dummy electrode layer 144 of the resulting structure generally has substantially vertical sidewalls, in other words, the gate CD can remain substantially the same from the top of the gate to the bottom of the gate (that is, at the top surface 132t of the isolation region 132). However, as transistor dimensions continue to shrink to process generations below 3 nanometers, maintaining gate control can be challenging. In some IC applications, it is necessary to increase the gate CD, particularly the gate CD at the bottom of the channel region, to mitigate SCE and DIBL. To intentionally introduce a tapered gate CD profile to achieve greater gate CD and stronger gate control near the bottom of the nanosheet stack 120, as explained in more detail below, the method 10 includes multiple etching steps to pattern the dummy electrode layer 144 instead of a single etching step. The multiple etching steps use a stronger etching step followed by one or more weaker etching steps to reduce the etching strength as the etching approaches the bottom of the gate, thereby intentionally introducing a tapered gate sidewall, thereby having a tapered gate CD profile at the intersection of the gate stack and the underlying protruding fin ( Fig.14 ). In some embodiments, multiple etching steps are in situ.

[0096] In some embodiments, operation 26 includes a plasma etching process. In a further embodiment, operation 26 includes a first RIE step 150a. In the sequence of multiple etching steps for patterning the dummy electrode layer 144, the first RIE step 150a is the strongest step in terms of etching rate and etching directionality. Various etching parameters can be adjusted to enhance the first RIE step 150a, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source radio frequency (RF) power, bias RF voltage, etchant flow rate, other suitable etching parameters, or a combination of the foregoing. In some embodiments, the etchant can be a plasma containing a sulfur-containing compound, such as sulfur dioxide (SO 2 ) mixed with an inert gas selected from helium (He), argon (Ar), xenon (Xe), krypton (Kr), neon (Ne) and a combination of the foregoing. 2 In a specific example, the first RIE step 150a is performed at a temperature between 0 and about 500 sccm of SO 2 / He flow rate, a gas pressure between 0 and about 60 mtorr, a source RF power between about 200 and about 600 Watts, a bias RF voltage between about 300 volts (V) and about 800 V, a frequency between about 12 megahertz (MHz) and about 14 MHz, and a temperature between about 50°C and about 60°C are applied.

[0097] As the strongest step in the sequence of multiple etching steps, the first RIE step 150a produces a substantially vertical sidewall at the top of the patterned dummy electrode layer 144, represented as the top sidewall 144T. The first RIE step 150a also recesses the top surface of the dummy electrode layer 144 at a fast rate, thereby reducing manufacturing time and increasing product yield. The first RIE step 150a can be a timed etch that is intended to stop at a certain distance (represented as ΔH) from the top surface of the fin 122. The distance ΔH allows the etching process to switch to the process window of the subsequent weaker etching step. The distance ΔH can also protect the top of the fin from being damaged in the strong plasma etching. In some embodiments, the distance ΔH ranges from about 10 nanometers to about 20 nanometers. This range is not arbitrary. If the distance ΔH is less than 10 nanometers, the process window for etching strength conversion may be too small and the top of the fin may be damaged. If the distance ΔH is greater than 20 nanometers, the sidewalls of the patterned dummy electrode layer 144 may begin to taper prematurely and cause the bottom of the gate to protrude into the adjacent dummy gate stack (that is, a device-level metal short).

[0098] Reference Figure 1 as well as Fig.10 , at operation 28, method 10 etches the middle portion of dummy electrode layer 144 using an etching step that is weaker than the previous etching step applied in operation 26. Under the weaker etching step, the sidewalls of patterned dummy electrode layer 144 begin to taper. In some embodiments, operation 28 includes a plasma etching process. In further embodiments, operation 28 includes a second RIE step 150b. The second RIE step 150b is weaker than the first RIE step 150a in terms of etching rate and etching directionality.

[0099] In some embodiments, the second RIE step 150b has the same etchant, flow rate, gas pressure, and temperature as the first RIE step 150a, but with a lower source RF power and a lower bias RF voltage. In further embodiments, the source RF power and the bias RF voltage can be reduced by about half during the transition from the first RIE step 150a to the second RIE step 150b. In a specific example, the second RIE step 150b is operated at a SO of between 0 and about 500 sccm. 2 / He flow rate, a gas pressure between 0 to about 60 mtorr, a source RF power between about 100 to about 300 watts, a bias RF voltage between about 150 volts (V) to about 400 V, a frequency between about 12 megahertz (MHz) to about 14 MHz, and a temperature between about 50°C to about 60°C.

[0100] The second RIE step 150b may be a timed etch designed to stop when the top of the fin is exposed or about to be exposed (ie, ΔH≈0). The weaker second RIE step 150b produces a middle portion (denoted as 144M) of the sidewall of the patterned dummy electrode layer 144 that begins to taper away from the top 144T.

[0101] Reference Figure 1 as well as Fig.11 , in operation 30, method 10 utilizes an etching step that is weaker than the previous etching step applied in operation 28 to etch the bottom of the dummy electrode layer 144 below the top of the fin. Even with the weaker etching step, the sidewalls of the patterned dummy electrode layer 144 continue to taper. In some embodiments, operation 30 includes a plasma etching process. In further embodiments, operation 30 includes a third RIE step 150c. The third RIE step 150c is weaker than the first RIE step 150a and the second RIE step 150b in terms of etching rate and etching directionality. The even weaker third RIE step 150c produces a bottom (denoted as 144B) of the sidewalls of the patterned dummy electrode layer 144 that tapers further away from the middle 144M.

[0102] In some embodiments, the third RIE step 150c has the same etchant, flow rate, gas pressure, and temperature as the second RIE step 150b, but has a further reduced source RF power and bias RF voltage. In further embodiments, the source RF power and bias RF voltage are reduced by about half in the transition from the second RIE step 150b to the third RIE step 150c. In a specific example, the third RIE step 150c is performed at a SO of between 0 and about 500 sccm. 2 / He flow rate, a gas pressure between 0 to about 60 mtorr, a source RF power between about 50 to about 150 watts, a bias RF voltage between about 75 volts (V) to about 200 V, a frequency between about 12 megahertz (MHz) to about 14 MHz, and a temperature between about 50°C to about 60°C are applied.

[0103] In some embodiments, the third RIE step 150c uses an etchant different from that of the first RIE step and the second RIE step, such as an etchant containing carbon tetrafluoride (CF4) in addition to the sulfur-containing compound. 4 ) and chlorine (Cl2 ) (that is, CF 4 / Cl 2 Plasma). In addition, the third RIE step 150c can intentionally introduce an etchant that can produce a polymer as a byproduct, such as a fluorine-containing etchant mixed with a nitrogen-containing carrier gas. Among other locations, the byproduct polymer can be formed on the bottom 144B of the sidewall. The polymer can slow down the etching of the recessed dummy electrode layer 144. In comparison, the first RIE step 150a and the second RIE step 150b can be free of byproduct polymers. As a result, the third RIE step 150c has the weakest etching strength in a series of multiple etching steps.

[0104] The third RIE step 150c exposes the top surface of the dummy dielectric layer 142. The uncovered portion of the dummy dielectric layer 142 may be further removed in a separate selective etching process. In some embodiments, the third RIE step 150c also removes the uncovered portion of the dummy dielectric layer 142 and exposes the top surface of the isolation region 132. A cleaning process may be applied to remove byproduct polymers (if any) from the device 100. The resulting structure is shown in FIG. Fig.12 As shown, the patterned dummy dielectric layer 142 , the patterned dummy electrode layer 144 and the hard mask strip 146S are collectively referred to as a dummy gate stack 160 . The patterned dummy dielectric layer 142 is also referred to as a dummy gate dielectric layer 142 . The patterned dummy electrode layer 144 is also referred to as a dummy gate electrode 144 .

[0105] Still refer to Fig.12 , multiple RIE steps 150a-c produce a protruding corner at the intersection of the dummy gate stack 160 and the protruding fin 122 below. The protruding corner starts at the middle 144M of the sidewall of the dummy gate stack 160, continues to the bottom 144B, and stops at the top surface of the isolation region 132. At the protruding corner, the gate CD (denoted as CD1) is greater than the gate CD (denoted as CD0) away from the protruding corner. Because the protruding corner starts above the top of the fin, the channel region (starting from the topmost channel layer 126 and downward) benefits from a relatively large gate CD. However, in some alternative embodiments, depending on the specific etching parameters of the above-mentioned anisotropic etching process (for example, the second RIE step 150b can be optionally skipped), the protruding corner can start below the top of the fin (that is, there is no 144M above the top of the fin). As a result, the top channel layer 126 can still be bonded by the gate CD (ie, CD0), while the middle channel layer 126 and the bottom channel layer 126 are bonded by the gate CD (ie, all larger than CD0).

[0106] Fig.13 Show Fig.12The cross-sectional view of the structure shown. The cross-sectional view is from the Fig.12 The horizontal plane passes through one of the channel layers 126 (e.g., the top channel layer 126, one of the middle channel layers 126, or the bottom channel layer 126). Fig.13 , one of the dummy gate stacks 160 is shown. The gate length (measured along a direction perpendicular to the longitudinal direction of the gate stack; that is, along Fig.13 The gate CD measured in the Y direction in the dummy gate stack 160 is denoted as the gate critical dimension (CD). Due to the gate patterning process discussed above, the portion where the dummy gate stack 160 intersects the fin 122 may be wider than other portions away from the fin 122. The widening in the portion where the dummy gate stack 160 intersects the fin 122 is also referred to as the "footing effect", and the widened portion is referred to as the footing region (or protruding corner), as marked by portion 162. Therefore, the gate CD measured at different portions of the dummy gate stack 160 may have different values. Fig.13 The gate CD measured at two different regions of the dummy gate stack 160 are shown, denoted as CD0 and CD1. CD0 is measured in a region away from the fin, which is referred to as the "outside fin" region. CD1 is measured near the edge (sidewall) of the protruding fin 122 (or channel layer 126), which is referred to as the "on-fin" region. The term "near" refers to a distance less than about 1 nanometer or just on the edge of the protruding fin.

[0107] In some embodiments, CD0 ranges from about 10 nanometers to about 12 nanometers, the width ((CD1-CD0) / 2) of the protruding corner 162 measured along the Y direction ranges from about 0.8 nanometers to about 2.8 nanometers, and the width of the channel layer 126 measured along the X direction (denoted as Wc) ranges from about 20 nanometers to about 25 nanometers.

[0108] By measuring the gate CD of different heights of the dummy gate stack 160 along the Z direction, the gate CD profile of the dummy gate stack 160 can be obtained. In various embodiments, the gate CD can be measured by metrology of the prior art, such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), critical dimension scanning electron microscopy (CD-SEM). Others such as optical critical dimension (OCD), atomic force microscope (AFM) and critical dimension-atomic force microscope (CD-AFM) can also be used to measure the gate CD.

[0109] Fig.14 Graph showing exemplary gate CD profiles measured at different regions of the dummy gate stack 160 . Fig.14 The graph in is common to both virtual gate stacks and replacement gate stacks (e.g., metal gate stacks) because the replacement gate stack can inherit the shape of the virtual gate stack. The horizontal axis in the graph represents the gate CD value, and the vertical axis in the graph represents the height of the gate stack relative to the top surface 132t of the isolation region 132. The total height of the gate stack (H1) and the total height of the protruding portion of the fin 122 (H2) are also marked on the vertical axis for reference. In particular, in the graph, line "CD0" represents the gate CD measured in the "outer fin" region of the gate stack, and line "CD1" represents the gate CD measured in the "on fin" region of the gate stack.

[0110] Still refer to Fig.14, when above the height ΔH above the fin top of the protruding fin, the gate CD measured in the "outer fin" region and the "on fin" region has a shape of substantially the same value (that is, CD0=CD1), which corresponds to the vertical top 144T of the gate stack sidewall. As described above, in some embodiments, ΔH can be in the range of about 10 nanometers to about 20 nanometers. Along the line "CD0", the gate CD remains substantially the same due to the vertical sidewall of the gate stack in the "outer fin" region. The line "CD0" may taper slightly when approaching the top surface 132t of the isolation region 132, which is mainly caused by the etching residues remaining in the corner region of the gate stack. Along the line "CD1", the gate CD begins to taper below the height ΔH above the fin top of the protruding fin, which corresponds to the tapered middle 144M of the gate stack sidewall, and further tapers below the fin top (H2) of the protruding fin 122, which corresponds to the tapered bottom 144B of the gate stack sidewall. The larger gate CD in the "on-fin" region provides stronger gate control capability. In addition, the closer to the bottom of the channel region, the larger the gate CD in the "on-fin" region becomes, which effectively combats SCE and DIBL. In some embodiments, DIBL can be suppressed by about 10%.

[0111] Reference Figure 1 as well as Fig.15 At operation 32 , method 10 conformally forms gate spacers 164 on sidewalls of the dummy gate stack 160 . Fig.15 From the included Fig.12 The gate spacer 164 can follow the contour of the sidewalls of the dummy gate stack 160 and thus cover the protruding corners of the dummy gate stack 160. In some embodiments, the gate spacer 164 is formed of a dielectric material such as silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiCON), or a combination of the foregoing. In some embodiments, the thickness of the gate spacer 164 ranges from about 1 nanometer to about 5 nanometers. Although Fig.15 The gate spacer 164 shown in FIG. 1 is a single-layer structure, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the gate spacer 164 may be a multi-layer structure, for example, the gate spacer 164 may include a silicon oxide layer and a silicon nitride layer disposed on the silicon oxide layer.

[0112] See also Figure 1 as well as Fig.16 At operation 34 , the method 10 removes the end of the nanosheet stack 120 to form the recess 170 . Fig.16 From the included Fig.121-1. Here, the recess 170 may be referred to as a source / drain (S / D) recess 170. In some embodiments, the end of the nanosheet stack 120 may be removed by an anisotropic etching process, an isotropic etching process, or a combination of the foregoing. In some embodiments, the S / D recess 170 also extends into the fin base 116 and is lower than the top surface 132t of the isolation region 132. In other words, the end of the nanosheet stack 120 is completely removed, and the top of the fin base 116 is further removed.

[0113] Reference Figure 1 as well as Fig.17 At operation 36, method 10 forms inner spacers 172 at opposite ends of sacrificial layer 128. In some embodiments, opposite ends of sacrificial layer 128 exposed in source / drain trenches 170 are selectively and partially recessed to form inner spacer recesses (not shown), while channel layer 126 is not substantially etched. In embodiments where channel layer 126 is primarily composed of silicon (Si) and sacrificial layer 128 is primarily composed of silicon germanium (SiGe), the selective and partial recessing of sacrificial layer 128 may include a silicon germanium oxidation process followed by silicon germanium oxide removal. The silicon germanium oxidation process may include using ozone (O 3 ). In some other embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 128 is recessed is controlled by the duration of the etching process. The selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include hydrofluoric acid (HF) or ammonia (NH 4 OH) etchant. After forming the inner spacer recess, an inner spacer material layer is deposited over the device 100, including in the inner spacer recess. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess inner spacer material layer over the sidewalls of the gate spacer 164 and the channel layer 126, thereby forming the inner spacer 172. In some embodiments, the etch back process may be a dry etching process, which includes using an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (e.g., carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), difluoromethane (CH 2 F 2 ), fluoroform (CHF 3 ) and / or hexafluoroethane (C 2 F 6 )), chlorine-containing gases (such as chlorine (Cl 2 ), chloroform (CHCl 3), carbon tetrachloride (CCl 4 ) and / or boron trichloride (BCl 3 )), bromine-containing gases (such as hydrogen bromide (HBr) and / or hydrogen bromide (CHBR 3 )), iodine-containing gases (e.g. trifluoroiodomethane (CF 3 I)), other suitable gases and / or plasmas and / or combinations of the foregoing.

[0114] Reference Figure 1 as well as Fig.18 At operation 38, the method 10 epitaxially grows a source / drain (S / D) feature 174 from the S / D recess 170. In this case, the S / D feature 174 includes a source disposed on one side of the dummy gate stack 160 and a drain disposed on the other side of the dummy gate stack 160. The source covers one end of the fin base 116, and the drain covers the other end of the fin base 116. The S / D feature 174 is adjacent to and electrically connected to the channel layer 126, while the S / D feature 174 is electrically isolated from the sacrificial layer 128 by the inner spacer 172. In some embodiments, the S / D feature 174 extends beyond the top surface of the nanosheet stack 120. However, embodiments of the present disclosure are not limited thereto, and in other embodiments, the top surface of the S / D feature 174 is substantially aligned with the top surface of the nanosheet stack 120.

[0115] The S / D component 174 includes any acceptable material, such as a material suitable for a p-type transistor or an n-type transistor, for example, the S / D component 174 may include silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium (Ge), germanium tin (GeSn), etc. suitable for a p-type transistor. In some alternative embodiments, the S / D component 174 may include silicon, silicon carbon (SiC), silicon carbon phosphide (SiCP), silicon phosphide (SiP), etc. suitable for an n-type transistor. In some embodiments, the S / D component 174 is formed by MOCVD, MBE, ALD, etc. The S / D component 174 may include one or more semiconductor material layers, for example, the S / D component 174 may include a bottom semiconductor material layer, an intermediate semiconductor material layer, and a capping semiconductor material layer. Any number of semiconductor material layers may be used for the S / D component 174. Each semiconductor material layer may be formed of a different semiconductor material and may be doped to a different dopant concentration. In embodiments where the S / D features 174 include three semiconductor material layers, a bottom semiconductor material layer may be deposited, a middle semiconductor material layer may be deposited over the bottom semiconductor material layer, and a capping semiconductor material layer may be deposited over the middle semiconductor material layer.

[0116] In some embodiments, the S / D component 174 is doped with conductive dopants. For example, the S / D component 174, such as SiGe, can be epitaxially grown with p-type dopants to apply strain to the p-type transistor. That is, the S / D component 174 is doped with p-type dopants to become the source and drain of the p-type transistor. The p-type dopant includes boron or boron difluoride (BF 2 ), and the S / D component 174 can be epitaxially grown by a low-pressure chemical vapor deposition (LPCVD) process with in-situ doping. As described above, the S / D component 174 can be epitaxially grown with multiple layers having different dopant concentrations, such as a SiGe:B bottom layer with a Ge atomic percentage of about 45% to 55% and a boron concentration of about 1x10 21 / cubic centimeters to about 2x10 21 / cubic centimeter, SiGe:B intermediate layer, Ge atomic percentage is about 45% to 60%, and boron concentration is about 8x10 20 / cubic centimeters to about 3x10 21 / cubic centimeter and a SiGe:B capping layer with a Ge atomic percentage of about 25% to 45% and a boron concentration of about 1x10 20 / cubic centimeters to about 8x10 20 / cubic centimeter. In some alternative embodiments, the S / D component 174 (such as silicon carbon (SiC), silicon phosphide (SiP), a combination of SiC / SiP, or silicon carbon phosphide (SiCP)) is epitaxially grown using n-type dopants to apply strain to the n-type transistor. That is, the S / D component 174 is doped with n-type dopants to become the source and drain of the n-type transistor. The n-type dopant includes arsenic and / or phosphorus, and the S / D component 174 can be epitaxially grown by an LPCVD process with in-situ doping. In some embodiments, the S / D component 174 is epitaxially grown with multiple film layers with different dopant concentrations, such as a phosphorus concentration of about 1x10 21 / cubic centimeters to about 2x10 21 / cubic centimeter of Si:P bottom layer, phosphorus concentration is about 1x10 21 / cubic centimeters to about 4x10 21 / cubic centimeter of Si:P intermediate layer and arsenic concentration of about 1×10 20 / cubic centimeter to about 1×10 21 / cubic centimeter of Si:As capping layer.

[0117] As a result of the epitaxial growth process for forming the S / D component 174, the cross section of the S / D component 174 may have a rhombus or pentagonal shape. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the cross section of the S / D component 174 also has a hexagonal shape, a columnar shape, or a bar shape. Fig.19A perspective view of an exemplary resulting structure after the epitaxial growth process is completed is depicted. Fig.19 As shown, adjacent S / D features 174 are separated from each other after the epitaxial growth process is completed. Alternatively, adjacent S / D features 174 may be merged.

[0118] Reference Figure 1 as well as Fig. 20 At operation 40 , method 10 forms an interlayer dielectric (ILD) layer 178 over device 100 . Fig. 20 From the included Fig.19 A contact etch stop layer (CESL) 176 may also be formed between the S / D features 174 and the ILD layer 178. In some embodiments, the CESL 176 conformally covers the sidewalls of the S / D features 174 and the outer sidewalls of the gate spacer 164. The CESL 176 may include silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, and / or other materials; and may be formed by CVD, PVD, ALD, or other suitable methods.

[0119] The ILD layer 178 includes silicon oxide, silicon nitride, silicon oxynitride, phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silicate glass (FSG), carbon-doped silicon oxide (e.g., silicon oxycarbide (SiCOH)), polyimide, and / or combinations thereof. In some other embodiments, the ILD layer 178 includes a low-k dielectric material. Examples of low-k dielectric materials include Black (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), (Dow Chemical, Midland, Michigan), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF) and / or a combination of the foregoing. In alternative embodiments, the ILD layer 178 includes one or more dielectric materials and / or one or more dielectric layers. In some embodiments, the ILD layer 178 is formed to a suitable thickness by FCVD, CVD, HDPCVD, SACVD, spin coating, sputtering or other suitable methods. For example, an interlayer dielectric material layer is first formed to cover the isolation region 132, the dummy gate stack 160 and the gate spacer 164. Subsequently, the thickness of the interlayer dielectric material layer is reduced until the dummy gate electrode 144 is exposed, thereby forming the ILD layer 178. The process of reducing the thickness of the interlayer dielectric material layer can be achieved by a CMP process, an etching process or other suitable process. In this case, the top surface of the ILD layer 178 can be coplanar with the top surface of the dummy gate electrode 144.

[0120] Reference Figure 1 as well as Fig.21 At operation 42, the method 10 removes the dummy gate stack 160 to form a gate trench 180. The CESL 176 and the ILD layer 178 can protect the S / D features 174 during the removal of the dummy gate stack 160. The dummy gate stack 160 can be removed using a plasma dry etch and / or a wet etch. When the dummy gate electrode 144 is polysilicon and the ILD layer 178 is silicon oxide, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode 144. Thereafter, the dummy gate dielectric layer 142 is removed by using another plasma dry etch and / or a wet etch.

[0121] Also like Fig.21As shown, an etching process is performed to remove the sacrificial layer 128. In this case, the sacrificial layer 128 can be completely removed to form a plurality of gaps between the channel layers 126. Therefore, the channel layers 126 are separated from each other by the gaps. In addition, the bottommost channel layer 126 can also be separated from the fin base 116 by the gap, so that the channel layer 126 is suspended. In the present embodiment, the channel layer 126 includes silicon and the sacrificial layer 128 includes silicon germanium. The sacrificial layer 128 can be selectively removed by oxidizing the sacrificial layer 128 using a suitable oxidant (such as ozone). Thereafter, the oxidized sacrificial layer 128 can be selectively removed from the gate trench 180. In some embodiments, the etching process includes a dry etching process to selectively remove the sacrificial layer 128, for example, by applying hydrogen chloride (HCl) gas at a temperature of about 20°C to about 300°C, or applying carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ) and fluoroform (CHF 3 ) gas mixture. The opposite end of the suspended channel layer 126 is connected to the S / D feature 174. The etching process may be referred to as a channel layer (or channel member) releasing process.

[0122] Reference Figure 1 as well as Figure 22 to Figure 23 At operation 44 , method 10 forms a metal gate stack 190 , such as a high-k metal gate stack, in gate trench 180 . Fig. 22 From the included Fig.19 A cross-sectional view obtained in a plane perpendicular to the line II-II. Fig.23 From the included Fig.19 . The horizontal plane passes through one of the channel layers 126 (e.g., the topmost channel layer 126, one of the middle channel layers 126, or the bottommost channel layer 126). The metal gate stack 190 includes a gate dielectric layer 192 and a gate electrode 194. The gate dielectric layer 192 surrounds the channel layer 126. In some embodiments, the gate dielectric layer 192 includes one or more dielectric materials, such as silicon oxide, silicon nitride, or a high dielectric constant dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high dielectric constant dielectric materials include hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium oxysilicide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), aluminum oxide (Al 2 O 3 ), hafnium oxide-aluminum oxide alloy (HfO 2 -Al 2 O 3alloy), other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 192 includes an interface layer (not shown) formed between the channel layer 126 and the high-k dielectric material. The gate dielectric layer 192 can be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 192 is formed by using a highly compliant deposition process such as ALD to ensure that a gate dielectric layer with uniform thickness is formed around each channel layer 126. In some embodiments, the thickness of the gate dielectric layer 192 ranges from about 0.5 nanometers to about 3 nanometers.

[0123] The gate electrode 194 is formed on the gate dielectric layer 192 and then planarized by using, for example, a CMP process until the top surface of the ILD layer 178 is exposed. The gate electrode 194 may include various conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum nitride (TaSiN), metal alloys, other suitable materials, and / or combinations thereof. The gate electrode 194 may include one or more conductive materials, such as a work function metal (WFM) layer and a metal filling layer (not shown) and / or other suitable film layers.

[0124] like Fig.23 As shown, the gate dielectric layer 192 and / or the gate electrode 194 can completely fill the space in the protruding corner 162. Fig.24 In the illustrated alternative embodiment, because it is difficult to fill the corner regions in the high aspect ratio gate trenches, voids 196 may be sealed by the gate dielectric layer 192 in the protruding corners 162. The voids 196 may trap air or other ambient gases applied during the manufacturing process. In addition, because it is more difficult to fill the corner regions closer to the bottom of the high aspect ratio gate trenches, the size of the voids 196 in the cross-sectional view becomes larger as the cross-sectional view cuts through the bottom channel layer of the channel layer 126. In one embodiment, the cross-sectional view cut through the topmost channel layer 126 is free of voids 196, as shown in FIG. Fig.23 As shown in FIG. 1 , a cross-sectional view of a cut through the underlying intermediate channel layer 126 (particularly, the bottommost channel layer 126) may show a void 196. Although the size of the void 196 may increase as the bottom of the gate is approached, as shown in FIG. Fig.14 As shown in Figure 2, due to the gradual taper of the gate sidewall, the gate CD on the “fin” ( Fig.14In some embodiments, the void 196 is replaced by the remnants of the dummy gate dielectric layer 142 and / or the dummy gate electrode 144 remaining in the corner region of the protruding corner 162, because it is difficult to remove the remnants from the high aspect ratio gate trench during the removal process.

[0125] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor devices and methods of forming the same. For example, embodiments of the present disclosure provide simple and cost-effective systems and methods for forming gates without significantly reducing production capacity. In the present disclosure, the critical dimensions of the gate measured near or on the edge of the gate stack bonding fin are enlarged to provide better gate control. In addition, the workflow of gate formation can be easily incorporated into existing semiconductor manufacturing processes.

[0126] In an exemplary manner, the present disclosure relates to a method for forming a semiconductor structure, the method comprising providing a structure, the structure comprising a substrate and a fin protruding from the substrate, depositing a dummy material stack above the fin, patterning the top of the dummy material stack in a first etching process, the first etching process having a first etching strength, patterning the middle of the dummy material stack in a second etching process, the second etching process having a second etching strength weaker than the first etching strength, patterning the bottom of the dummy material stack in a third etching process, thereby forming a dummy gate stack, the third etching process having a third etching strength weaker than the second etching strength, and replacing the dummy gate stack with a metal gate stack. In some embodiments, the first etching process produces a substantially vertical sidewall at the top of the dummy material stack. In some embodiments, the second etching process produces a tapered sidewall in the middle of the dummy material stack. In some embodiments, the third etching process produces a tapered sidewall at the bottom of the dummy material stack. In some embodiments, the third etching process produces a polymer byproduct deposited on the tapered sidewall at the bottom of the dummy material stack. In some embodiments, the first etching process and the second etching process do not produce polymer byproducts. In some embodiments, the first etching process stops at a height above the top surface of the fin. In some embodiments, the height above the top surface of the fin is in a range of about 10 nanometers to about 20 nanometers. In some embodiments, the second etching process stops at the top surface of the fin. In some embodiments, the metal gate stack has a first gate critical dimension (CD) measured at an edge of the fin and a second gate critical dimension measured at a position away from the fin, and the first gate critical dimension is greater than the second gate critical dimension.

[0127] In another exemplary embodiment, the present disclosure relates to a method for forming a semiconductor device, the method comprising forming a fin protruding from a substrate, depositing a dummy electrode layer above the fin, etching the top of the dummy electrode layer in a first etching process to form a first sidewall above the top surface of the fin, etching the bottom of the dummy electrode layer in a second etching process to form a second sidewall below the top surface of the fin, wherein the first etching process and the second etching process use different etching recipes, and the second sidewall tapers from the first sidewall, depositing a gate spacer layer on the first sidewall and the second sidewall of the dummy electrode layer, removing the dummy electrode layer to form a gate trench, and depositing a metal gate stack in the gate trench. In some embodiments, the method further comprises etching a middle portion of the dummy electrode layer in a third etching process after the first etching process and before the second etching process, wherein the first etching process, the second etching process, and the third etching process use different etching recipes. In some embodiments, the third etching process for the middle portion of the dummy electrode layer forms a third sidewall between the first sidewall and the second sidewall, and the third sidewall tapers from the first sidewall. In some embodiments, the second sidewall further tapers from the third sidewall. In some embodiments, the first sidewall is substantially vertical. In some embodiments, the second etching process has an etching strength that is less than an etching strength of the first etching process.

[0128] In yet another illustrative embodiment, the present disclosure relates to a semiconductor device, the structure comprising a substrate, a plurality of channel layers, vertically stacked and suspended above the substrate, and a gate structure, surrounding each of the channel layers, wherein the gate structure has a first gate critical dimension measured at a height above a top surface of a topmost channel layer of the channel layers, a second gate critical dimension measured at an edge of the topmost channel layer of the channel layers, and a third gate critical dimension measured at an edge of a bottommost channel layer of the channel layers, wherein the second gate critical dimension is greater than the first gate critical dimension, and the third gate critical dimension is greater than the second gate critical dimension. In some embodiments, the gate structure comprises a protruding corner located at an intersecting region of the gate structure and the channel layers, and wherein a tip of the protruding corner is above a top surface of a topmost channel layer of the channel layers. In some embodiments, the gate structure comprises a void trapped in the protruding corner. In some embodiments, the gate structure comprises a vertical sidewall terminating above a top surface of a topmost channel layer of the channel layers and a tapered sidewall starting above a top surface of a topmost channel layer of the channel layers.

[0129] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a base; a plurality of channel layers vertically stacked and suspended above the substrate; as well as a gate structure surrounding each of the plurality of channel layers, The gate structure has a first gate critical dimension measured at a height above a top surface of a topmost channel layer of the plurality of channel layers, a second gate critical dimension measured at an edge of the topmost channel layer of the plurality of channel layers, and a third gate critical dimension measured at an edge of a bottommost channel layer of the plurality of channel layers, wherein the second gate critical dimension is greater than the first gate critical dimension, and the third gate critical dimension is greater than the second gate critical dimension.

2. The semiconductor device according to claim 1, wherein The gate structure includes a protruding corner located at an intersection of the gate structure and the plurality of channel layers, wherein a tip of the protruding corner is above the top surface of the topmost channel layer of the plurality of channel layers.

3. The semiconductor device according to claim 2, wherein: The width of the protruding corner is in the range of 0.8 nanometers to 2.8 nanometers.

4. The semiconductor device according to claim 2, wherein: The gate structure includes a void captured in the protruding corner.

5. The semiconductor device according to claim 1, wherein The gate structure includes a vertical sidewall terminating above the top surface of the topmost channel layer of the plurality of channel layers and a tapered sidewall starting above the top surface of the topmost channel layer of the plurality of channel layers.

6. The semiconductor device according to claim 1 or 2, wherein: The height is in the range of 10 nanometers to 20 nanometers.

7. The semiconductor device according to claim 1, wherein The critical dimension of the first gate is in a range of 10 nanometers to 12 nanometers.

8. The semiconductor device according to claim 1, wherein The gate structure includes: a gate dielectric layer surrounding each of the plurality of channel layers; and A gate electrode is disposed on the gate dielectric layer.

9. The semiconductor device according to claim 8, wherein: The gate dielectric layer has a thickness ranging from 0.5 nanometers to 3 nanometers.

10. The semiconductor device according to claim 1, wherein Also includes: A gate spacer layer is disposed on a portion of the sidewall of the gate structure.

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