Display device

Abstract

The display device includes: a bank including an opening overlapping an emission area; and a light emitting element layer disposed on the bank. The light emitting element layer includes a first region and a second region. The first region and the second region of the light emitting element layer are separated from each other in the opening. A thickness of the first region is different from a thickness of the second region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0076251 filed on June 14, 2023 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to display devices and methods of manufacturing display devices. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Utility Model Content

[0005] Embodiments provide a display device capable of improving brightness uniformity of the display device and a method of manufacturing the display device.

[0006] The technical purposes achieved by the present disclosure are not limited to those described herein, and other technical purposes not mentioned herein will be clearly understood by those skilled in the art from the description of the present disclosure.

[0007] According to an aspect of the present disclosure, a display device is provided, comprising: a bank including an opening overlapping an emission region; and a light-emitting element layer disposed on the bank. The light-emitting element layer includes a first region and a second region, the first region and the second region of the light-emitting element layer are separated from each other in the opening, and the thickness of the first region is different from the thickness of the second region.

[0008] The second region may surround the first region.

[0009] The first region may be disposed in the middle of the opening.

[0010] The second region may be in contact with the bank.

[0011] The first region may have a uniform thickness.

[0012] The second region may have a non-uniform thickness.

[0013] The light emitting element layer may include a first layer disposed on the bank and a second layer disposed on the first layer. A thermal expansion coefficient of the first layer may be different from a thermal expansion coefficient of the second layer.

[0014] The second layer may be disposed directly on the first layer.

[0015] The light emitting element layer may further include a third layer disposed on the second layer. The thermal expansion coefficient of the third layer may be different from the thermal expansion coefficient of the second layer.

[0016] The third layer may be disposed directly on the second layer.

[0017] According to another aspect of the present disclosure, a method for manufacturing a display device is provided, the method comprising: forming a dam including an opening above a first electrode; forming a light-emitting element layer in the opening; forming a crack in the light-emitting element layer by baking the light-emitting element layer; and forming a second electrode on the light-emitting element layer.

[0018] The light emitting element layer may include a first region and a second region having thicknesses different from each other.

[0019] The crack may separate the first region and the second region from each other.

[0020] The first region may have a uniform thickness.

[0021] The first region may be formed in the middle of the opening.

[0022] The second region may have a non-uniform thickness.

[0023] The second region may surround the first region.

[0024] Forming the light emitting element layer may include forming a first layer on the first electrode and forming a second layer on the first layer.

[0025] The coefficient of thermal expansion of the first layer may be different than the coefficient of thermal expansion of the second layer.

[0026] Forming the light emitting element layer may further include forming a third layer on the second layer. The third layer may have a thermal expansion coefficient different from that of the second layer.

[0027] According to the present disclosure, adjacent layers of the light emitting element layer are formed of materials having different thermal expansion coefficients, thereby forming cracks inside the light emitting element layer. Therefore, current is blocked in a region where the thickness of the light emitting element layer is uneven, thereby improving brightness uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will convey the scope of the exemplary embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals always refer to the same elements.

[0030] Figure 1 is a schematic perspective view showing a display device according to an embodiment of the present disclosure.

[0031] Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 3 is a schematic plan view showing a display panel according to an embodiment of the present disclosure.

[0033] Figure 4 is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure.

[0034] Figure 5 and Figure 6 It is shown Figure 4 Schematic cross-sectional view of the display element layers shown in .

[0035] Figures 7 to 10 2 is a schematic cross-sectional view showing process steps of a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] By referring to the embodiments described in detail below in conjunction with the accompanying drawings, the effects and features of the present disclosure and the methods for achieving the effects and features will become apparent. However, the present disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms. The embodiments are provided only by way of example so that those of ordinary skill in the art can understand the features and the scope of the present disclosure. Therefore, the present disclosure can be limited by the scope of the appended claims.

[0037] The terms used herein are only used for the purpose of describing specific embodiments and should not be construed as limiting the inventive concept. Unless the context clearly indicates otherwise, otherwise. As used herein, the singular form is intended to also include the plural form. When used in this specification, the terms "include / comprise" and / or "include / comprises" specify the presence of the components, steps, operations and / or elements mentioned, but do not exclude the presence or addition of one or more other components, steps, operations and / or elements.

[0038] When an element is referred to as being "on," "connected to," or "coupled to" another element, it may be directly on, directly connected to, or directly coupled to another element, or there may be intervening elements or layers. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0039] The term "on" used to indicate that an element or layer is on another element or layer includes both the case where the element or layer is directly on another element or layer and the case where the element or layer is on another element or layer via yet another element or layer. Throughout the specification, the same reference numerals generally refer to the same elements.

[0040] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element.

[0041] The term "and / or" includes all combinations of one or more that the relevant configurations can define. For example, "A and / or B" can be understood to mean A, B, or A and B.

[0042] For the purpose of the present disclosure, the phrase "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0043] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0044] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0045] Figure 1 is a schematic perspective view showing a display device according to an embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment of the present disclosure. Figure 3 is a schematic plan view showing a display panel according to an embodiment of the present disclosure.

[0046] refer to Figures 1 to 3 , the display device DD may include a display panel PNL and a window WD.

[0047] The display device DD may include a display area DD_DA in which an image is displayed and a non-display area DD_NDA in which no image is displayed. The non-display area DD_NDA may be disposed at least one side of the display area DD_DA. In an example, the non-display area DD_NDA may be adjacent to the display area DD_DA or surround the display area DD_DA.

[0048] The display device DD may be provided in a rectangular plate shape having angular corners. However, in some embodiments, the corners of the display device DD may have a curved shape. However, the present disclosure is not necessarily limited thereto, and the display device DD may be implemented in various shapes.

[0049] The display device DD can be applied to an electronic device in which a display surface is applied to at least one surface thereof, such as a smart phone, a television, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a medical device, a camera or a wearable device.

[0050] The display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA other than the display area DA. The display area DA may constitute a screen on which an image is displayed, and the non-display area NDA may be other areas other than the display area DA.

[0051] For the convenience of discussion, Figure 3 , the structure of the display panel PNL will be briefly illustrated based on the display area DA. However, in some embodiments, at least one driving circuit (eg, at least one of a scan driver and a data driver), a line and / or a pad may be further disposed in the display panel PNL.

[0052] The pixel unit PXU may be disposed in the display area DA. The pixel unit PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. Hereinafter, in the case of arbitrarily specifying at least one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 or in the case of specifying two or more of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 in an inclusive manner, the corresponding pixel (pixel) or the corresponding plurality of pixels (pixels) will be referred to as "pixel (pixel) PXL" or "pixels (pixels) PXL".

[0053] The pixel PXL can be based on the stripe structure, However, the arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in the display area DA by using various structures and / or methods.

[0054] In some embodiments, two or more of the pixels PXL emit light of different colors. In the example, a first pixel PXL1 emitting light of a first color, a second pixel PXL2 emitting light of a second color, and a third pixel PXL3 emitting light of a third color may be arranged in the display area DA. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 disposed adjacent to each other may constitute a pixel unit PXU capable of emitting light of various colors. For example, the first pixel PXL1 may be a red pixel emitting red light, the second pixel PXL2 may be a green pixel emitting green light, and the third pixel PXL3 may be a blue pixel emitting blue light. However, the present disclosure is not limited thereto. Although the pixel unit PXU includes a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3, in Figure 3 2 is shown as an example, but the present disclosure is not necessarily limited thereto. The pixel unit PXU may include one first pixel PXL1, two second pixels PXL2, and one third pixel PXL3.

[0055] The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may each have a first light emitting element ( Figure 4 LD1 shown in FIG), the second light emitting element ( Figure 4 LD2) and the third light emitting element ( Figure 4 LD3 shown in FIG. 1 ) is used to emit light of a first color, light of a second color, and light of a third color. However, the color of light emitted from each pixel PXL may be variously changed.

[0056] A window WD for protecting an exposed surface of the display panel PNL may be provided on the display panel PNL. The window WD may protect the display panel PNL from external impacts and provide an input surface and / or a display surface to a user. The window WD may be bonded to the display panel PNL by using an optically transparent adhesive (or sticky) member (not shown).

[0057] The window WD may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The multilayer structure may be formed by a continuous process or an adhesive process using an adhesive layer. The entirety or a portion of the window WD may have flexibility.

[0058] Figure 4 is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure. Figure 5 and Figure 6 It is shown Figure 4 Schematic cross-sectional view of the display element layers shown in .

[0059] refer to Figure 4 , each of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 may include an emission area EMA, and the non-emission area NEMA may be located between the emission areas EMA of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 .

[0060] Each of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 may include a pixel circuit layer PCL, a display element layer DPL, and a thin film encapsulation layer TFE sequentially disposed on a substrate SUB.

[0061] The substrate SUB may form a base surface. The substrate SUB may include a transparent insulating material to allow light to pass through it. The substrate SUB may be a rigid substrate or a flexible substrate. The rigid substrate may be, for example, at least one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate. The flexible substrate may be at least one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the present disclosure is not limited thereto.

[0062] The pixel circuit layer PCL may include a pixel circuit disposed on the substrate SUB. The pixel circuit layer PCL may include a sensor circuit disposed on the substrate SUB.

[0063] The pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and / or a via layer VIA sequentially stacked on the substrate SUB along a third direction (Z-axis direction).

[0064] The buffer layer BFL may be an inorganic insulating layer including an inorganic material. The buffer layer BFL may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ). The buffer layer BFL may be provided as a single layer, but may be provided as a multilayer including at least two layers. In the case where the buffer layer BFL is provided as a multilayer, the layers may be formed of the same material or of different materials. The buffer layer BFL may be omitted depending on the material of the substrate SUB, process conditions, etc.

[0065] The transistor T may be disposed on the buffer layer BFL. The transistor T may include an active pattern ACT, a gate electrode GE, a first transistor electrode TE1, and / or a second transistor electrode TE2.

[0066] The active pattern ACT may be disposed on the buffer layer BFL. The active pattern ACT may include a polysilicon semiconductor. For example, the active pattern ACT may be formed by a low temperature polysilicon process. However, the present disclosure is not necessarily limited thereto, and the active pattern ACT may be formed of an oxide semiconductor, a metal oxide semiconductor, or the like.

[0067] Each active pattern ACT may include a channel region, a first contact region connected to one end of the channel region, and / or a second contact region connected to the other end of the channel region. The channel region, the first contact region, and the second contact region may be formed by a semiconductor layer that is not doped with impurities or doped with impurities. In an example, the first contact region and the second contact region may be formed by a semiconductor layer doped with impurities, and the channel region may be formed by a semiconductor layer that is not doped with impurities. The impurities may include p-type impurities, but the present disclosure is not limited thereto. One of the first contact region and the second contact region may be a source region, and the other of the first contact region and the second contact region may be a drain region.

[0068] The gate insulating layer GI may be disposed throughout (or on) the active pattern ACT. The gate insulating layer GI may be an inorganic layer (or an inorganic insulating layer) including an inorganic material. In an example, the gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) is at least one of metal oxides of the present invention. However, the material of the gate insulating layer GI is not limited to the above-mentioned embodiments. In some embodiments, the gate insulating layer GI may be an organic layer (or organic insulating layer) including an organic material. The gate insulating layer GI may be provided as a single layer, but may be provided as a multilayer including at least two layers.

[0069] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the channel region of the active pattern ACT. The gate electrode GE may be formed as a single layer including one selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and any alloy thereof (such as aluminum neodymium (AlNd)) or a mixture thereof, or formed as a double-layer structure or a multi-layer structure including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low resistance material to reduce wiring resistance.

[0070] The interlayer insulating layer ILD may be disposed over the gate electrode GE. The interlayer insulating layer ILD and the gate insulating layer GI may include the same material. In an alternative, the interlayer insulating layer ILD may include at least one material selected from, for example, the materials discussed herein regarding the materials constituting the gate insulating layer GI.

[0071] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on the interlayer insulating layer ILD.

[0072] The first transistor electrode TE1 of the transistor T may contact the first contact region of the active pattern ACT through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI. In the case where the first contact region is a source region, the first transistor electrode TE1 may be a first source electrode.

[0073] The second transistor electrode TE2 of the transistor T may contact or be in contact with the second contact region of the active pattern ACT through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI. In the case where the first contact region is a drain region, the first transistor electrode TE1 may be a second drain electrode.

[0074] Each of the first and second transistor electrodes TE1 and TE2 and the gate electrode GE may include the same material. In the alternative, each of the first and second transistor electrodes TE1 and TE2 may include at least one material selected from, for example, the materials discussed herein regarding materials constituting the gate electrode GE.

[0075] The passivation layer PSV may be disposed over the first transistor electrode TE1 and the second transistor electrode TE2. The passivation layer PSV (eg, a protective layer) may be an inorganic layer (or an inorganic insulating layer) including an inorganic material or an organic layer (or an organic insulating layer) including an organic material. The inorganic layer may include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x The organic layer may include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and benzocyclobutene resin.

[0076] In some embodiments, the passivation layer PSV and the interlayer insulating layer ILD may include the same material, but the present disclosure is not limited thereto. The passivation layer PSV may be provided as a single layer, but may be provided as a multilayer including at least two layers.

[0077] The via layer VIA may be disposed on the passivation layer PSV. The via layer VIA and the passivation layer PSV may include the same material. In an alternative, the via layer VIA may include at least one material selected from the materials discussed herein for materials constituting the passivation layer PSV.

[0078] The display element layer DPL may be disposed on the pixel circuit layer PCL.

[0079] The display element layer DPL may include a light emitting element LD that emits light. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3, respectively.

[0080] The first light emitting element LD1 may include a first electrode AE, a first light emitting element layer EML1, and a second electrode CE. The second light emitting element LD2 may include a first electrode AE, a second light emitting element layer EML2, and a second electrode CE. The third light emitting element LD3 may include a first electrode AE, a third light emitting element layer EML3, and a second electrode CE. In an example, each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be a top emission organic light emitting element.

[0081] The first electrode AE ​​of each pixel PXL may be disposed in the emission area EMA and may be spaced apart from each other. The first electrode AE ​​of each pixel PXL may be electrically connected to the first transistor electrode TE1 of the transistor T of the corresponding pixel PXL.

[0082] The bank PDL may be disposed on the first electrode AE. The bank PDL may define (or divide) the emission area EMA of each pixel PXL. The bank PDL may include an opening partially exposing the first electrode AE ​​of each pixel PXL. The opening of the bank PDL may overlap the emission area EMA of each pixel PXL.

[0083] The bank PDL may be an organic insulating layer made of an organic material, such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0084] In some embodiments, the bank PDL may include a light absorbing material, or have a light absorber applied thereon to absorb light introduced from the outside. For example, the bank PDL may include a carbon-based black pigment. However, the present disclosure is not necessarily limited thereto, and the bank PDL may include an opaque metal material with high light absorption such as chromium (Cr), molybdenum (Mo), an alloy of molybdenum and titanium (MoTi), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), or nickel (Ni).

[0085] The light emitting element layer EML of each pixel PXL may be disposed on the first electrode AE ​​exposed by the bank PDL. Figure 5 and Figure 6 The light emitting element layer EML is described in detail.

[0086] refer to Figure 5 and Figure 6 , the light emitting element layer EML may be disposed in the opening of the bank PDL. The light emitting element layer EML may include a first region A1 and a second region A2 separated from each other in the opening of the bank PDL. The first region A1 of the light emitting element layer EML may be disposed in the middle of the opening of the bank PDL. In an example, the first region A1 of the light emitting element layer EML may be a region in which the thickness of the light emitting element layer EML is uniform or the light emitting element layer EML has a uniform thickness.

[0087] The second area A2 of the light emitting element layer EML may surround the first area A1. The second area A2 of the light emitting element layer EML may be disposed at an edge of an opening of the embankment PDL to contact the embankment PDL. In an example, the second area A2 of the light emitting element layer EML may be an area in which the thickness of the light emitting element layer EML is uneven or the light emitting element layer EML has an uneven thickness. In an embodiment, the thickness t2 of the second area A2 of the light emitting element layer EML may be different from the thickness t1 of the first area A1 of the light emitting element layer EML. The thickness t2 of the second area A2 of the light emitting element layer EML may be thicker (or larger) than the thickness t1 of the first area A1 of the light emitting element layer EML, but the present disclosure is not necessarily limited thereto.

[0088] As described above, in the case where the thickness t2 of the second region A2 of the light emitting element layer EML is formed unevenly, the light emitting element layer EML may emit light unevenly in the second region A2. Therefore, since the first region A1 of the light emitting element layer EML is separated from the second region A2 of the light emitting element layer EML, the current in the second region A2 is blocked, thereby improving the brightness uniformity. In the example, the first region A1 and the second region A2 of the light emitting element layer EML may be separated from each other by the crack CR.

[0089] like Figure 5As shown in , the crack CR can completely separate the first area A1 and the second area A2 of the light emitting element layer EML from each other. In the example, in the case where the light emitting element layer EML includes a first layer L1, a second layer L2, a third layer L3, a fourth layer L4, and a fifth layer L5 sequentially stacked therein, the crack CR can be formed in all of the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 to completely separate the first area A1 and the second area A2 of the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 from each other.

[0090] like Figure 6 As shown in , the crack CR can partially separate the first area A1 and the second area A2 of the light emitting element layer EML from each other. In the example, in the case where the light emitting element layer EML includes a first layer L1, a second layer L2, a third layer L3, a fourth layer L4, and a fifth layer L5 sequentially stacked therein, the crack CR can be formed in some of the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 to partially separate the first area A1 and the second area A2 of the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 from each other. Although in Figure 6 2A and 2B illustrate, as an example, a case in which the crack CR is partially formed in the first layer L1 , the second layer L2 , and the third layer L3 , but the present disclosure is not necessarily limited thereto.

[0091] The first layer L1 may be disposed on the first electrode AE ​​and the bank PDL. The first layer L1 may be disposed directly on the first electrode AE ​​and the bank PDL. In an example, the first layer L1 may be a hole injection layer, but the present disclosure is not necessarily limited thereto.

[0092] The second layer L2 may be disposed on the first layer L1. The second layer L2 may be disposed directly on the first layer L1. In an example, the second layer L2 may be a hole transport layer, but the present disclosure is not necessarily limited thereto. In an embodiment, the thermal expansion coefficient of the second layer L2 may be different from the thermal expansion coefficient of the first layer L1. Therefore, in a case where adjacent layers of the light emitting element layer EML are formed of materials having different thermal expansion coefficients, a crack CR may be formed inside the light emitting element layer EML due to thermal expansion when baking is performed at a high temperature. The crack CR of the light emitting element layer EML may be formed between the first area A1 and the second area A2 to block the current in the second area A2, thereby improving brightness uniformity.

[0093] The third layer L3 may be disposed on the second layer L2. The third layer L3 may be disposed directly on the second layer L2. In an embodiment, the thermal expansion coefficient of the third layer L3 may be different from the thermal expansion coefficient of the second layer L2. In an example, the third layer L3 may be a light emitting layer, but the present disclosure is not necessarily limited thereto.

[0094] The fourth layer L4 may be disposed on the third layer L3. The fourth layer L4 may be disposed directly on the third layer L3. In an embodiment, the thermal expansion coefficient of the fourth layer L4 may be different from the thermal expansion coefficient of the third layer L3. In an example, the fourth layer L4 may be an electron transport layer, but the present disclosure is not necessarily limited thereto.

[0095] The fifth layer L5 may be disposed on the fourth layer L4. The fifth layer L5 may be disposed directly on the fourth layer L4. In an embodiment, the thermal expansion coefficient of the fifth layer L5 may be different from the thermal expansion coefficient of the fourth layer L4. In an example, the fifth layer L5 may be an electron injection layer, but the present disclosure is not necessarily limited thereto.

[0096] Although in Figure 5 and Figure 6 , the light emitting element layer EML includes a first layer L1, a second layer L2, a third layer L3, a fourth layer L4 and a fifth layer L5 as an example, but the present disclosure is not necessarily limited thereto. In the example, the light emitting element layer EML may further include a layer including an electron blocking layer and / or a hole blocking layer.

[0097] The second electrode CE may be disposed on the light emitting element layer EML. The second electrode CE may be disposed throughout all of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. In an example, the second electrode CE may be disposed as a common electrode, but the present disclosure is not necessarily limited thereto.

[0098] The second electrode CE may be configured with a metal layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or any alloy thereof and / or a transparent conductive layer such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO). In some embodiments, the second electrode CE may be configured as a multilayer including at least two layers including a metal thin layer. For example, the second electrode CE may be configured as a triple layer of ITO / Ag / ITO.

[0099] The thin film encapsulation layer TFE may be disposed on the display element layer DPL. The thin film encapsulation layer TFE may have a single-layer structure or a multi-layer structure. The thin film encapsulation layer TFE may include an insulating layer covering the light emitting element LD. The thin film encapsulation layer TFE may include at least one of an inorganic layer and an organic layer. For example, the thin film encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the thin film encapsulation layer TFE may have a structure in which inorganic layers and organic layers are alternately stacked. In some embodiments, the thin film encapsulation layer TFE may be an encapsulation substrate disposed throughout the light emitting element LD to be bonded to the substrate SUB through a sealant.

[0100] The sensing layer TS may be disposed on the thin film encapsulation layer TFE. The sensing layer TS may include a first insulating layer INS1, a first sensing conductive layer MT1, a second insulating layer INS2, a second sensing conductive layer MT2 and / or a third insulating layer INS3.

[0101] The first insulating layer INS1 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), titanium oxide (TiO x ), Tantalum Oxide (Ta x O y ), hafnium oxide (HfO x ) or zinc oxide (ZnO x ) inorganic insulating material. The organic insulating layer may include at least one of an acryl-based resin, a methacryl-based resin, polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin. However, the present disclosure is not necessarily limited thereto. The first insulating layer INS1 may be omitted in some embodiments, or may be configured as the uppermost layer of the thin film encapsulation layer TFE.

[0102] The first sensing conductive layer MT1 may be disposed on the first insulating layer INS1. The first sensing conductive layer MT1 may be partially opened without overlapping the light emitting element LD of each pixel PXL. In an example, the first sensing conductive layer MT1 may be disposed to overlap the non-emission area NEMA at the periphery of the emission area EMA.

[0103] The first sensing conductive layer MT1 may include a metal layer or a transparent conductive layer. For example, the metal layer may include at least one of molybdenum, titanium, copper, aluminum, and alloys thereof. The transparent conductive layer may include, for example, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, and metal nanowires, but the present disclosure is not necessarily limited thereto. The first sensing conductive layer MT1 may form a connection electrode that connects the sensing electrodes to each other.

[0104] The second insulating layer INS2 may be disposed on the first sensing conductive layer MT1. The second insulating layer INS2 and the first insulating layer INS1 may include the same material. In an alternative solution, the second insulating layer INS2 may include at least one material selected from the materials discussed herein for materials constituting the first insulating layer INS1.

[0105] The second sensing conductive layer MT2 may be disposed on the second insulating layer INS2. The second sensing conductive layer MT2 may be partially opened without overlapping the light emitting element LD of each pixel PXL. In an example, the second sensing conductive layer MT2 may be disposed to overlap the non-emission area NEMA at the periphery of the emission area EMA.

[0106] The second sensing conductive layer MT2 and the first sensing conductive layer MT1 may include the same material. In an alternative solution, the second sensing conductive layer MT2 may include at least one material selected from, for example, the materials discussed herein with respect to the materials constituting the first sensing conductive layer MT1.

[0107] The second sensing conductive layer MT2 may be electrically connected to the first sensing conductive layer MT1 through a contact hole passing through the second insulating layer INS2 . The second sensing conductive layer MT2 may form a sensing electrode.

[0108] The third insulating layer INS3 may be disposed on the second sensing conductive layer MT2. The third insulating layer INS3 may include an organic layer, but the present disclosure is not necessarily limited thereto. In some embodiments, the third insulating layer INS3 may be formed of an inorganic layer, or have a structure in which an organic layer and an inorganic layer are alternately stacked.

[0109] The light blocking layer LBP may be disposed on the display element layer DPL, the thin film encapsulation layer TFE and / or the sensing layer TS. The light blocking layer LBP may include an opening overlapping with the light emitting element LD of each pixel PXL. In an example, the light blocking layer LBP may be disposed to overlap with the non-emitting area NEMA at the periphery of the emission area EMA.

[0110] The light blocking layer LBP may include a light blocking material to prevent light leakage and color mixing. In an example, the light blocking layer LBP may include a black matrix (BM), but the present disclosure is not necessarily limited thereto. In some embodiments, the light blocking layer LBP may include carbon black (CB) and / or titanium black (TiBK).

[0111] The color filter layer CFL may be disposed on the light blocking layer LBP. The color filter layer CFL may include color filters CF1, CF2, and CF3 that are consistent with the colors of the corresponding pixels PXL. The color filters CF1, CF2, and CF3 that are consistent with the colors of the corresponding first, second, and third pixels PXL1, PXL2, and PXL3 are disposed so that a full-color image may be displayed.

[0112] The color filter layer CFL may include a first color filter CF1 disposed in the first pixel PXL1 to allow light emitted from the first pixel PXL1 to selectively pass therethrough, a second color filter CF2 disposed in the second pixel PXL2 to allow light emitted from the second pixel PXL2 to selectively pass therethrough, and a third color filter CF3 disposed in the third pixel PXL3 to allow light emitted from the third pixel PXL3 to selectively pass therethrough.

[0113] In an embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red filter, a green filter, and a blue filter, respectively, but the present disclosure is not necessarily limited thereto. Hereinafter, in the case of specifying any color filter of the first color filter CF1, the second color filter CF2, and the third color filter CF3, or in the case of specifying two or more color filters in an inclusive manner, the corresponding color filter or the corresponding multiple color filters are referred to as "color filter CF" or "multiple color filters CF".

[0114] The first color filter CF1 may include a color filter material for allowing light of a first color (or red) to selectively pass therethrough. For example, in the case where the first pixel PXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0115] The second color filter CF2 may include a color filter material for allowing light of the second color (or green) to selectively pass therethrough. For example, in the case where the second pixel PXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0116] The third color filter CF3 may include a color filter material for allowing light of a third color (or blue) to selectively pass therethrough. For example, in the case where the third pixel PXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0117] The window WD may be disposed on the color filter layer CFL. The window WD may protect the lower member from external impact and provide an input surface and / or a display surface to a user.

[0118] According to the above embodiment, adjacent layers of the light emitting element layer EML are formed of materials having different thermal expansion coefficients, thereby forming cracks CR inside the light emitting element layer EML. Therefore, current is blocked in the second area A2 where the thickness of the light emitting element layer EML is uneven, thereby improving brightness uniformity.

[0119] Hereinafter, a method of manufacturing a display device according to the above-described embodiment will be described.

[0120] Figures 7 to 10 2 is a schematic cross-sectional view showing process steps of a method of manufacturing a display device according to an embodiment of the present disclosure. Figures 7 to 9 It shows the manufacturing Figure 5 A cross-sectional view of a method of displaying a device as shown in FIG. Fig.10 It shows the manufacturing Figure 6 Schematic cross-sectional view of a method of displaying a device shown in . To facilitate discussion, components substantially the same as those described above are denoted by the same reference numerals, and detailed reference numerals are omitted.

[0121] refer to Figure 7 First, a first electrode AE ​​is formed, and a bank PDL is formed over the first electrode AE. The bank PDL may include an opening partially exposing the first electrode AE. The bank PDL may cover an edge of the first electrode AE.

[0122] The bank PDL may be formed of an organic material. In an example, the bank PDL may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc., but the present disclosure is not necessarily limited thereto.

[0123] In some embodiments, the bank PDL may be formed of a light absorbing material, or have a light absorber applied thereon to absorb light introduced from the outside. For example, the bank PDL may be formed of a carbon-based black pigment. However, the present disclosure is not necessarily limited thereto, and the bank PDL may be formed of an opaque metal material having a high light absorption rate such as chromium (Cr), molybdenum (Mo), an alloy of molybdenum and titanium (MoTi), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), or nickel (Ni).

[0124] refer to Figure 8, then, a light emitting element layer EML is formed on the first electrode AE. The light emitting element layer EML may be formed in the opening of the embankment PDL. The light emitting element layer EML may be formed by inkjet printing, but the present disclosure is not necessarily limited thereto. The thickness of the light emitting element layer EML may be partially unevenly formed in the process of printing the light emitting element layer EML in the opening of the embankment PDL. In an example, the thickness t1 of the first region A1 of the light emitting element layer EML may be uniformly formed. The first region A1 of the light emitting element layer EML may be located in the middle of the opening of the embankment PDL. The thickness t2 of the second region A2 of the light emitting element layer EML may be different from the thickness t1 of the first region A1 of the light emitting element layer EML. The thickness t2 of the second region A2 of the light emitting element layer EML may be thicker than the thickness t1 of the first region A1 of the light emitting element layer EML, but the present disclosure is not necessarily limited thereto. The second region A2 of the light emitting element layer EML may be located at the edge of the opening of the embankment PDL. The second region A2 of the light emitting element layer EML may surround the first region A1 of the light emitting element layer EML.

[0125] A first layer L1, a second layer L2, a third layer L3, a fourth layer L4, and a fifth layer L5 of the light emitting element layer EML may be sequentially stacked on the first electrode AE. The first layer L1 may be formed on the first electrode AE ​​and the bank PDL. The first layer L1 may be formed directly on the first electrode AE ​​and the bank PDL. In an example, the first layer L1 may be a hole injection layer, but the present disclosure is not necessarily limited thereto.

[0126] The second layer L2 may be formed on the first layer L1. The second layer L2 may be formed directly on the first layer L1. In an embodiment, the thermal expansion coefficient of the second layer L2 may be different from the thermal expansion coefficient of the first layer L1. In an example, the second layer L2 may be a hole transport layer, but the present disclosure is not necessarily limited thereto.

[0127] The third layer L3 may be formed on the second layer L2. The third layer L3 may be formed directly on the second layer L2. In an embodiment, the thermal expansion coefficient of the third layer L3 may be different from the thermal expansion coefficient of the second layer L2. In an example, the third layer L3 may be a light emitting layer, but the present disclosure is not necessarily limited thereto.

[0128] The fourth layer L4 may be formed on the third layer L3. The fourth layer L4 may be formed directly on the third layer L3. In an embodiment, the thermal expansion coefficient of the fourth layer L4 may be different from the thermal expansion coefficient of the third layer L3. In an example, the fourth layer L4 may be an electron transport layer, but the present disclosure is not necessarily limited thereto.

[0129] The fifth layer L5 may be formed on the fourth layer L4. The fifth layer L5 may be formed directly on the fourth layer L4. In an embodiment, the thermal expansion coefficient of the fifth layer L5 may be different from the thermal expansion coefficient of the fourth layer L4. In an example, the fifth layer L5 may be an electron injection layer, but the present disclosure is not necessarily limited thereto.

[0130] Although in Figure 8 , the light emitting element layer EML includes a first layer L1, a second layer L2, a third layer L3, a fourth layer L4 and a fifth layer L5 as an example, but the present disclosure is not necessarily limited thereto. In the example, the light emitting element layer EML may further include a layer including an electron blocking layer and / or a hole blocking layer.

[0131] refer to Fig. 9 and Fig.10 , and then, a crack CR is formed in the light emitting element layer EML by baking the light emitting element layer EML. As described above, in the case where adjacent layers of the light emitting element layer EML are formed of materials having different thermal expansion coefficients, a crack CR may be formed inside the light emitting element layer EML due to thermal expansion when baking is performed at a high temperature. The crack CR of the light emitting element layer EML is formed between the first region A1 and the second region A2 to separate the first region A1 and the second region A2 from each other.

[0132] like Fig. 9 As shown in , the crack CR can completely separate the first area A1 and the second area A2 of the light emitting element layer EML from each other. In the example, the crack CR can be formed in all of the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 to completely separate the first area A1 and the second area A2 of the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 from each other.

[0133] like Fig.10 As shown in , the crack CR can partially separate the first area A1 and the second area A2 of the light emitting element layer EML from each other. In the example, the crack CR can be formed in some of the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 to partially separate the first area A1 and the second area A2 of the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 from each other. Although in Fig.10 2A and 2B illustrate a case where cracks CR are partially formed in the first layer L1 , the second layer L2 , and the third layer L3 as an example, but the present disclosure is not necessarily limited thereto.

[0134] Subsequently, a second electrode CE is formed on the light emitting element layer EML, thereby completing Figure 5 or Figure 6 The display device DD shown in .

[0135] According to the above embodiment, adjacent layers of the light emitting element layer EML are formed of materials having different thermal expansion coefficients, thereby forming cracks CR inside the light emitting element layer EML. Therefore, current is blocked in the second region A2 where the thickness of the light emitting element layer EML is uneven, thereby improving brightness uniformity.

[0136] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure and as set forth in the appended claims.

Claims

1. A display device, characterized in that include: a dike including an opening overlapping the launch area; as well as A light emitting element layer is provided on the bank, wherein: The light emitting element layer includes a first region and a second region, The first region and the second region of the light emitting element layer are separated from each other in the opening, and The thickness of the first region is different from the thickness of the second region.

2. The display device according to claim 1, characterized in that The second area surrounds the first area.

3. The display device according to claim 1, characterized in that The first area is disposed in the middle of the opening.

4. The display device according to claim 1, characterized in that The second region is in contact with the bank.

5. The display device according to claim 1, characterized in that The first region has a uniform thickness.

6. The display device according to claim 1, characterized in that: The second region has a non-uniform thickness.

7. The display device according to claim 1, characterized in that: The light emitting element layer includes a first layer provided on the bank and a second layer provided on the first layer, and The first layer has a coefficient of thermal expansion that is different from a coefficient of thermal expansion of the second layer.

8. The display device according to claim 7, characterized in that: The second layer is disposed directly on the first layer.

9. The display device according to claim 7, characterized in that: The light emitting element layer further includes a third layer disposed on the second layer, and The coefficient of thermal expansion of the third layer is different from the coefficient of thermal expansion of the second layer.

10. The display device according to claim 9, characterized in that: The third layer is disposed directly on the second layer.

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