Daisy chain communication control circuit, integrated circuit chip and daisy chain communication system

Abstract

The utility model discloses a daisy chain communication control circuit, an integrated circuit chip and a daisy chain communication system, wherein the control circuit includes: a data signal interface, a command signal interface and / or a clock signal interface; a short-circuit transmission path, which is arranged between the input end and the output end of the data signal interface; when the short-circuit transmission path is turned on, a data signal with a frequency adjustment command is received, and the instruction of the data signal is executed in response to the clock pulse signal or the CMD command signal. This scheme sets a short-circuit transmission path inside the control circuit, and uses one of the command signal interface or the clock signal interface to cooperate with the data signal interface to execute the instruction of the data signal when the short-circuit transmission path is turned on. It only needs to configure one piece of data information to perform differential configuration on multiple slaves, which greatly reduces the transmission amount of communication data.

Description

Technical Field

[0001] The utility model relates to the technical field of electrical digital data processing, in particular to a daisy chain communication control circuit, an integrated circuit chip and a daisy chain communication system. Background Art

[0002] like Figure 1 As shown in the figure, in traditional keyboard design, in order to achieve communication between multiple keyboard chips, multiple chip select (CS) pins are often used to control each chip individually to control the brightness and color of the keyboard LED light. The microcontroller (host) sends commands to each slave device through a serial clock output (SCLK) and a master output / slave input (MOSI) signal line. The host assigns an independent chip select signal (SS) to each slave, thereby achieving independent addressing of each slave. Since all slaves share the same clock and data lines, only slaves with CS enable input will respond to the serial clock and data lines. When the number of slaves is small, the system is easier to implement. If the number of slaves in the system is large, the microcontroller needs to provide the same number of SS outputs as the slaves, and this structure increases the complexity of hardware and layout. This design not only occupies a large amount of IO resources, but also as the complexity of the keyboard increases, the hardware design becomes more complex and the scalability is also limited.

[0003] like Figure 2 As shown in the figure, the daisy chain method can be used to replace the serial interface, and the daisy chain communication technology is used to control the brightness and color of the LED lights of the keyboard. Daisy chain communication is a serial communication method. The daisy chain structure usually includes a master device (Master) / host (with a master chip) and multiple slave devices (Slave) / slaves (with cascade chips). All slaves receive the same clock signal. Only the first slave (slave 1) in the chain receives commands directly from the host. All other slaves obtain their input data from the output of the previous slave in the chain. The host is responsible for sending data and control signals, and the slaves receive and transmit these data in turn. Multiple slaves are connected in turn through a single communication link to form a chain structure. Each slave input is connected to the output of the previous slave and passes the data to the input of the next slave. In this way, data is transmitted from the starting point to the end point of the chain, passing through each slave in turn. In the keyboard, the cascade chip of each slave receives and transmits data in turn, thereby realizing the control of each or each group of LEDs.

[0004] However, this communication method has some disadvantages. Since each cascade chip receives data at different times, the time interval between the first cascade chip and the last cascade chip in the chain receiving data may be longer. Since the data needs to pass through each slave in turn, the later slaves in the chain will receive data later than the previous slaves, which may cause delay accumulation, which will lead to poor overall keyboard LED control. In addition, when different LEDs or different groups of LEDs are required to display different colors and brightness, the corresponding slaves need to receive and process specific / different configuration information / instructions separately, which usually increases the number of communications and the amount of communication data transmitted is large. Utility Model Content

[0005] According to one aspect of the utility model, there is provided a daisy chain communication control circuit, comprising: a data signal interface, a command signal interface and / or a clock signal interface;

[0006] The clock signal interface is used to receive a clock pulse signal sent by the host;

[0007] The command signal interface is used to receive a CMD command signal sent by the host;

[0008] The data signal interface is used to receive a data signal sent by the host;

[0009] The control circuit includes a short-circuit transmission path, which is arranged between the input end and the output end of the data signal interface;

[0010] When the short-circuit transmission path is turned on:

[0011] The data signal with the frequency adjustment command is received, and the instruction of the data signal is executed in response to the clock pulse signal or the CMD command signal.

[0012] In some embodiments, it further includes a data processing unit, a clock unit, and a counting unit;

[0013] The data processing unit is connected to the clock unit and the data signal interface, performs initialization settings after receiving the data signal, and selects to conduct the short-circuit transmission path or the receiving instruction path;

[0014] When the short-circuit transmission path is turned on,

[0015] The clock unit receives data information with a frequency adjustment command in the data signal sent by the host, and generates a specific clock signal according to the frequency adjustment command;

[0016] The counting unit receives a clock pulse signal or a CMD command signal, counts the specific clock signal within its pulse period and sends the count value to the data processing unit, and the data processing unit executes the instruction of the data signal according to the count value.

[0017] In some embodiments, the clock unit includes a first internal clock and a frequency conversion unit electrically connected to the first internal clock, the frequency conversion unit receives data information with a frequency adjustment command in the data signal sent by the host, and generates the specific clock signal based on the clock frequency of the first internal clock.

[0018] In some embodiments, the frequency conversion unit includes a frequency divider or a frequency multiplier.

[0019] In some implementations, the first internal clock comprises a programmable clock.

[0020] In some embodiments, the counting unit is connected to the clock signal interface to receive a clock pulse signal, and counts the specific clock signal within a pulse period of the clock pulse signal and sends the count value to the data processing unit.

[0021] In some embodiments, the counting unit is connected to the command signal interface to receive a CMD command signal, and counts the specific clock signal within a pulse period of the CMD command signal and sends the count value to the data processing unit.

[0022] In some embodiments, the clock unit includes a timing unit and a frequency conversion unit electrically connected to the timing unit, the timing unit generates a second internal clock according to the clock pulse signal after receiving the clock pulse signal sent by the host, the frequency conversion unit receives the data information with the frequency adjustment command in the data signal sent by the host, and generates the specific clock signal based on the clock frequency of the second internal clock.

[0023] In some implementations, the clock unit is connected to the data signal interface or the data processing unit to receive data information carrying a frequency adjustment command in the data signal.

[0024] According to a second aspect of the present invention, there is provided an integrated circuit chip for controlling the brightness and / or color of an indicator light of a keyboard, comprising any one of the above-mentioned daisy chain communication control circuits. According to a third aspect of the present invention, there is provided a daisy chain communication system, comprising:

[0025] Host;

[0026] At least one slave, the slave comprising: the daisy chain communication control circuit as described in any one of the above items.

[0027] Beneficial effects of the utility model: The scheme of the utility model sets a short-circuit transmission path inside the control circuit, and uses one of the command signal interface or the clock signal interface to cooperate with the data signal interface to execute the data signal instruction when the short-circuit transmission path is turned on. In this way, only one piece of data information needs to be configured to differentiate multiple slaves, so that the keyboard indicator lights display different brightness and / or colors. There is no need to configure the data information for each slave separately and repeatedly transmit it, which greatly reduces the transmission volume of communication data. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of a control circuit in the prior art;

[0029] Figure 2 It is a structural schematic diagram of a daisy chain communication system in the prior art;

[0030] Figure 3 It is a structural schematic diagram of a daisy chain communication system of the utility model;

[0031] Figure 4 It is a schematic diagram of the structure of the control circuit of daisy chain communication in some embodiments of the utility model;

[0032] Figure 5 A schematic diagram of connecting a daisy chain communication control circuit and a host in some embodiments of the present invention;

[0033] Figure 6 The waveform diagrams of the CMD command signal and the specific clock signals of different slaves in some embodiments of the present utility model;

[0034] Figure 7 It is a structural schematic diagram of a daisy chain communication control circuit of other embodiments of the utility model;

[0035] Figure 8 The waveform diagrams of CMD command signals and specific clock signals of different slaves in other embodiments of the present utility model;

[0036] Fig. 9 It is a structural schematic diagram of a daisy chain communication control circuit of some other embodiments of the utility model;

[0037] Fig.10 It is a structural schematic diagram of a daisy chain communication control circuit of some other embodiments of the utility model;

[0038] Fig.11 Waveform diagrams of clock pulse signals and specific clock signals of different slaves in some embodiments of the present utility model;

[0039] Fig.12Schematic diagram of the structure of the daisy chain communication control circuit of some other embodiments of the utility model. DETAILED DESCRIPTION

[0040] For better understanding and implementation, the technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The terms "including" and "having" and any variations of the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to these processes, methods, products or devices.

[0042] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0043] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0044] According to the first aspect of the utility model, Figure 4 The daisy chain communication control circuit according to one embodiment of the present invention is schematically shown. The control circuit can be used to control the indicator light (LED light) on the keyboard, including but not limited to controlling the brightness and color of the LED light. Figure 3As shown, the control circuit can be integrated into multiple cascade chips (slave chips) of the keyboard. The control of the LED lights on the keyboard and the sampling and transmission of the key signals of the keys on the keyboard are all realized by multiple cascade chips as slaves and the keyboard main control chip as the host. The main control chip includes but is not limited to MCU (microcontroller unit), FPGA (field programmable gate array), DSP (digital signal processor), SoC (system on chip), ASIC (application-specific integrated circuit), ARM processor; wherein each slave controls one or more, one or more groups of LED lights, and multiple slaves are connected to the host through a daisy chain.

[0045] like Figure 4 As shown, the daisy chain communication control circuit includes a data signal interface, a command signal interface CMD, a clock signal interface CLK, a data processing unit 10 , a clock unit 20 and a counting unit 30 .

[0046] like Figure 4 As shown, the clock signal interface CLK is used to receive the clock pulse signal (external clock) sent by the host; the clock pulse signal is used to synchronize data transmission, and all slaves connected to the daisy chain will send and receive data according to the beat of the clock pulse signal. The clock pulse signal is used for synchronization, and the host and the slave can exchange data in the same clock cycle to ensure the accuracy and consistency of data transmission. The clock signal interface CLK is connected to the data processing unit 10.

[0047] like Figure 4 As shown, the command signal interface CMD is used to receive the CMD command signal sent by the host; the CMD (Command) command signal is usually used to transmit command and control information. In a daisy chain structure, the CMD command signal can be used to control the operation of all slaves in the chain, such as starting, stopping or configuring the slave. The CMD command signal is usually broadcast, and all slaves connected to the daisy chain will receive the same command.

[0048] like Figure 4 As shown, the data signal interface is connected to the data processing unit 10, and is used to receive the data signal sent by the host. The data signal interface includes a data signal input terminal SDI and a data signal output terminal SDO. The data signal input terminal SDI is used to receive serial data. The data signal input terminal SDI of the first slave in the chain is connected to the host, and its data signal output terminal SDO is connected to the data signal input terminal SDI of the next slave. During the data signal transmission process, the data signal interface is responsible for transferring the data signal from one slave to the next slave, and is mainly used to transmit the actual data content, such as sensor readings, image data, etc. And further transmit the data information to the data processing unit 10. In this application, the data transmitted by the data signal interface includes sensor data generated by pressing a button.

[0049] like Figure 4 As shown, the data processing unit 10 is connected to the clock signal interface CLK and the data signal interface, and the data processing unit 10 receives the clock pulse signal through the clock signal interface CLK to achieve synchronization. The data processing unit 10 includes but is not limited to a DSP unit, an ALU (arithmetic logic unit), an FPU (floating point unit), a vector processing unit, a register, and other control units that are mainly responsible for decoding and executing instructions. After receiving the data signal from the data signal input terminal SDI, the data processing unit 10 performs slave initialization settings and selects to enter the short-circuit transmission state or the instruction receiving state.

[0050] like Figure 5 As shown, specifically, the control circuit is provided with two data signal transmission paths, one of which is a short-circuit transmission path, corresponding to the short-circuit transmission state, the short-circuit transmission path is connected to the data processing unit 10 and the data signal output terminal SDO, when the short-circuit transmission path is turned on (i.e., enters the short-circuit transmission state), the signal of the data signal input terminal SDI can be directly output at the data signal output terminal SDO, at which time the data processing unit 10 only receives the data signal but does not execute the instruction of the data signal. The other transmission path is a receiving instruction path, corresponding to the receiving instruction state, the receiving instruction path is connected to the data processing unit 10 and the data signal output terminal SDO, when the instruction receiving path is turned on (i.e., enters the receiving instruction state), after the data processing unit 10 receives the data signal at the data signal input terminal SDI, it performs the necessary execution according to the instruction indicated by the data signal, and then outputs the data signal from the data signal output terminal SDO to the next level (according to the traditional daisy chain transmission).

[0051] When entering the receiving instruction state (the instruction receiving path is turned on), the data processing unit 10 inside the slave decodes the data signal and performs other necessary processing, and then regenerates and amplifies the data signal to ensure the signal quality. The processed data signal is transmitted to the next slave through the data signal output port SDO.

[0052] like Figure 4 As shown, the clock unit 20 is connected to the data signal input terminal SDI of the data signal interface. When the short-circuit transmission state is entered (the short-circuit transmission path is turned on), the clock unit 20 receives data information with a frequency adjustment command sent by the host from the data signal input terminal SDI, and generates a specific clock signal according to the frequency adjustment command. The clock unit 20 is also connected to the counting unit 30.

[0053] like Figure 4As shown, the counting unit 30 is connected to the command signal interface CMD to receive the CMD command signal, and the counting unit 30 is also connected to the data processing unit 10. The counting unit 30 includes but is not limited to timers, counters and other circuits for timing and event counting, such as 555 timers, 74 series counters, etc. The counting unit 30 receives the CMD command signal and counts the characteristic clock signal generated by the clock unit 20 within the pulse period of the CMD command signal, and sends the count value to the data processing unit 10. The data processing unit 10 executes the instruction of the data signal according to the count value, so that the slave enters a specific state, that is, adjusts the LED light controlled by it.

[0054] Specifically, the CMD command signal can be a pulse signal, and the pulse width of the specific clock signal generated by the clock unit 20 is smaller than the pulse width of the CMD command signal. The counting unit 30 is set to start counting the number of pulses of the specific clock signal when the rising edge of the pulse of the CMD command signal arrives (it can also start counting at the falling edge). In some embodiments, when in a short-circuit transmission state (the short-circuit transmission path is turned on) and there are two slaves (the clock units of the two slaves correspond to the clock unit 20-1 and the clock unit 20-2 respectively), the clock unit 20 of each slave will receive the data signal through the data signal input terminal SDI in almost the same time (the frequency adjustment commands indicated for different slaves in the data signal are different or the same, and the following is explained by taking the different frequency adjustment commands of the slaves as an example). Figure 6 As shown, within a pulse period of a CMD command signal, the number of pulses of the specific clock signal generated by the clock unit 20-1 (count value = 10) is different from the number of pulses of the specific clock signal generated by the clock unit 20-2 (count value = 5). The counting unit 30 of each slave will feed back different count values ​​(number of pulses) to their respective data processing units 10. The data processing unit 10 of each slave will execute the instructions in the previously received data signal according to the count values. Due to the difference in count values, the results after execution of each slave are not the same. For example, if one slave represents the LED backlight of one or a group of keyboard keys, two slaves represent the LED backlights of two or two different keyboard keys. Due to the different count values, the two or two groups of keyboard key LED backlights can respectively display different colors or different brightness, thereby achieving keyboard color or brightness adjustment.

[0055] Through the circuit structure of this embodiment, a short-circuit transmission path is set inside the control circuit, and one of the command signal interface or the clock signal interface is used in conjunction with the data signal interface to execute the instructions of the data signal when the short-circuit transmission path is turned on. Only one piece of data information with a frequency adjustment command needs to be configured to achieve differentiated configuration of multiple slaves, without the need to separately configure data information for each (each group) of the LED lights of the buttons for repeated transmission, which greatly reduces the transmission volume of communication data, thereby reducing unnecessary communication problems caused by bandwidth limitations, data delays, data loss, increased energy consumption, etc.

[0056] In some embodiments, the present application also discloses another daisy chain communication control circuit. Compared with the above embodiments, this embodiment provides a more specific clock unit structure.

[0057] like Figure 7 As shown, in this embodiment, the clock unit includes a first internal clock 21 and a frequency conversion unit 22, the first internal clock 21 is electrically connected to the frequency conversion unit 22, and the frequency conversion unit 22 is connected to the data signal input terminal SDI and the counting unit 30. The frequency conversion unit 22 receives data information with a frequency adjustment command in a data signal sent by the host, and generates a specific clock signal based on the clock frequency of the first internal clock 21.

[0058] Specifically, the frequency conversion unit 22 may be a frequency divider or a frequency multiplier. Preferably, the frequency divider is used as an example for explanation. The first internal clock 21 is a default clock frequency set when the chip leaves the factory to ensure that the chip can work normally after power is turned on. Figure 7 and Figure 8 As shown, when entering the short-circuit transmission state (short-circuit transmission path is turned on), the frequency divider (frequency conversion unit 22) receives the data information with the frequency adjustment command sent by the host, and generates a specific clock signal based on the clock frequency of the first internal clock 21 according to the frequency adjustment command (frequency conversion command) indicated by the data information, and the pulse width of the specific clock signal generated by the frequency divider is less than the pulse width of the CMD command signal. Set the clock frequency f of the first internal clock 21 to 20, the frequency conversion coefficient in the frequency adjustment command received by slave 1 is 0.5, and the frequency conversion coefficient in the frequency adjustment command received by slave 2 is 0.25, then the frequency f1 of the specific clock signal generated by the frequency divider of slave 1 is 0.5*f=0.5*20=10; then the frequency f2 of the specific clock signal generated by the frequency divider of slave 2 is 0.25*f=0.25*20=5.

[0059] The counting unit 30 in slave 1 receives the CMD command signal and counts the specific clock signal generated by the frequency divider of slave 1 within the pulse period corresponding to the CMD command signal and sends the count value (count value = 10) to the data processing unit 10 of slave 1; the counting unit 30 in slave 2 receives the CMD command signal and counts the specific clock signal generated by the frequency divider of slave 2 within the pulse period corresponding to the CMD command signal and sends the count value (count value = 5) to the data processing unit 10 of slave 2. Due to the difference in count values, the data processing units 10 of slave 1 and slave 2 will perform differential actions according to the difference in count values. If one slave represents one or a group of LED backlights of keyboard keys, two slaves represent two or two groups of LED backlights of different keyboard keys. Due to the different count values, the two or two groups of keyboard key LED backlights can respectively display different colors or display different brightness, thereby realizing the adjustment of keyboard color or brightness.

[0060] It can be understood that if the frequency conversion unit 22 adopts a frequency multiplier, the pulse width of the specific clock signal generated by the frequency multiplier is smaller than the pulse width of the CMD command signal.

[0061] In the circuit structure of this embodiment, the first internal clock 21 is provided to reduce the dependence on the external clock source, thereby reducing the complexity of the system and potential failure points.

[0062] In some embodiments, the present application further discloses yet another daisy chain communication control circuit. Compared with the previous embodiment, the structure of the clock unit of this embodiment is different.

[0063] like Fig. 9 As shown, in this embodiment, the clock unit includes a frequency conversion unit 22 and a first internal clock. The structure and connection relationship of the frequency conversion unit 22 are the same as those in the above embodiment, and are not repeated here. The first internal clock is a programmable clock 23. The circuit connection relationship of the programmable clock 23 is the same as the connection relationship of the first internal clock 21 in the above embodiment. The programmable clock 23 can be adjusted through register settings or configuration files.

[0064] It can be understood that when the programmable clock 23 is used, the frequency conversion unit 22 receives data information with a frequency adjustment command sent by the host, and generates a specific clock signal based on the clock frequency of the programmable clock 23 according to the frequency adjustment command (frequency conversion command) indicated by the data information, and the pulse width of the specific clock signal generated by the frequency conversion unit 22 is smaller than the pulse width of the CMD command signal.

[0065] In low-power applications, users may need to reduce the clock frequency of the programmable clock 23 to reduce power consumption. In high-performance applications, users may need to increase the clock frequency of the programmable clock 23 to improve processing capabilities. Therefore, the programmable clock 23 can better adapt to different application scenarios, taking into account the needs of power consumption and performance. Moreover, in a system that requires multiple chips (master-slave system or slave system) to work together, clock synchronization is very important, and users can adjust the internal clocks of each slave according to actual needs to achieve synchronization.

[0066] In some embodiments, the present application further discloses another daisy chain communication control circuit. Compared with the above embodiments, the circuit connection of the counting unit 30 is different.

[0067] like Fig.10 and Fig.11 As shown, in this embodiment, the counting unit 30 is connected to the clock signal interface CLK, receives the clock pulse signal (CLK signal) sent by the host, and counts the specific clock signal generated by the clock unit 20 within the pulse period corresponding to the clock pulse signal and sends the count value to the data processing unit 10. The counting unit 30 counts using the pulse period of the clock pulse signal. The pulse width of the specific clock signal generated by the clock unit 20 is smaller than the pulse width of the clock pulse signal. The counting unit 30 is set to start counting the number of pulses of the specific clock signal when the falling edge of the clock pulse signal arrives (it can also start counting at the rising and falling edges), as shown in FIG. Fig.11 As shown, within a pulse period of a clock pulse signal, the number of pulses generated by the clock unit 20-1 is different from the number of pulses generated by the clock unit 20-2. The counting unit 30 of each slave machine will feed back different counting values ​​to their respective data processing units 10. Since there are differences in the counting values, the data processing unit 10 will perform differentiated actions according to the differences in the counting values, thereby achieving adjustment of the keyboard color or brightness.

[0068] In the scheme of this embodiment, one signal interface (command signal interface CMD) of the slave can be reduced. The slave only needs to set three ports: clock signal interface CLK, data signal input terminal SDI, and data signal output terminal SDO. The chip area of ​​the slave cascade chip can be reduced and the cost can be reduced.

[0069] In some embodiments, the present application further discloses another daisy chain communication control circuit, and compared with the above embodiments, the structure of the clock unit is different.

[0070] like Fig.12As shown, in this embodiment, the clock unit includes a timing unit 24 and a frequency conversion unit 22. The structure and connection of the frequency conversion unit 22 are the same as those of some of the above embodiments, and will not be repeated here. The timing unit 24 receives an external clock signal and converts it into a clock signal suitable for internal use to ensure the synchronization and stability of the system. The timing unit 24 includes but is not limited to circuits such as a clock buffer and a clock driver. The timing unit 24 is respectively connected to the clock signal interface CLK and the frequency conversion unit 22. The timing unit 24 receives a clock pulse signal (external clock) sent by the host and generates a second internal clock according to the clock pulse signal. The frequency conversion unit 22 receives data information with a frequency adjustment command in a data signal sent by the host, and generates a specific clock signal based on the clock frequency of the second internal clock.

[0071] The clock frequency of the second internal clock generated by the timing unit 24 receiving the clock pulse signal may be the same as or different from the clock frequency of the clock pulse signal; since each slave receives a different frequency adjustment command, the number of pulses of the specific clock signal generated by the frequency conversion unit 22 (divider) of each slave based on the clock frequency of the second internal clock according to different frequency adjustment commands is also different (within the same pulse period). At this time, the counting unit 30 counts the number of pulses of the specific clock signal generated by the divider according to the pulse period of the CMD command signal and sends the count value to the data processing unit 10. Since there are differences in the count values, the data processing unit 10 will perform differentiated execution of actions according to the differences in the count values, thereby achieving keyboard color or brightness adjustment.

[0072] In some other implementations, the timing unit 24 may not be directly connected to the clock signal interface CLK, but may be connected to the data processing unit 10 to indirectly receive the clock pulse signal sent by the host through the data processing unit 10 .

[0073] In the solution of this embodiment, it is not necessary to set an internal clock for each cascade chip of each slave separately before leaving the factory, thereby reducing the chip area and reducing the cost.

[0074] It should be noted that, in each of the above-mentioned embodiments, the clock unit 20 or the frequency conversion unit 22 receives data information with a frequency adjustment command sent by the host from the data signal input terminal SDI, and generates a specific clock signal according to the frequency adjustment command. In some other embodiments, the clock unit 20 or the frequency conversion unit 22 can also receive data information with a frequency adjustment command from the data processing unit 10, and generate a specific clock signal according to the frequency adjustment command, wherein the data information with the frequency adjustment command can come from the host, and be sent after being processed by the data processing unit, or be directly forwarded to the clock unit 20 or the frequency conversion unit 22 without being processed. The specific form can be flexibly adjusted according to conditions such as data processing speed and number of interfaces.

[0075] In some embodiments, the present application further provides an integrated circuit chip having signal processing capabilities, including a control circuit for daisy chain communication as in any of the above embodiments. The integrated circuit chip may be a keyboard chip (a cascade chip in the above slave), capable of implementing the functions of any of the above embodiments, thereby controlling the brightness and / or color of the LED light of the keyboard. The specific contents of the control function can be found in the description of the above embodiments, and will not be repeated here for the sake of brevity.

[0076] like Figure 3 , Figure 4 As shown, corresponding to the above embodiments, this embodiment provides a daisy chain communication system, which can be a control system of a keyboard and can implement the functions of any of the above embodiments, thereby controlling the brightness and / or color of the LED light of the keyboard.

[0077] In some embodiments, the daisy chain communication system includes:

[0078] A master and at least one slave, the slave being connected to the master via a daisy chain.

[0079] The slave includes: a data signal interface, a data processing unit 10, a clock unit 20, a counting unit 30, and a command signal interface and / or a clock signal interface;

[0080] The clock signal interface is used to receive the clock pulse signal sent by the host;

[0081] The command signal interface is used to receive the CMD command signal sent by the host;

[0082] The data signal interface is connected to the data processing unit 10, and is used to receive the data signal sent by the host and transmit the data signal to the data processing unit 10;

[0083] The data processing unit 10 is connected to the clock signal interface and the data signal interface, performs slave initialization settings after receiving the data signal, and selects to enter the short-circuit transmission state (short-circuit transmission path is turned on) or the receiving instruction state (receiving instruction path is turned on); wherein,

[0084] The short-circuit transmission state is configured to directly output the data signal received from the input end of the data signal interface at the output end;

[0085] The receiving instruction state is configured to execute and output the data signal received from the input end of the data signal interface at the output end;

[0086] When entering the short-circuit transmission state (short-circuit transmission path is turned on):

[0087] The clock unit 20 receives data information with a frequency adjustment command in a data signal sent by the host, and generates a specific clock signal according to the frequency adjustment command;

[0088] The counting unit 30 receives a clock pulse signal or a CMD command signal, counts a specific clock signal within its pulse period and sends the count value to the data processing unit 10. The data processing unit 10 executes the instruction of the data signal according to the count value to make the slave enter a specific state.

[0089] The specific content of this embodiment can be found in the description of the above-mentioned multiple circuit embodiments, and for the sake of brevity, it will not be repeated here.

[0090] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the inventive concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A daisy chain communication control circuit, characterized in that: include: Data signal interface, command signal interface and / or clock signal interface; The clock signal interface is used to receive a clock pulse signal sent by the host; The command signal interface is used to receive a CMD command signal sent by the host; The data signal interface is used to receive or send data signals; The control circuit includes a short-circuit transmission path, which is arranged between the input end and the output end of the data signal interface; When the short-circuit transmission path is turned on: The data signal with the frequency adjustment command is received, and the instruction of the data signal is executed in response to the clock pulse signal or the CMD command signal.

2. The daisy chain communication control circuit according to claim 1, characterized in that: It also includes a data processing unit, a clock unit and a counting unit; The data processing unit is connected to the clock unit and the data signal interface, performs initialization settings after receiving the data signal, and selects to conduct the short-circuit transmission path or the receiving instruction path; When the short-circuit transmission path is turned on, The clock unit receives data information with a frequency adjustment command in the data signal sent by the host, and generates a specific clock signal according to the frequency adjustment command; The counting unit receives a clock pulse signal or a CMD command signal, counts the specific clock signal within its pulse period and sends the count value to the data processing unit, and the data processing unit executes the instruction of the data signal according to the count value.

3. The daisy chain communication control circuit according to claim 2, characterized in that: The clock unit includes a first internal clock and a frequency conversion unit electrically connected to the first internal clock. The frequency conversion unit receives data information with a frequency adjustment command in the data signal sent by the host, and generates the specific clock signal based on the clock frequency of the first internal clock.

4. The daisy chain communication control circuit according to claim 3, characterized in that: The frequency conversion unit includes a frequency divider or a frequency multiplier.

5. The daisy chain communication control circuit according to claim 3, characterized in that: The first internal clock comprises a programmable clock.

6. The daisy chain communication control circuit according to claim 2, characterized in that: The counting unit is connected to the clock signal interface to receive a clock pulse signal, and counts the specific clock signal within a pulse period of the clock pulse signal and sends the count value to the data processing unit.

7. The daisy chain communication control circuit according to claim 2, characterized in that: The counting unit is connected to the command signal interface to receive a CMD command signal, and counts the specific clock signal within a pulse period of the CMD command signal and sends the count value to the data processing unit.

8. The daisy chain communication control circuit according to claim 2, characterized in that: The clock unit includes a timing unit and a frequency conversion unit electrically connected to the timing unit. The timing unit generates a second internal clock according to the clock pulse signal after receiving the clock pulse signal sent by the host. The frequency conversion unit receives data information with a frequency adjustment command in the data signal sent by the host, and generates the specific clock signal based on the clock frequency of the second internal clock.

9. An integrated circuit chip for controlling the brightness and / or color of an indicator light of a keyboard, characterized in that: The invention comprises a daisy chain communication control circuit as claimed in any one of claims 1 to 8.

10. A daisy chain communication system, characterized in that: include: Host; At least one slave, wherein the slave comprises a daisy chain communication control circuit according to any one of claims 1 to 8.

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