A computer

Abstract

The utility model provides a computer, including a power on / off control circuit, the power on / off control circuit including a time-delay reset module and a logic judge. The time-delay reset module includes a reset input terminal and a reset output terminal, the reset input terminal is connected to the shutdown signal output terminal of the south bridge of the computer, and the reset output terminal is connected to the second input terminal of the logic judge. The first input terminal of the logic judge is connected to the power button of the computer, and the output terminal is connected to the key signal input terminal of the south bridge. During the shutdown process of the computer, the south bridge outputs a shutdown signal to the time-delay reset module, so that the time-delay reset module outputs a high-level signal to the logic judge. When the computer completes shutdown and power off, the time-delay reset module outputs a low-level signal to the logic judge after waiting for a preset delay time. The utility model can prevent the user from triggering a key to start the computer when the computer shutdown and power off are not completed, thereby improving the operational safety of the computer.

Description

Technical Field

[0001] The utility model relates to the technical field of computers, and in particular to a computer with a power on / off control circuit. Background Art

[0002] Computers are electronic devices commonly used in people's work and life. With the rapid development of information technology, computers have become more and more widely used.

[0003] Computer timing is the time control of the computer. To ensure that the computer works in an orderly manner, there are strict requirements on the generation time, stabilization time, cancellation time and the relationship between the various operation signals of the computer. In other words, the computer needs strict timing control to ensure its normal operation. Computer timing errors may cause abnormal functions of the computer motherboard.

[0004] At present, computers can use Super IO chips / hardware circuits to achieve power supply and power-on and power-off timing control, and no software control is required in the power on and off process. However, in the existing solutions that only rely on hardware to achieve computer power supply and power-on and power-off timing control, during the computer power on and off process, the user may trigger the shutdown and power on actions continuously in a short period of time. In particular, during the computer shutdown process, when the computer power has not yet been completely powered off, if the computer power button is pressed again, the computer will be triggered to start up again by the power button, which may easily cause the computer to have a timing error, or even cause the motherboard to malfunction.

[0005] Therefore, how to cooperate with the scheme of realizing the power supply and power-on and power-off timing control of the computer through hardware to avoid the user triggering the startup of the computer when the computer power is not completely off is a technical problem that needs to be solved urgently. Summary of the invention

[0006] The utility model aims to provide a computer, which can prevent the user from triggering a key to start the computer when the computer is not completely shut down and power is off by setting a power on / off control circuit, thereby improving the operating safety of the computer.

[0007] To achieve the above-mentioned purpose, the utility model provides a computer, including a power on / off control circuit, the power on / off control circuit including a delayed reset module and a logic judge, the delayed reset module including a reset input end and a reset output end, the logic judge including a first input end, a second input end and an output end, wherein the reset input end is connected to the shutdown signal output end of the south bridge of the computer, and the reset output end is connected to the second input end of the logic judge; the first input end of the logic judge is connected to the power button of the computer, and the output end of the logic judge is connected to the key signal input end of the south bridge; during the shutdown process of the computer, the shutdown signal output end of the south bridge outputs a shutdown signal to the reset input end of the delayed reset module, and the delayed reset module outputs a high level signal to the second input end of the logic judge via the reset output end; when the computer completes shutdown and power off, the delayed reset module outputs a low level signal to the second input end of the logic judge via the reset output end after waiting for a preset delay time.

[0008] Preferably, the shutdown signal is a high-level signal, and when the computer is shut down and powered off, the reset input end of the delayed reset module is converted from receiving the shutdown signal to receiving a low-level signal.

[0009] Preferably, the delayed reset module also includes a voltage monitoring end, which is connected to the standby voltage output end of the power supply of the computer, wherein, when the standby voltage received by the voltage monitoring end from the standby voltage output end is lower than the set voltage, the delayed reset module outputs a high level signal to the second input end of the OR logic judgement; when the standby voltage received by the voltage monitoring end from the standby voltage output end is increased to higher than the set voltage, the delayed reset module outputs a low level signal to the second input end of the OR logic judgement through the reset output end after waiting for the delay time; and when the standby voltage received by the voltage monitoring end remains higher than the set voltage, the computer completes shutdown and power-off, and the delayed reset module outputs a low level signal to the second input end of the OR logic judgement through the reset output end after waiting for the delay time.

[0010] Preferably, the delayed reset module further comprises a power input terminal, and the power input terminal is connected to the standby voltage output terminal of the power supply of the computer.

[0011] Preferably, the delay reset module further includes a time adjustment terminal, and the time adjustment terminal is grounded via a capacitor.

[0012] Preferably, the delayed reset module includes a voltage monitoring chip, a first inverter and a second inverter, wherein the voltage monitoring chip includes a reset signal input terminal and a reset signal output terminal; the input terminal of the first inverter is connected to the shutdown signal output terminal as the reset input terminal of the delayed reset module and is grounded via a first resistor, and the output terminal of the first inverter is connected to the reset signal input terminal of the voltage monitoring chip; the input terminal of the second inverter is connected to the reset signal output terminal of the voltage monitoring chip, and the output terminal of the second inverter is connected to the second input terminal of the OR logic judgement device as the reset output terminal of the delayed reset module.

[0013] Preferably, the voltage monitoring chip also includes a voltage monitoring terminal, a power input terminal and a ground terminal, the voltage monitoring terminal and the power input terminal are connected to the standby voltage output terminal of the power supply of the computer, and the ground terminal is grounded; wherein, when the standby voltage received by the voltage monitoring terminal from the standby voltage output terminal is lower than the set voltage, the voltage monitoring chip outputs a low level signal to the input terminal of the second inverter via the reset signal output terminal; when the standby voltage received by the voltage monitoring terminal from the standby voltage output terminal is increased to be higher than the set voltage, the voltage monitoring chip outputs a high level signal to the input terminal of the second inverter via the reset signal output terminal after waiting for the delay time; and when the standby voltage received by the voltage monitoring terminal remains higher than the set voltage, the computer completes shutdown and power-off, and the voltage monitoring chip outputs a high level signal to the input terminal of the second inverter via the reset signal output terminal after waiting for the delay time.

[0014] Preferably, the voltage monitoring chip further comprises a time adjustment terminal, and the time adjustment terminal is grounded via a capacitor; the delay time is 1.25ms-10s.

[0015] Preferably, the OR logic judger is an OR gate chip, the first input end of the OR logic judger is connected to one end of the power button of the computer and connected to the standby voltage output end of the power supply of the computer via a second resistor, and the other end of the power button is grounded.

[0016] Preferably, the south bridge is a platform path controller, and a universal output interface of the platform path controller serves as the shutdown signal output terminal.

[0017] Beneficial effects of the utility model: the computer of the utility model sets a power on / off control circuit between the power button and the south bridge, and locks the key signal of the power button during the computer shutdown process and for a period of time after the computer completes the shutdown and power-off process, so that it cannot be forwarded to the south bridge of the computer, and the south bridge cannot receive the key signal generated by the power button, thereby prohibiting the computer from responding to the user's key operation, so as to avoid the user pressing the power button and triggering the computer to start up when the power off is not completed during the computer shutdown process, causing the computer to generate a timing error, and even causing the motherboard to function abnormally, thereby improving the operating safety of the computer; Moreover, the computer of the present invention realizes the above functions through the design of a delayed reset circuit and a logic circuit, avoids the out-of-control state of the mainboard, and makes the mainboard work under the designed standard conditions. Therefore, it can cooperate well with the existing scheme of realizing the power supply and power-on and power-off timing control of the computer through hardware. It is not only highly safe, but also widely applicable, and can be applied to various computer hardware platforms such as Loongson / Megacore / Haiguang; at the same time, the power on and off control circuit of the computer of the present invention has high compatibility, and the latch time of the key signal during the shutdown process is adjustable. Therefore, the actual delay time can be adjusted according to different power supply design schemes, and it is compatible with various power supply design schemes. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings are only provided for reference and explanation and are not intended to limit the present invention.

[0019] Figure 1 This is a structural block diagram of a computer power on / off control circuit according to an embodiment of the utility model.

[0020] Figure 2 This is a circuit wiring diagram of a computer power on / off control circuit according to an embodiment of the utility model.

[0021] Figure 3 This is a working diagram of the power on / off control circuit of a computer according to an embodiment of the utility model. DETAILED DESCRIPTION

[0022] In order to further illustrate the technical means and effects adopted by the present invention, the preferred embodiments of the present invention and the accompanying drawings are described in detail below.

[0023] The utility model provides a computer, including a power on / off control circuit 10, such as Figure 1As shown, the power on / off control circuit 10 includes a delayed reset module 11 and a logic judge 12. The delayed reset module 11 includes a reset input terminal 111 and a reset output terminal 112. The logic judge 12 includes a first input terminal 121, a second input terminal 122 and an output terminal 123. Among them, the reset input terminal 111 of the delayed reset module 11 is connected to the shutdown signal output terminal 21 of the south bridge 20 of the computer, and the reset output terminal 112 is connected to the second input terminal 122 of the logic judge 12; the first input terminal 121 of the logic judge 12 is connected to the power button 30 of the computer, and the output terminal 123 is connected to the key signal input terminal 22 of the south bridge 20. During the shutdown process of the computer, the shutdown signal output terminal 21 of the south bridge 20 outputs a shutdown signal to the reset input terminal 111 of the delayed reset module 11, and the delayed reset module 11 outputs a high-level signal to the second input terminal 122 of the OR logic judge 12 via the reset output terminal 112; when the computer completes shutdown and power off, the delayed reset module 11 outputs a low-level signal to the second input terminal 122 of the OR logic judge 12 via the reset output terminal 112 after waiting for a preset delay time.

[0024] Based on the above description, the computer of the present invention sets the power on / off control circuit 10 between the power button 30 and the south bridge 20 , and controls whether the key signal generated by the power button 30 can be transmitted to the south bridge 20 through the power on / off control circuit 10 . Specifically, the power on / off control circuit 10 uses the output signal of the reset output terminal 112 of the delayed reset module 11 and the key signal from the power button 30 of the computer as the two input signals of the OR logic judge 12, and the output signal of the OR logic judge 12 is input into the key signal input terminal 22 of the south bridge 20. That is to say, when the reset output terminal 112 of the delayed reset module 11 outputs a low level signal to the OR logic judge 12, the key signal generated by the power button 30 can be normally sent to the key signal input terminal 22 of the south bridge 20 via the OR logic judge 12, and the south bridge 20 normally receives the key signal generated by the power button 30; when the reset output terminal 112 of the delayed reset module 11 outputs a high level signal to the OR logic judge 12, the key signal generated by the power button 30 is latched and cannot be forwarded to the south bridge 20, so the south bridge 20 cannot receive the key signal generated by the power button 30.

[0025] On this basis, during the shutdown process of the computer, the shutdown signal output terminal 21 of the south bridge 20 outputs a shutdown signal to the delayed reset module 11, and the delayed reset module 11 outputs a high level signal to the second input terminal 122 of the OR logic judge 12 via its reset output terminal 112; when the computer completes shutdown and power off, the delayed reset module 11 outputs a low level signal to the second input terminal 122 of the OR logic judge 12 via the reset output terminal 112 after waiting for a preset delay time.

[0026] Since when the computer is shutting down, when the software executes the last node of the shutdown instruction, the south bridge 20 generates a shutdown signal and starts the hardware shutdown process; when the computer completes the shutdown and power-off, the south bridge 20 stops outputting the shutdown signal. Therefore, the power on / off control circuit 10 can latch the key signal of the power button 30 from the start of the hardware shutdown process to the end of the computer shutdown process and a period of time thereafter (preset delay time), and stop forwarding the key signal to the south bridge 20, thereby prohibiting the computer from responding to user key operations during the entire shutdown process (including the delay time), so as to avoid the user pressing the power button and triggering the computer to start up when the computer power off is not completed, thereby avoiding the use scenario where the computer works under abnormal conditions.

[0027] After the computer is shut down and powered off for a period of time (preset delay time), the delayed reset module 11 outputs a low-level signal to the second input terminal 122 of the OR logic judge 12 via the reset output terminal 112, unlocking the power button 30. The key signal generated by the power button 30 can be normally sent to the key signal input terminal 22 of the south bridge 20, and the south bridge 20 normally receives the key signal generated by the power button 30, so that the user can normally turn on the computer through the power button 30.

[0028] Specifically, the shutdown signal outputted by the shutdown signal output terminal 21 of the south bridge 20 is a high-level signal. When the computer is shut down and powered off, the shutdown signal output terminal 21 of the south bridge 20 stops outputting the shutdown signal, and the reset input terminal 111 of the delay reset module 11 is converted from receiving a high-level shutdown signal to receiving a low-level signal. For example, the shutdown signal outputted by the shutdown signal output terminal 21 of the south bridge 20 can be converted to output a low-level signal to the reset input terminal 111 of the delay reset module 11 through a pull-down resistor.

[0029] Furthermore, the delayed reset module 11 also includes a voltage monitoring terminal 113, and the voltage monitoring terminal 113 is connected to the standby voltage output terminal VCC Standby of the power supply 40 of the computer, wherein: when the standby voltage received by the voltage monitoring terminal 113 from the standby voltage output terminal VCC Standby is lower than the set voltage, the delayed reset module 11 outputs a high level signal to the second input terminal 122 of the OR logic judge 12; when the standby voltage received by the voltage monitoring terminal 113 from the standby voltage output terminal VCC Standby is increased to higher than the set voltage, the delayed reset module 11 outputs a low level signal to the second input terminal 122 of the OR logic judge 12 through the reset output terminal 112 after waiting for the delay time.

[0030] In this way, the power on / off control circuit 10 allows the key signal generated by the power button 30 to be sent to the south bridge only when it is detected that the standby voltage provided by the power supply 40 meets the set voltage requirement. When it is detected that the standby voltage provided by the power supply 40 does not meet the set voltage requirement, the key signal generated by the power button 30 is latched, and the south bridge 20 cannot receive the key signal generated by the power button 30, thereby prohibiting the user from operating the computer when the power supply is at a non-standard level, so as to ensure the normal working conditions of the computer. In one embodiment, the set voltage is 2.93V.

[0031] Specifically, when the computer is working normally, when the reset input terminal 111 of the delay reset module 11 receives the shutdown signal output by the shutdown signal output terminal 21 of the south bridge 20, the high level signal is immediately output to the second input terminal 122 of the OR logic judge 12 through the reset output terminal 112, and the key signal generated by the power button 30 is latched. If the standby voltage received by the voltage monitoring terminal 113 remains higher than the set voltage, the computer completes shutdown and power-off, that is, the reset input terminal 111 of the delay reset module 11 changes from receiving the shutdown signal to receiving a low level signal, then the delay reset module 11 outputs a low level signal to the second input terminal 122 of the OR logic judge 12 through the reset output terminal 112 after waiting for the delay time. In other words, when the computer completes shutdown and power-off when there is still the standby voltage that meets the requirements, the power on / off control circuit 10 restores the path for the power button 30 to send the key signal to the south bridge 20 after waiting for the delay time.

[0032] Furthermore, the delayed reset module 11 further includes a power input terminal 114 , which is connected to a standby voltage output terminal VCC Standby of a power supply 40 of the computer, and is used to receive a standby voltage from the power supply 40 to ensure normal operation.

[0033] Furthermore, the delay reset module 11 further includes a time adjustment terminal 115, and the time adjustment terminal 115 can be grounded via a capacitor. By adjusting the capacitor, the preset delay time of the delay reset module 11 can be adjusted. In a preferred embodiment, the delay time can be preset to 1.25ms-10s.

[0034] like Figure 2 As shown, in a preferred embodiment of the computer power on / off control circuit 10 of the utility model, the delayed reset module 11 may include a voltage monitoring chip U1, a first inverter U3 and a second inverter U4. Among them, the voltage monitoring chip U1 includes a reset signal input terminal nMR and a reset signal output terminal nRESET. The input terminal of the first inverter U3 serves as the reset input terminal 111 of the delayed reset module 11, connected to the shutdown signal output terminal 21 of the south bridge 20 of the computer, and grounded through the first resistor R1; the output terminal of the first inverter U3 is connected to the reset signal input terminal nMR of the voltage monitoring chip U1. The input terminal of the second inverter U4 is connected to the reset signal output terminal nRESET of the voltage monitoring chip U1, and the output terminal of the second inverter U4 serves as the reset output terminal 112 of the delayed reset module 11, connected to the second input terminal 122 of the OR logic judgement device 12.

[0035] The voltage monitoring chip U1 further includes a voltage monitoring terminal SENSE and a power input terminal VDD, wherein the voltage monitoring terminal SENSE and the power input terminal VDD are connected to a standby voltage output terminal VCC Standby of the computer power supply 40. The voltage monitoring terminal SENSE of the voltage monitoring chip U1 is the voltage monitoring terminal 113 of the delay reset module 11, and the power input terminal VDD is the power input terminal 114 of the delay reset module 11.

[0036] Among them, when the standby voltage received by the voltage monitoring terminal SENSE from the standby voltage output terminal VCCStandby of the power supply 40 of the computer is lower than the set voltage, the voltage monitoring chip U1 outputs a low level signal to the input terminal of the second inverter U4 through its reset signal output terminal nRESET; when the standby voltage received by the voltage monitoring terminal SENSE from the standby voltage output terminal VCC Standby of the power supply 40 of the computer is increased to higher than the set voltage, the voltage monitoring chip U1 outputs a high level signal to the input terminal of the second inverter U4 through its reset signal output terminal nRESET after waiting for the delay time. Moreover, when the standby voltage received by the voltage monitoring terminal SENSE from the standby voltage output terminal VCC Standby remains higher than the set voltage, the computer completes shutdown and power-off, that is, the first inverter U3 converts from receiving the shutdown signal of the south bridge 20 of the computer to receiving a low level signal, and the voltage monitoring chip U1 outputs a high level signal to the input terminal of the second inverter U4 through its reset signal output terminal nRESET after waiting for the delay time.

[0037] The voltage monitoring chip U1 also includes a time adjustment terminal CT, which is grounded via a capacitor C1. The time adjustment terminal CT of the voltage monitoring chip U1 is the time adjustment terminal 115 of the delay reset module 11. By adjusting the capacitor C1, the preset delay time of the delay reset module 11 can be adjusted.

[0038] In a preferred embodiment, the delay time t delay It can be determined by the following formula:

[0039] t delay (μs) = (5.58 × 10 6 ) × C1 (μF) + 520 (μs).

[0040] In a preferred embodiment, the delay time t delay Can be preset to 1.25ms-10s.

[0041] The voltage monitoring chip U1 further includes a ground terminal GND, and the ground terminal GND is grounded.

[0042] Furthermore, the OR logic determiner 12 is an OR gate chip U2, the B end of the OR gate chip U2 is a first input end 121, connected to one end of the power button 30 of the computer and connected to the standby voltage output end VCC Standby of the power supply 40 of the computer via a second resistor R2, and the other end of the power button 30 is grounded; the A end of the OR gate chip U2 is a second input end 122, connected to the output end of the second inverter U4.

[0043] The south bridge 20 is a platform path controller PCH, a general output interface GPO1 of the platform path controller PCH serves as the shutdown signal output terminal 21 , and a key signal input terminal ACPI_PWRBTN of the platform path controller PCH serves as the key signal input terminal 22 .

[0044] Figure 2 When the power on / off control circuit 10 shown is working, when the standby voltage provided by the standby voltage output terminal VCC Standby of the power supply 40 of the computer to the voltage monitoring terminal SENSE of the voltage monitoring chip U1 is lower than the set voltage such as 2.93V, the reset signal output terminal nRESET of the voltage monitoring chip U1 provides a low level signal to the second inverter U4, and the second inverter U4 outputs a high level signal to the A terminal of the OR gate chip U2, latching the key signal generated by the power button 30, and the south bridge 20 cannot receive the key signal generated by the power button 30, thereby prohibiting the user from operating the computer when the power supply is at a non-standard level.

[0045] When the standby voltage provided by the standby voltage output terminal VCC Standby of the power supply 40 of the computer to the voltage monitoring terminal SENSE of the voltage monitoring chip U1 is increased to a value higher than the set voltage, such as 2.93V, the voltage monitoring chip U1 waits for the preset delay time t delay Afterwards, the reset signal output terminal nRESET provides a high level signal to the input terminal of the second inverter U4, and the second inverter U4 outputs a low level signal to the A terminal of the OR gate chip U2, and the key signal generated by the power button 30 can be normally sent to the south bridge 20 via the OR gate chip U2. At this time, the computer can enter the power-on state according to the key signal generated by the power button 30.

[0046] Please also refer to Figure 3As shown, when the computer is turned on and during the boot process, the general output interface GPO1 of the south bridge 20 of the computer outputs a low-level signal to the first inverter U3, the first inverter U3 outputs a high-level signal to the voltage monitoring chip U1, the voltage monitoring chip U1 outputs a high-level signal to the second inverter U4, the RST signal output by the second inverter U4 to the A end of the OR gate chip U2 is a low-level signal, and the key signal PWRBTN generated by the power button 30 can be normally sent to the key signal input terminal ACPI_PWRBTN of the south bridge 20.

[0047] During this process, if the user presses the power button 30 and the pressing time t is greater than a certain time, such as 4 seconds, the computer is triggered to enter the shutdown process; if the pressing time t is less than the time, such as 4 seconds, the power menu will be triggered.

[0048] When the computer enters the shutdown process and the software executes the last node of the shutdown command, the south bridge 20 generates a high-level shutdown signal, that is, its general output interface GPO1 outputs a high-level signal to the first inverter U3, the first inverter U3 outputs a low-level signal to the voltage monitoring chip U1, the voltage monitoring chip U1 outputs a low-level signal to the second inverter U4, the second inverter U4 outputs the RST signal of the A terminal of the OR gate chip U2 as a high-level signal, and the key signal input terminal ACPI_PWRBTN of the south bridge 20 maintains a high-level signal. That is, the OR gate chip U2 latches the key signal generated by the power button 30, stops forwarding the key signal to the south bridge 20, and the south bridge 20 cannot receive the key signal generated by the power button 30, and does not respond to the key signal generated by the user pressing the power button 30, thereby prohibiting the user from operating the computer during the shutdown process.

[0049] When the computer is shut down and powered off, the general output interface GPO1 of the south bridge 20 stops outputting a high level signal, the level signal of the general output interface GPO1 is converted into a low level signal by the first resistor R1, and the reset signal input terminal nMR of the voltage monitoring chip U1 receives a high level signal, but the voltage monitoring chip U1 waits for the preset delay time t delay After that (waiting time t1 is greater than delay time t delay ), only then the reset signal output terminal nRESET provides a high level signal to the input terminal of the second inverter U4. When the second inverter U4 receives the high level signal provided by the voltage monitoring chip U1, it outputs a low level signal to the A terminal of the OR gate chip U2, and the key signal generated by the power button 30 can be sent to the south bridge 20 normally. Afterwards, the computer can enter the power-on state according to the key signal generated by the power button 30.

[0050] That is to say, after the computer completes the shutdown and power-off procedure, the delay time t is further delayed. delay , the south bridge 20 is allowed to receive the key signal and start up normally.

[0051] In one embodiment, the voltage monitoring chip U1 is a voltage monitoring chip with controllable delay, which can be a voltage monitoring chip of the SGM836 series, such as SGM836-3.3XN6G / TR, but not limited thereto. In one embodiment, the model of the OR gate chip U2 can be RS1G32XC5, but not limited thereto.

[0052] In summary, the computer of the present invention sets a power on / off control circuit between the power button and the south bridge, and locks the key signal of the power button during the computer shutdown process and for a period of time after the computer completes the shutdown and power-off process, so that it cannot be forwarded to the south bridge of the computer. The south bridge cannot receive the key signal generated by the power button, thereby prohibiting the computer from responding to the user's key operation, so as to avoid the user pressing the power button and triggering the computer to start up when the power off is not completed during the computer shutdown process, causing the computer to generate a timing error, and even causing the motherboard to malfunction, thereby improving the computer's operational safety; moreover, the present invention The computer of the utility model realizes the above functions through the design of a delayed reset circuit and a logic circuit, avoids the out-of-control state of the mainboard, and makes the mainboard work under the designed standard conditions. Therefore, it can cooperate well with the existing scheme of realizing the power supply and power-on and power-off timing control of the computer through hardware. It is not only highly safe, but also widely applicable, and can be applied to various computer hardware platforms such as Loongson / Megacore / Haiguang; at the same time, the power on and off control circuit of the computer of the utility model has high compatibility, and the latch time of the key signal during the shutdown process is adjustable. Therefore, the actual delay time can be adjusted according to different power supply design schemes, and it is compatible with various power supply design schemes.

[0053] As described above, for ordinary technicians in this field, various other corresponding changes and modifications can be made according to the technical scheme and technical concept of the utility model, and all these changes and modifications should fall within the protection scope of the claims of the utility model.

Claims

1. A computer, characterized in that: The invention comprises a power on / off control circuit, wherein the power on / off control circuit comprises a time delay reset module and a logic judge, wherein the time delay reset module comprises a reset input terminal and a reset output terminal, and the logic judge comprises a first input terminal, a second input terminal and an output terminal, wherein the reset input terminal is connected to a shutdown signal output terminal of the south bridge of the computer, and the reset output terminal is connected to the second input terminal of the logic judge; the first input terminal of the logic judge is connected to a power button of the computer, and the output terminal of the logic judge is connected to a key signal input terminal of the south bridge; during the shutdown process of the computer, the shutdown signal output terminal of the south bridge outputs a shutdown signal to the reset input terminal of the time delay reset module, and the time delay reset module outputs a high level signal to the second input terminal of the logic judge via the reset output terminal; when the computer completes shutdown and power off, the time delay reset module outputs a low level signal to the second input terminal of the logic judge via the reset output terminal after waiting for a preset delay time.

2. The computer according to claim 1, characterized in that The shutdown signal is a high-level signal. When the computer is shut down and powered off, the reset input terminal of the delayed reset module is converted from receiving the shutdown signal to receiving a low-level signal.

3. The computer according to claim 1 or 2, characterized in that: The delayed reset module also includes a voltage monitoring end, which is connected to the standby voltage output end of the power supply of the computer, wherein, when the standby voltage received by the voltage monitoring end from the standby voltage output end is lower than the set voltage, the delayed reset module outputs a high-level signal to the second input end of the OR logic judgement; when the standby voltage received by the voltage monitoring end from the standby voltage output end is increased to higher than the set voltage, the delayed reset module outputs a low-level signal to the second input end of the OR logic judgement through the reset output end after waiting for the delay time; and when the standby voltage received by the voltage monitoring end remains higher than the set voltage, the computer completes shutdown and power-off, and the delayed reset module outputs a low-level signal to the second input end of the OR logic judgement through the reset output end after waiting for the delay time.

4. The computer according to claim 3, characterized in that The delayed reset module further includes a power input terminal, and the power input terminal is connected to the standby voltage output terminal of the power supply of the computer.

5. The computer according to claim 1, characterized in that The delay reset module also includes a time adjustment terminal, and the time adjustment terminal is grounded via a capacitor.

6. The computer according to claim 1 or 2, characterized in that: The delayed reset module includes a voltage monitoring chip, a first inverter and a second inverter, wherein the voltage monitoring chip includes a reset signal input terminal and a reset signal output terminal; the input terminal of the first inverter is connected to the shutdown signal output terminal as the reset input terminal of the delayed reset module and is grounded via a first resistor, and the output terminal of the first inverter is connected to the reset signal input terminal of the voltage monitoring chip; the input terminal of the second inverter is connected to the reset signal output terminal of the voltage monitoring chip, and the output terminal of the second inverter is connected to the second input terminal of the OR logic judgement device as the reset output terminal of the delayed reset module.

7. The computer according to claim 6, characterized in that The voltage monitoring chip also includes a voltage monitoring terminal, a power input terminal and a ground terminal, wherein the voltage monitoring terminal and the power input terminal are connected to the standby voltage output terminal of the power supply of the computer, and the ground terminal is grounded; wherein, when the standby voltage received by the voltage monitoring terminal from the standby voltage output terminal is lower than the set voltage, the voltage monitoring chip outputs a low-level signal to the input terminal of the second inverter via the reset signal output terminal; when the standby voltage received by the voltage monitoring terminal from the standby voltage output terminal is increased to be higher than the set voltage, the voltage monitoring chip outputs a high-level signal to the input terminal of the second inverter via the reset signal output terminal after waiting for the delay time; and when the standby voltage received by the voltage monitoring terminal remains higher than the set voltage, the computer completes shutdown and power-off, and the voltage monitoring chip outputs a high-level signal to the input terminal of the second inverter via the reset signal output terminal after waiting for the delay time.

8. The computer according to claim 6, characterized in that The voltage monitoring chip also includes a time adjustment terminal, which is grounded via a capacitor; the delay time is 1.25ms-10s.

9. The computer according to claim 1, wherein: The OR logic judger is an OR gate chip, the first input end of the OR logic judger is connected to one end of the power button of the computer and connected to the standby voltage output end of the power supply of the computer through a second resistor, and the other end of the power button is grounded.

10. The computer according to claim 1, wherein: The south bridge is a platform path controller, and a universal output interface of the platform path controller serves as the shutdown signal output terminal.

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